diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/long/fs/10.linux-boot/ref/arm | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
6 files changed, 9756 insertions, 8406 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 5c2619e22..8cfdfc3f7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,132 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.524310 # Number of seconds simulated -sim_ticks 2524309551500 # Number of ticks simulated -final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525141 # Number of seconds simulated +sim_ticks 2525141046500 # Number of ticks simulated +final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55803 # Simulator instruction rate (inst/s) -host_op_rate 71803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2335855340 # Simulator tick rate (ticks/s) -host_mem_usage 401408 # Number of bytes of host memory used -host_seconds 1080.68 # Real time elapsed on the host -sim_insts 60305560 # Number of instructions simulated -sim_ops 77596391 # Number of ops (including micro ops) simulated +host_inst_rate 50522 # Simulator instruction rate (inst/s) +host_op_rate 65007 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2115457252 # Simulator tick rate (ticks/s) +host_mem_usage 427804 # Number of bytes of host memory used +host_seconds 1193.66 # Real time elapsed on the host +sim_insts 60305756 # Number of instructions simulated +sim_ops 77596741 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory -system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 966197440 # Total number of bytes read from memory -system.physmem.bytesWritten 52040704 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2524308440000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14942208 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154591 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754018 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59118 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096843 # Number of read requests accepted +system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue +system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943582 # Per bank write bursts +system.physmem.perBankRdBursts::1 943145 # Per bank write bursts +system.physmem.perBankRdBursts::2 939291 # Per bank write bursts +system.physmem.perBankRdBursts::3 939307 # Per bank write bursts +system.physmem.perBankRdBursts::4 943115 # Per bank write bursts +system.physmem.perBankRdBursts::5 943141 # Per bank write bursts +system.physmem.perBankRdBursts::6 939138 # Per bank write bursts +system.physmem.perBankRdBursts::7 938546 # Per bank write bursts +system.physmem.perBankRdBursts::8 943996 # Per bank write bursts +system.physmem.perBankRdBursts::9 943390 # Per bank write bursts +system.physmem.perBankRdBursts::10 938426 # Per bank write bursts +system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.perBankRdBursts::12 943928 # Per bank write bursts +system.physmem.perBankRdBursts::13 943533 # Per bank write bursts +system.physmem.perBankRdBursts::14 939234 # Per bank write bursts +system.physmem.perBankRdBursts::15 938672 # Per bank write bursts +system.physmem.perBankWrBursts::0 6704 # Per bank write bursts +system.physmem.perBankWrBursts::1 6457 # Per bank write bursts +system.physmem.perBankWrBursts::2 6598 # Per bank write bursts +system.physmem.perBankWrBursts::3 6635 # Per bank write bursts +system.physmem.perBankWrBursts::4 6561 # Per bank write bursts +system.physmem.perBankWrBursts::5 6794 # Per bank write bursts +system.physmem.perBankWrBursts::6 6789 # Per bank write bursts +system.physmem.perBankWrBursts::7 6723 # Per bank write bursts +system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankWrBursts::9 6877 # Per bank write bursts +system.physmem.perBankWrBursts::10 6538 # Per bank write bursts +system.physmem.perBankWrBursts::11 6183 # Per bank write bursts +system.physmem.perBankWrBursts::12 7149 # Per bank write bursts +system.physmem.perBankWrBursts::13 6765 # Per bank write bursts +system.physmem.perBankWrBursts::14 7038 # Per bank write bursts +system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 36 # Read request sizes (log2) +system.physmem.readPktSize::3 14942208 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 154599 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 59125 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -140,294 +142,604 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation -system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests -system.physmem.totBusLat 75453215000 # Total cycles spent in databus access -system.physmem.totBankLat 15307050000 # Total cycles spent in bank access -system.physmem.avgQLat 19314.15 # Average queueing delay per request -system.physmem.avgBankLat 1014.34 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25328.49 # Average memory access latency -system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 14.41 # Average write queue length over time -system.physmem.readRowHits 15065383 # Number of row buffer hits during reads -system.physmem.writeRowHits 94229 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes -system.physmem.avgGap 158662.04 # Average gap between requests +system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 84 0.10% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 98 0.11% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 5 0.01% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 17 0.02% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 80 0.09% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 74 0.09% 71.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 645 0.75% 72.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 72 0.08% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 78 0.09% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 28 0.03% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 5 0.01% 72.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 407 0.47% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 18 0.02% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 3 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 147 0.17% 73.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 144 0.17% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 279 0.32% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 73 0.08% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 77 0.09% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 5 0.01% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 263 0.31% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 82 0.10% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 140 0.16% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 343 0.40% 74.89% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 73 0.08% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 83 0.10% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 83 0.10% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 387 0.45% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 78 0.09% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.80% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 78 0.09% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 401 0.47% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 2 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 82 0.10% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 77 0.09% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 15 0.02% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 403 0.47% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 11 0.01% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 83 0.10% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 97 0.11% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 341 0.40% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 143 0.17% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 77 0.09% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 85 0.10% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 2 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 268 0.31% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 76 0.09% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 74 0.09% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 2 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 271 0.31% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 145 0.17% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 148 0.17% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 4 0.00% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 398 0.46% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 18 0.02% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 78 0.09% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 83 0.10% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 642 0.75% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 73 0.08% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 78 0.09% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 27 0.03% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 406 0.47% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 16 0.02% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 144 0.17% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 147 0.17% 84.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 269 0.31% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 87 0.10% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 72 0.08% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 2 0.00% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 77 0.09% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 268 0.31% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 81 0.09% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 77 0.09% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 1 0.00% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 144 0.17% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 2 0.00% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 338 0.39% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 1 0.00% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 91 0.11% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 83 0.10% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 11 0.01% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 404 0.47% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 15 0.02% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 77 0.09% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 84 0.10% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 401 0.47% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation +system.physmem.totQLat 365610387500 # Total ticks spent queuing +system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks +system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing +system.physmem.readRowHits 14986740 # Number of row buffer hits during reads +system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes +system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -440,50 +752,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54917647 # Throughput (bytes/s) +system.membus.throughput 54899945 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16149440 # Transaction distribution system.membus.trans_dist::ReadResp 16149440 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59118 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution -system.membus.trans_dist::ReadExReq 131433 # Transaction distribution -system.membus.trans_dist::ReadExResp 131433 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 59125 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution +system.membus.trans_dist::ReadExReq 131442 # Transaction distribution +system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138629141 # Total data (bytes) +system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630105 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -491,13 +803,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48301509 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution +system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution system.iobus.trans_dist::WriteResp 8157 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -519,12 +831,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -546,14 +858,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121927961 # Total data (bytes) +system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121927965 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -599,41 +911,41 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14390442 # Number of BP lookups -system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits +system.cpu.branchPred.lookups 14384905 # Number of BP lookups +system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14986742 # DTB read hits -system.cpu.checker.dtb.read_misses 7308 # DTB read misses -system.cpu.checker.dtb.write_hits 11227334 # DTB write hits -system.cpu.checker.dtb.write_misses 2189 # DTB write misses +system.cpu.checker.dtb.read_hits 14986852 # DTB read hits +system.cpu.checker.dtb.read_misses 7306 # DTB read misses +system.cpu.checker.dtb.write_hits 11227410 # DTB write hits +system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994050 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229523 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994158 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229601 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26214076 # DTB hits +system.cpu.checker.dtb.hits 26214262 # DTB hits system.cpu.checker.dtb.misses 9497 # DTB misses -system.cpu.checker.dtb.accesses 26223573 # DTB accesses -system.cpu.checker.itb.inst_hits 61479547 # ITB inst hits +system.cpu.checker.dtb.accesses 26223759 # DTB accesses +system.cpu.checker.itb.inst_hits 61479743 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -650,36 +962,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61484018 # ITB inst accesses -system.cpu.checker.itb.hits 61479547 # DTB hits +system.cpu.checker.itb.inst_accesses 61484214 # ITB inst accesses +system.cpu.checker.itb.hits 61479743 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61484018 # DTB accesses -system.cpu.checker.numCycles 77882185 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61484214 # DTB accesses +system.cpu.checker.numCycles 77882535 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51188083 # DTB read hits -system.cpu.dtb.read_misses 64353 # DTB read misses -system.cpu.dtb.write_hits 11697459 # DTB write hits -system.cpu.dtb.write_misses 15788 # DTB write misses +system.cpu.dtb.read_hits 51179212 # DTB read hits +system.cpu.dtb.read_misses 64531 # DTB read misses +system.cpu.dtb.write_hits 11698539 # DTB write hits +system.cpu.dtb.write_misses 15837 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6547 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6568 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51252436 # DTB read accesses -system.cpu.dtb.write_accesses 11713247 # DTB write accesses +system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51243743 # DTB read accesses +system.cpu.dtb.write_accesses 11714376 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62885542 # DTB hits -system.cpu.dtb.misses 80141 # DTB misses -system.cpu.dtb.accesses 62965683 # DTB accesses -system.cpu.itb.inst_hits 11520428 # ITB inst hits -system.cpu.itb.inst_misses 11439 # ITB inst misses +system.cpu.dtb.hits 62877751 # DTB hits +system.cpu.dtb.misses 80368 # DTB misses +system.cpu.dtb.accesses 62958119 # DTB accesses +system.cpu.itb.inst_hits 11513998 # ITB inst hits +system.cpu.itb.inst_misses 11344 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -688,114 +1000,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4968 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4962 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11531867 # ITB inst accesses -system.cpu.itb.hits 11520428 # DTB hits -system.cpu.itb.misses 11439 # DTB misses -system.cpu.itb.accesses 11531867 # DTB accesses -system.cpu.numCycles 473080437 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11525342 # ITB inst accesses +system.cpu.itb.hits 11513998 # DTB hits +system.cpu.itb.misses 11344 # DTB misses +system.cpu.itb.accesses 11525342 # DTB accesses +system.cpu.numCycles 474882944 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available @@ -823,13 +1135,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -842,397 +1154,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued -system.cpu.iq.rate 0.259812 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued +system.cpu.iq.rate 0.258795 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221034 # number of nop insts executed -system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed -system.cpu.iew.exec_branches 11474602 # Number of branches executed -system.cpu.iew.exec_stores 12209197 # Number of stores executed -system.cpu.iew.exec_rate 0.255417 # Inst execution rate -system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47030253 # num instructions producing a value -system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value +system.cpu.iew.exec_nop 221869 # number of nop insts executed +system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475076 # Number of branches executed +system.cpu.iew.exec_stores 12210518 # Number of stores executed +system.cpu.iew.exec_rate 0.254424 # Inst execution rate +system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47026181 # num instructions producing a value +system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60455941 # Number of instructions committed -system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456137 # Number of instructions committed +system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385481 # Number of memory references committed -system.cpu.commit.loads 15653838 # Number of loads committed -system.cpu.commit.membars 403568 # Number of memory barriers committed -system.cpu.commit.branches 9961054 # Number of branches committed +system.cpu.commit.refs 27385736 # Number of memory references committed +system.cpu.commit.loads 15654008 # Number of loads committed +system.cpu.commit.membars 403573 # Number of memory barriers committed +system.cpu.commit.branches 9961077 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852229 # Number of committed integer instructions. -system.cpu.commit.function_calls 991205 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. +system.cpu.commit.function_calls 991208 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239241509 # The number of ROB reads -system.cpu.rob.rob_writes 195965670 # The number of ROB writes -system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305560 # Number of Instructions Simulated -system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated -system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547265504 # number of integer regfile reads -system.cpu.int_regfile_writes 87536110 # number of integer regfile writes -system.cpu.fp_regfile_reads 8349 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads -system.cpu.misc_regfile_writes 831835 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution +system.cpu.rob.rob_reads 240636318 # The number of ROB reads +system.cpu.rob.rob_writes 195934369 # The number of ROB writes +system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305756 # Number of Instructions Simulated +system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated +system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547208472 # number of integer regfile reads +system.cpu.int_regfile_writes 87526189 # number of integer regfile writes +system.cpu.fp_regfile_reads 8624 # number of floating regfile reads +system.cpu.fp_regfile_writes 3008 # number of floating regfile writes +system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.misc_regfile_writes 831837 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 979660 # number of replacements -system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits -system.cpu.icache.overall_hits::total 10456897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses -system.cpu.icache.overall_misses::total 1059959 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked +system.cpu.icache.tags.replacements 980741 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits +system.cpu.icache.overall_hits::total 10449649 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses +system.cpu.icache.overall_misses::total 1060761 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79476 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981285 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981285 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981285 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981285 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64363 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1353,161 +1665,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643614 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits -system.cpu.dcache.overall_hits::total 21018772 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses -system.cpu.dcache.overall_misses::total 3700946 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits +system.cpu.dcache.overall_hits::total 21010251 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses +system.cpu.dcache.overall_misses::total 3701471 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks -system.cpu.dcache.writebacks::total 607864 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks +system.cpu.dcache.writebacks::total 607699 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1529,10 +1841,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 99b249a14..22f0dd0ff 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,154 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.104038 # Number of seconds simulated -sim_ticks 1104038330000 # Number of ticks simulated -final_tick 1104038330000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.104766 # Number of seconds simulated +sim_ticks 1104765949000 # Number of ticks simulated +final_tick 1104765949000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65967 # Simulator instruction rate (inst/s) -host_op_rate 84921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1182267512 # Simulator tick rate (ticks/s) -host_mem_usage 404512 # Number of bytes of host memory used -host_seconds 933.83 # Real time elapsed on the host -sim_insts 61602211 # Number of instructions simulated -sim_ops 79302243 # Number of ops (including micro ops) simulated +host_inst_rate 62642 # Simulator instruction rate (inst/s) +host_op_rate 80640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1123477436 # Simulator tick rate (ticks/s) +host_mem_usage 430892 # Number of bytes of host memory used +host_seconds 983.35 # Real time elapsed on the host +sim_insts 61598253 # Number of instructions simulated +sim_ops 79296895 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 410368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory -system.physmem.bytes_read::total 59194084 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 410368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 816192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267200 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 408192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4366132 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 406848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5251248 # Number of bytes read from this memory +system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 408192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4268480 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7294544 # Number of bytes written to this memory +system.physmem.bytes_written::total 7295824 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257998 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66675 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6378 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68293 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6357 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82077 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66695 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823511 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44164032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 696 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823531 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44134945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 371697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3955272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4755646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53615968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 371697 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 739279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3865083 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2726666 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6607147 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3865083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44164032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 369483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3952088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 368266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4753267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53579613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 369483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 368266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 737749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3863696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6603954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3863696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44134945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 371697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3970670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7482313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60223116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257998 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 823511 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 6257998 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 823511 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 400511872 # Total number of bytes read from memory -system.physmem.bytesWritten 52704704 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59194084 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7294544 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 4191 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 12574 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391107 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391051 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 391031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 390511 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391821 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 391470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 391242 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 390250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 391418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 389084 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 390982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 391146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 389937 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7175 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7320 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7294 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7815 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7419 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7389 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7204 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7511 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7529 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6626 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7294 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7205 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1104037196000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 6094848 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163045 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 756836 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66675 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 510579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 438231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 410611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1497375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1129368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1114937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1085131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 10318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 12945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.bw_total::cpu0.inst 369483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3967476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 368266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7478138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60183567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257980 # Number of read requests accepted +system.physmem.writeReqs 823531 # Number of write requests accepted +system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 823531 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 398200448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2310272 # Total number of bytes read from write queue +system.physmem.bytesWritten 7402624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7295824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 36098 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707850 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12605 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 391110 # Per bank write bursts +system.physmem.perBankRdBursts::1 390863 # Per bank write bursts +system.physmem.perBankRdBursts::2 386866 # Per bank write bursts +system.physmem.perBankRdBursts::3 386878 # Per bank write bursts +system.physmem.perBankRdBursts::4 391778 # Per bank write bursts +system.physmem.perBankRdBursts::5 391417 # Per bank write bursts +system.physmem.perBankRdBursts::6 386925 # Per bank write bursts +system.physmem.perBankRdBursts::7 386783 # Per bank write bursts +system.physmem.perBankRdBursts::8 391442 # Per bank write bursts +system.physmem.perBankRdBursts::9 391216 # Per bank write bursts +system.physmem.perBankRdBursts::10 386574 # Per bank write bursts +system.physmem.perBankRdBursts::11 385570 # Per bank write bursts +system.physmem.perBankRdBursts::12 390981 # Per bank write bursts +system.physmem.perBankRdBursts::13 390596 # Per bank write bursts +system.physmem.perBankRdBursts::14 386700 # Per bank write bursts +system.physmem.perBankRdBursts::15 386183 # Per bank write bursts +system.physmem.perBankWrBursts::0 7188 # Per bank write bursts +system.physmem.perBankWrBursts::1 7193 # Per bank write bursts +system.physmem.perBankWrBursts::2 7297 # Per bank write bursts +system.physmem.perBankWrBursts::3 7231 # Per bank write bursts +system.physmem.perBankWrBursts::4 7835 # Per bank write bursts +system.physmem.perBankWrBursts::5 7450 # Per bank write bursts +system.physmem.perBankWrBursts::6 7370 # Per bank write bursts +system.physmem.perBankWrBursts::7 7176 # Per bank write bursts +system.physmem.perBankWrBursts::8 7508 # Per bank write bursts +system.physmem.perBankWrBursts::9 7517 # Per bank write bursts +system.physmem.perBankWrBursts::10 6849 # Per bank write bursts +system.physmem.perBankWrBursts::11 6596 # Per bank write bursts +system.physmem.perBankWrBursts::12 7160 # Per bank write bursts +system.physmem.perBankWrBursts::13 6824 # Per bank write bursts +system.physmem.perBankWrBursts::14 7287 # Per bank write bursts +system.physmem.perBankWrBursts::15 7185 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1104764856500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 105 # Read request sizes (log2) +system.physmem.readPktSize::3 6094848 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 163027 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66695 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 548369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 494073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 445478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1468713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1058783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1047686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1043195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 25416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,312 +159,563 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35262 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11560.822642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 608.575977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 24356.197009 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 8749 24.81% 24.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 4356 12.35% 37.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2652 7.52% 44.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 2010 5.70% 50.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1437 4.08% 54.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1214 3.44% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 927 2.63% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 1120 3.18% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 659 1.87% 65.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 617 1.75% 67.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 450 1.28% 68.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 454 1.29% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 302 0.86% 70.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 302 0.86% 71.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 179 0.51% 72.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 219 0.62% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 133 0.38% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 156 0.44% 73.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 97 0.28% 73.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 134 0.38% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 73 0.21% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 395 1.12% 75.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 262 0.74% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 538 1.53% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 109 0.31% 78.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 178 0.50% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 51 0.14% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 128 0.36% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 49 0.14% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 68 0.19% 79.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 39 0.11% 79.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 74 0.21% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 17 0.05% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 56 0.16% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 22 0.06% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 30 0.09% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 13 0.04% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 29 0.08% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 10 0.03% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 19 0.05% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 9 0.03% 80.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 17 0.05% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 7 0.02% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 14 0.04% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 6 0.02% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 10 0.03% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 4 0.01% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 17 0.05% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 3 0.01% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 15 0.04% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 4 0.01% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 7 0.02% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 9 0.03% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 11 0.03% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 3 0.01% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 7 0.02% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 3 0.01% 80.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 11 0.03% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 80.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 4 0.01% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 5 0.01% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 13 0.04% 80.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 3 0.01% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 28 0.08% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 4 0.01% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 7 0.02% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 4 0.01% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 3 0.01% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 1 0.00% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 6 0.02% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 4 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 2 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 1 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 1 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 6 0.02% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 4 0.01% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 5 0.01% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 3 0.01% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 4 0.01% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5199 4 0.01% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 2 0.01% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 5 0.01% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 1 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5583 4 0.01% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 3 0.01% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 4 0.01% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5839 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 2 0.01% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6031 2 0.01% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6095 1 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 2 0.01% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 3 0.01% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 2 0.01% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6351 3 0.01% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 3 0.01% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 1 0.00% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6671 2 0.01% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 2 0.01% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 16 0.05% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 3 0.01% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6927 5 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6991 3 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 1 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 8 0.02% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7247 1 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 1 0.00% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 3 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 5 0.01% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7631 2 0.01% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 3 0.01% 81.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7759 2 0.01% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 1 0.00% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 4 0.01% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 6 0.02% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8015 1 0.00% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 7 0.02% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 5 0.01% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 318 0.90% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8399 1 0.00% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 41 0.12% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 122 0.35% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 8 0.02% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8719 1 0.00% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 3 0.01% 82.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 3 0.01% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 1 0.00% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9743 2 0.01% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9999 1 0.00% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10255 2 0.01% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10767 2 0.01% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11023 1 0.00% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11279 2 0.01% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11535 2 0.01% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12047 2 0.01% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12303 1 0.00% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12751 1 0.00% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13071 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13583 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13839 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14351 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14607 1 0.00% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15375 2 0.01% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15631 1 0.00% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16399 2 0.01% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16527 1 0.00% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 3 0.01% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17935 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18447 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18880-18895 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19151 1 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19215 1 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19727 1 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19919 1 0.00% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20239 1 0.00% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20495 2 0.01% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20928-20943 1 0.00% 82.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21007 2 0.01% 82.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21327 1 0.00% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21519 2 0.01% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22031 1 0.00% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22543 3 0.01% 83.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23567 1 0.00% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23823 1 0.00% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24143 1 0.00% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 4 0.01% 83.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24847 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25024-25039 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25103 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25359 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26319 1 0.00% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26383 1 0.00% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26639 1 0.00% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26703 1 0.00% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27215 1 0.00% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27407 1 0.00% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 2 0.01% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27983 1 0.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28111 1 0.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28687 3 0.01% 83.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 83.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29711 1 0.00% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29967 3 0.01% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30415 1 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30479 1 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 1 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31247 2 0.01% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31759 3 0.01% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32015 1 0.00% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32271 1 0.00% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32527 1 0.00% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32655 1 0.00% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32783 2 0.01% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32911 1 0.00% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33039 1 0.00% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33295 1 0.00% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33551 9 0.03% 83.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33615 9 0.03% 83.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33679 3 0.01% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33743 3 0.01% 83.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 23 0.07% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36879 1 0.00% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37568-37583 1 0.00% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37903 2 0.01% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39247 1 0.00% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39695 1 0.00% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43535 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44239 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44559 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45583 1 0.00% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46400-46415 1 0.00% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46863 1 0.00% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47119 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47247 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47311 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47439 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47887 1 0.00% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48143 2 0.01% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48335 2 0.01% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49039 1 0.00% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49600-49615 1 0.00% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49935 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52864-52879 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53504-53519 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54287 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54464-54479 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54784-54799 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58383 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60160-60175 1 0.00% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60672-60687 1 0.00% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60928-60943 1 0.00% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64527 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65039 10 0.03% 83.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65423 6 0.02% 83.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 5666 16.07% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::68672-68687 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69120-69135 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::72128-72143 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73088-73103 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 20 0.06% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 91 0.26% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 61 0.17% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35262 # Bytes accessed per row activation -system.physmem.totQLat 121597245250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 160506894000 # Sum of mem lat for all requests -system.physmem.totBusLat 31269035000 # Total cycles spent in databus access -system.physmem.totBankLat 7640613750 # Total cycles spent in bank access -system.physmem.avgQLat 19443.72 # Average queueing delay per request -system.physmem.avgBankLat 1221.75 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25665.47 # Average memory access latency -system.physmem.avgRdBW 362.77 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.74 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.62 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.21 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 12.74 # Average write queue length over time -system.physmem.readRowHits 6235456 # Number of row buffer hits during reads -system.physmem.writeRowHits 98940 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 12.01 # Row buffer hit rate for writes -system.physmem.avgGap 155904.23 # Average gap between requests +system.physmem.bytesPerActivate::samples 71125 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5702.673097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 368.783347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 12967.835637 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25909 36.43% 36.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14850 20.88% 57.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3162 4.45% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2234 3.14% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1545 2.17% 67.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1302 1.83% 68.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 996 1.40% 70.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1191 1.67% 71.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 629 0.88% 72.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 663 0.93% 73.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 567 0.80% 74.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 536 0.75% 75.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 288 0.40% 75.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 263 0.37% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 175 0.25% 76.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 373 0.52% 76.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 125 0.18% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 132 0.19% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 91 0.13% 77.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 197 0.28% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 57 0.08% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 541 0.76% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 41 0.06% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 225 0.32% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 27 0.04% 78.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 110 0.15% 79.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 22 0.03% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 16 0.02% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 61 0.09% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 267 0.38% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 16 0.02% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 40 0.06% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 17 0.02% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 50 0.07% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 11 0.02% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 22 0.03% 79.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 7 0.01% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 43 0.06% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 4 0.01% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 15 0.02% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 8 0.01% 80.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 32 0.04% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 30 0.04% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 157 0.22% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 6 0.01% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 17 0.02% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 2 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 36 0.05% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 17 0.02% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 7 0.01% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 7 0.01% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 8 0.01% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 39 0.05% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 6 0.01% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 181 0.25% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 9 0.01% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 12 0.02% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 12 0.02% 81.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 102 0.14% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 17 0.02% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 25 0.04% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 7 0.01% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 11 0.02% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 5 0.01% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 19 0.03% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 161 0.23% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 13 0.02% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 9 0.01% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 14 0.02% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 3 0.00% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 16 0.02% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 18 0.03% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 5 0.01% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 8 0.01% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 5 0.01% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 150 0.21% 81.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 2 0.00% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 12 0.02% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 13 0.02% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 95 0.13% 82.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 7 0.01% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 23 0.03% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.01% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 11 0.02% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 3 0.00% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 112 0.16% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 9 0.01% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 20 0.03% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 8 0.01% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 28 0.04% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 4 0.01% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 2 0.00% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 94 0.13% 82.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 6 0.01% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 10 0.01% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 92 0.13% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 3 0.00% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 10 0.01% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 3 0.00% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 20 0.03% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 2 0.00% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 2 0.00% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 4 0.01% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 6 0.01% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 249 0.35% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 83.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 31 0.04% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 16 0.02% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 3 0.00% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 75 0.11% 83.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 93 0.13% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9415 1 0.00% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 20 0.03% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 102 0.14% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 14 0.02% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 94 0.13% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 94 0.13% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 15 0.02% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10823 1 0.00% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10887 1 0.00% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 6 0.01% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11079 2 0.00% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 147 0.21% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11335 3 0.00% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 1 0.00% 84.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 1 0.00% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11847 1 0.00% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 79 0.11% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 162 0.23% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 20 0.03% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12743 1 0.00% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 68 0.10% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12935 1 0.00% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 148 0.21% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13511 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 19 0.03% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 18 0.03% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 11 0.02% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 228 0.32% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 27 0.04% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 14 0.02% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 1 0.00% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 73 0.10% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 2 0.00% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 145 0.20% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 10 0.01% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15751 1 0.00% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 20 0.03% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 17 0.02% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 1 0.00% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16327 1 0.00% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 273 0.38% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16455 1 0.00% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 1 0.00% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 21 0.03% 86.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 13 0.02% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 1 0.00% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 156 0.22% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 2 0.00% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 1 0.00% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 80 0.11% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 1 0.00% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 14 0.02% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 31 0.04% 86.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 2 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 219 0.31% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 6 0.01% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18752-18759 1 0.00% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 15 0.02% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19015 1 0.00% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 4 0.01% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 13 0.02% 87.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19264-19271 1 0.00% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 140 0.20% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 17 0.02% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19847 2 0.00% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 68 0.10% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 1 0.00% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 17 0.02% 87.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 2 0.00% 87.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 157 0.22% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 82 0.12% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 4 0.01% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 14 0.02% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 2 0.00% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 145 0.20% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21696-21703 1 0.00% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 4 0.01% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21824-21831 1 0.00% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 14 0.02% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 2 0.00% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 92 0.13% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 1 0.00% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 2 0.00% 88.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 85 0.12% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 14 0.02% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 102 0.14% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 2 0.00% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23232-23239 1 0.00% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.03% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23488-23495 1 0.00% 88.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 91 0.13% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23744-23751 4 0.01% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 75 0.11% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23872-23879 2 0.00% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 1 0.00% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 21 0.03% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 31 0.04% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24512-24519 1 0.00% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 139 0.20% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24711 1 0.00% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24775 1 0.00% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 29 0.04% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 2 0.00% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 18 0.03% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 77 0.11% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 90 0.13% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 104 0.15% 89.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 14 0.02% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 87 0.12% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 2 0.00% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 94 0.13% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 2 0.00% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27328-27335 1 0.00% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 5 0.01% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 143 0.20% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 1 0.00% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 16 0.02% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 5 0.01% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28224-28231 2 0.00% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 82 0.12% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 1 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 1 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 157 0.22% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 2 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 1 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 22 0.03% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 2 0.00% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 67 0.09% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29383 1 0.00% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 16 0.02% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 3 0.00% 90.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 139 0.20% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 3 0.00% 90.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30016-30023 1 0.00% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 2 0.00% 90.78% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31175 1 0.00% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 17 0.02% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 70 0.10% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 147 0.21% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31808-31815 1 0.00% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 14 0.02% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32064-32071 1 0.00% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 20 0.03% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 2 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 14 0.02% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32704-32711 1 0.00% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 271 0.38% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 14 0.02% 91.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 20 0.03% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 1 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 20 0.03% 92.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 4 0.01% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 153 0.22% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 71 0.10% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 15 0.02% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34368-34375 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 26 0.04% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34624-34631 2 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 211 0.30% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 7 0.01% 92.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 15 0.02% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 136 0.19% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 19 0.03% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36288-36295 1 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 67 0.09% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 1 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 18 0.03% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 155 0.22% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 79 0.11% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 3 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 1 0.00% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 12 0.02% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37696-37703 1 0.00% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 140 0.20% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 3 0.00% 93.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 13 0.02% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 93 0.13% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 85 0.12% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 15 0.02% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39360-39367 2 0.00% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 104 0.15% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 1 0.00% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 19 0.03% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 90 0.13% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 75 0.11% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 16 0.02% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 2 0.00% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 30 0.04% 94.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40832-40839 1 0.00% 94.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 138 0.19% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 29 0.04% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41280-41287 1 0.00% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 18 0.03% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41536-41543 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41664-41671 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 74 0.10% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41792-41799 2 0.00% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41920-41927 2 0.00% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 90 0.13% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 19 0.03% 94.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 98 0.14% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 15 0.02% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 2 0.00% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 82 0.12% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 90 0.13% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43392-43399 1 0.00% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 4 0.01% 95.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 144 0.20% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 2 0.00% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 12 0.02% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 2 0.00% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 5 0.01% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 85 0.12% 95.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 155 0.22% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 16 0.02% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 96.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 2 0.00% 96.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 71 0.10% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45639 2 0.00% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 19 0.03% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 138 0.19% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 14 0.02% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 15 0.02% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 10 0.01% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 214 0.30% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 31 0.04% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 15 0.02% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 70 0.10% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 146 0.21% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 10 0.01% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 20 0.03% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48832-48839 2 0.00% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 13 0.02% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 1979 2.78% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49792-49799 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50183 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50887 4 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 3 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51648-51655 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52352-52359 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52672-52679 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 71125 # Bytes accessed per row activation +system.physmem.totQLat 151840872500 # Total ticks spent queuing +system.physmem.totMemAccLat 191562815000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 31109410000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8612532500 # Total ticks spent accessing banks +system.physmem.avgQLat 24404.33 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1384.23 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30788.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 360.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.87 # Data bus utilization in percentage +system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.06 # Average write queue length when enqueuing +system.physmem.readRowHits 6168484 # Number of row buffer hits during reads +system.physmem.writeRowHits 97939 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.66 # Row buffer hit rate for writes +system.physmem.avgGap 156006.94 # Average gap between requests +system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 3.92 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -485,300 +734,286 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 62410733 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306749 # Transaction distribution -system.membus.trans_dist::ReadResp 7306749 # Transaction distribution +system.membus.throughput 62369736 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306752 # Transaction distribution +system.membus.trans_dist::ReadResp 7306752 # Transaction distribution system.membus.trans_dist::WriteReq 767894 # Transaction distribution system.membus.trans_dist::WriteResp 767894 # Transaction distribution -system.membus.trans_dist::Writeback 66675 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33869 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17715 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12574 # Transaction distribution -system.membus.trans_dist::ReadExReq 138085 # Transaction distribution -system.membus.trans_dist::ReadExResp 137703 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382522 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 66695 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33888 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17695 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12605 # Transaction distribution +system.membus.trans_dist::ReadExReq 138070 # Transaction distribution +system.membus.trans_dist::ReadExResp 137680 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382518 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11642 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971187 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366229 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555907 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389789 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16555925 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389781 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23284 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729844 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20145057 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729972 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20145177 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68903841 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68903841 # Total data (bytes) +system.membus.tot_pkt_size::total 68903961 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68903961 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475612500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487006499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9865000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9880000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 750000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 749500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8618805999 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8612723499 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4854602214 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4837509170 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13760099489 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13760375954 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 72758 # number of replacements -system.l2c.tags.tagsinuse 53808.125296 # Cycle average of tags in use -system.l2c.tags.total_refs 1836602 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137939 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.314596 # Average number of references to valid blocks. +system.l2c.tags.replacements 72740 # number of replacements +system.l2c.tags.tagsinuse 53853.567584 # Cycle average of tags in use +system.l2c.tags.total_refs 1839137 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.334423 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39514.415699 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.446892 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257540 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4002.916228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2827.365052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.413975 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.918976 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3679.171285 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3769.219649 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.602942 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000068 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 39512.680536 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.162068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257969 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4009.847433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2829.767621 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.955070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3709.355619 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3778.541270 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.602916 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061080 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043142 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000144 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056140 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057514 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821047 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21860 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4237 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386435 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166509 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30879 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 588366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198248 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1401466 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581263 # number of Writeback hits -system.l2c.Writeback_hits::total 581263 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 743 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2078 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 202 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 141 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 343 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48314 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58639 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106953 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21860 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4237 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386435 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214823 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30879 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4932 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 588366 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256887 # number of demand (read+write) hits -system.l2c.demand_hits::total 1508419 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21860 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4237 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386435 # number of overall hits -system.l2c.overall_hits::cpu0.data 214823 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30879 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4932 # number of overall hits -system.l2c.overall_hits::cpu1.inst 588366 # number of overall hits -system.l2c.overall_hits::cpu1.data 256887 # number of overall hits -system.l2c.overall_hits::total 1508419 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.061185 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056600 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.057656 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.821740 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 22065 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4358 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386342 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166614 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30647 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5089 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 590258 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198399 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1403772 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581386 # number of Writeback hits +system.l2c.Writeback_hits::total 581386 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 750 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2084 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48317 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58643 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22065 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4358 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63156.973522 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65507.251603 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62685.936512 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.485283 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10089.113917 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.462688 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.555730 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.934625 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10033.371429 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57735.641497 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69024.341151 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63933.038618 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -981,62 +1204,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 136659470 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2706207 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2706206 # Transaction distribution +system.toL2Bus.throughput 136691596 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2708551 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2708550 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581263 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33352 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18058 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51410 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258939 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258939 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 786305 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073575 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13268 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55413 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1190023 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801593 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14394 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72130 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8006701 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25142464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34843867 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38062080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47776006 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 19732 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 123572 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 146072169 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146072169 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4805124 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4892877936 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 581386 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33382 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18023 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51405 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258959 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258959 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785985 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13547 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1193885 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4802054 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14684 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 71694 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8011498 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25134272 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847315 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17444 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38184256 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47797126 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20356 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 122632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146211713 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146211713 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4800508 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4894625900 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1772488367 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1771371395 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1516304011 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1514575770 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9043467 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9208452 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 33687702 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34011429 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2681029210 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2689519761 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3243394678 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 3237226447 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9483701 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 9617950 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41522672 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41300207 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 46328621 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278159 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278159 # Transaction distribution +system.iobus.throughput 46298101 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution system.iobus.trans_dist::WriteReq 7950 # Transaction distribution system.iobus.trans_dist::WriteResp 7950 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1058,12 +1281,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382518 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 14572214 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1085,14 +1308,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389789 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389781 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148573 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148573 # Total data (bytes) +system.iobus.tot_pkt_size::total 51148565 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148565 # Total data (bytes) system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4019000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1138,42 +1361,42 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374572000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374568000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16699589511 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16664438046 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6002321 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4576737 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295742 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3785758 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2914394 # Number of BTB hits +system.cpu0.branchPred.lookups 6002691 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4577903 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 294712 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3771820 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2913648 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.983104 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673290 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28745 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.247801 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672509 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28479 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8907919 # DTB read hits -system.cpu0.dtb.read_misses 28331 # DTB read misses -system.cpu0.dtb.write_hits 5140728 # DTB write hits -system.cpu0.dtb.write_misses 5464 # DTB write misses +system.cpu0.dtb.read_hits 8905508 # DTB read hits +system.cpu0.dtb.read_misses 28991 # DTB read misses +system.cpu0.dtb.write_hits 5140500 # DTB write hits +system.cpu0.dtb.write_misses 5723 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1828 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 958 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1824 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 969 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 551 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8936250 # DTB read accesses -system.cpu0.dtb.write_accesses 5146192 # DTB write accesses +system.cpu0.dtb.perms_faults 556 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8934499 # DTB read accesses +system.cpu0.dtb.write_accesses 5146223 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14048647 # DTB hits -system.cpu0.dtb.misses 33795 # DTB misses -system.cpu0.dtb.accesses 14082442 # DTB accesses -system.cpu0.itb.inst_hits 4222709 # ITB inst hits -system.cpu0.itb.inst_misses 5005 # ITB inst misses +system.cpu0.dtb.hits 14046008 # DTB hits +system.cpu0.dtb.misses 34714 # DTB misses +system.cpu0.dtb.accesses 14080722 # DTB accesses +system.cpu0.itb.inst_hits 4219281 # ITB inst hits +system.cpu0.itb.inst_misses 5089 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1182,114 +1405,114 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1348 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1343 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1494 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1465 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4227714 # ITB inst accesses -system.cpu0.itb.hits 4222709 # DTB hits -system.cpu0.itb.misses 5005 # DTB misses -system.cpu0.itb.accesses 4227714 # DTB accesses -system.cpu0.numCycles 69175889 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4224370 # ITB inst accesses +system.cpu0.itb.hits 4219281 # DTB hits +system.cpu0.itb.misses 5089 # DTB misses +system.cpu0.itb.accesses 4224370 # DTB accesses +system.cpu0.numCycles 69432037 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11717201 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32026454 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6002321 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3587684 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7519324 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1452827 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60860 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19607589 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5035 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47006 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1325879 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 324 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4221110 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157905 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2000 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41325646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.001484 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.381957 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11713503 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32019404 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6002691 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3586157 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7516730 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1449804 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61386 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19631994 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46872 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1335943 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4217707 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157539 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41351812 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.000563 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.381156 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33813760 81.82% 81.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565868 1.37% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 817164 1.98% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676151 1.64% 86.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772838 1.87% 88.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 560246 1.36% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 669817 1.62% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351583 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098219 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33842541 81.84% 81.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565579 1.37% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816874 1.98% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676358 1.64% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 772843 1.87% 88.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 558608 1.35% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 669211 1.62% 91.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351371 0.85% 92.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3098427 7.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41325646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086769 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.462971 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12221128 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20791110 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6824454 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 510238 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 978716 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935346 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64732 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40027040 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212951 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 978716 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12790081 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5972534 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12789547 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6714080 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2080688 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38920228 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 41351812 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086454 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461162 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12216999 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20826551 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6820783 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 510850 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 976629 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935170 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64759 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40012064 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213022 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 976629 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12786291 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5985032 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12800887 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6711570 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2091403 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38907337 # Number of instructions processed by rename system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 436221 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1152507 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 84 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39264921 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175790758 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 161860177 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4025 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30938700 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8326220 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411215 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370279 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5370420 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7651291 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5689186 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1120456 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1254854 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36835170 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895288 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37251130 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81272 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6287660 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13163035 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256365 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41325646 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.901405 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514906 # Number of insts issued each cycle +system.cpu0.rename.IQFullEvents 435425 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1163203 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 107 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39252215 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175728295 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 161804372 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3955 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30935092 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8317122 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411284 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370379 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5367119 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7645996 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5688511 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1121166 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1220161 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36823164 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895382 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37236653 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80347 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6279547 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13158300 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256522 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41351812 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.900484 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.514831 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26248472 63.52% 63.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5690851 13.77% 77.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3114453 7.54% 84.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2470786 5.98% 90.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2128163 5.15% 95.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 926108 2.24% 98.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 506651 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 185379 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54783 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26282952 63.56% 63.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5688374 13.76% 77.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3116432 7.54% 84.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2466494 5.96% 90.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2112034 5.11% 95.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 939185 2.27% 98.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 506930 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184996 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54415 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41325646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41351812 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27685 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.04% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27736 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 453 0.04% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available @@ -1317,395 +1540,395 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842164 78.64% 81.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 200566 18.73% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 842113 78.49% 81.12% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 202594 18.88% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22335497 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46969 0.13% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22326150 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46947 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9366005 25.14% 85.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5449722 14.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9362954 25.14% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5447671 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37251130 # Type of FU issued -system.cpu0.iq.rate 0.538499 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070867 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028747 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117005145 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44025943 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34344840 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8484 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3874 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38265319 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4464 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307168 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37236653 # Type of FU issued +system.cpu0.iq.rate 0.536304 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1072896 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028813 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117004426 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44005967 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34332716 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8422 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4624 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3857 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38252914 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4421 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307648 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1372814 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2493 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13018 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537400 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1368398 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2491 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13086 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 537466 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192818 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5781 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192854 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5939 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 978716 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4319425 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 103424 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37848942 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83231 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7651291 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5689186 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571145 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39872 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 13404 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13018 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150227 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117595 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267822 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36871306 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9223534 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 379824 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 976629 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4337522 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 100010 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37836354 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83498 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7645996 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5688511 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571219 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39755 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6621 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13086 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149491 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117486 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 266977 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36859042 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9220953 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 377611 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118484 # number of nop insts executed -system.cpu0.iew.exec_refs 14624342 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4855002 # Number of branches executed -system.cpu0.iew.exec_stores 5400808 # Number of stores executed -system.cpu0.iew.exec_rate 0.533008 # Inst execution rate -system.cpu0.iew.wb_sent 36677174 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34348714 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18316479 # num instructions producing a value -system.cpu0.iew.wb_consumers 35213732 # num instructions consuming a value +system.cpu0.iew.exec_nop 117808 # number of nop insts executed +system.cpu0.iew.exec_refs 14621413 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4853789 # Number of branches executed +system.cpu0.iew.exec_stores 5400460 # Number of stores executed +system.cpu0.iew.exec_rate 0.530865 # Inst execution rate +system.cpu0.iew.wb_sent 36664720 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34336573 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18306413 # num instructions producing a value +system.cpu0.iew.wb_consumers 35193198 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.496542 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520152 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.494535 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520169 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6093987 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638923 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232030 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40346930 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775643 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740681 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6085996 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638860 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231074 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40375183 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775004 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.739173 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28704762 71.14% 71.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5702920 14.13% 85.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1886389 4.68% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 981050 2.43% 92.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 790069 1.96% 94.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 509429 1.26% 95.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 395100 0.98% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 219754 0.54% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1157457 2.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28737053 71.18% 71.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5697190 14.11% 85.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1882101 4.66% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 980199 2.43% 92.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 786708 1.95% 94.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 526531 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 398386 0.99% 96.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 216969 0.54% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1150046 2.85% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40346930 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23686340 # Number of instructions committed -system.cpu0.commit.committedOps 31294803 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40375183 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23683551 # Number of instructions committed +system.cpu0.commit.committedOps 31290943 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11430263 # Number of memory references committed -system.cpu0.commit.loads 6278477 # Number of loads committed -system.cpu0.commit.membars 229716 # Number of memory barriers committed -system.cpu0.commit.branches 4246456 # Number of branches committed +system.cpu0.commit.refs 11428643 # Number of memory references committed +system.cpu0.commit.loads 6277598 # Number of loads committed +system.cpu0.commit.membars 229694 # Number of memory barriers committed +system.cpu0.commit.branches 4245889 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27650320 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489514 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1157457 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27646853 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489416 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1150046 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75726854 # The number of ROB reads -system.cpu0.rob.rob_writes 75758265 # The number of ROB writes -system.cpu0.timesIdled 367474 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27850243 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138859041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23605598 # Number of Instructions Simulated -system.cpu0.committedOps 31214061 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23605598 # Number of Instructions Simulated -system.cpu0.cpi 2.930487 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.930487 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.341240 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.341240 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171860544 # number of integer regfile reads -system.cpu0.int_regfile_writes 34096305 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads -system.cpu0.fp_regfile_writes 892 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13010065 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451140 # number of misc regfile writes -system.cpu0.icache.tags.replacements 392795 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.002835 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3796668 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 393307 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.653192 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6982777250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.002835 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998052 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3796668 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3796668 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3796668 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3796668 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3796668 # number of overall hits -system.cpu0.icache.overall_hits::total 3796668 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 424314 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 424314 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 424314 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 424314 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 424314 # number of overall misses -system.cpu0.icache.overall_misses::total 424314 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5901888496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5901888496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5901888496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5901888496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5901888496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5901888496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4220982 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4220982 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4220982 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4220982 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4220982 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4220982 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100525 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100525 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100525 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100525 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100525 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100525 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13909.247623 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.247623 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13909.247623 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13909.247623 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3930 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75750709 # The number of ROB reads +system.cpu0.rob.rob_writes 75732466 # The number of ROB writes +system.cpu0.timesIdled 364061 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28080225 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2140058132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23602809 # Number of Instructions Simulated +system.cpu0.committedOps 31210201 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23602809 # Number of Instructions Simulated +system.cpu0.cpi 2.941685 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.941685 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.339941 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.339941 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171807193 # number of integer regfile reads +system.cpu0.int_regfile_writes 34081987 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3237 # number of floating regfile reads +system.cpu0.fp_regfile_writes 886 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13003191 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451099 # number of misc regfile writes +system.cpu0.icache.tags.replacements 392605 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.965142 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3793600 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 393117 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.650053 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7051834000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.965142 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997979 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997979 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3793600 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3793600 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3793600 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3793600 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3793600 # number of overall hits +system.cpu0.icache.overall_hits::total 3793600 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423979 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423979 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423979 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423979 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423979 # number of overall misses +system.cpu0.icache.overall_misses::total 423979 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5892352014 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5892352014 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5892352014 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5892352014 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5892352014 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5892352014 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4217579 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4217579 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4217579 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4217579 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4217579 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4217579 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100527 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100527 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100527 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100527 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100527 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100527 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.744969 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.744969 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13897.744969 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13897.744969 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3802 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 194 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 164 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.257732 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.182927 # 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number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977015 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977015 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977015 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5539255201 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5539255201 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79907349135 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 79907349135 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 90050735 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 90050735 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45818635 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45818635 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 85446604336 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 85446604336 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 85446604336 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 85446604336 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6170364 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6170364 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743672 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4743672 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147871 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147871 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144543 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144543 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10914036 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10914036 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10914036 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10914036 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063544 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063544 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334114 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.334114 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059038 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059038 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051549 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051549 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181144 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181144 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181144 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181144 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14127.509503 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14127.509503 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50417.116983 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50417.116983 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10315.089920 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10315.089920 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6149.326936 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6149.326936 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43220.008111 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43220.008111 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43220.008111 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43220.008111 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9481 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 10276 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 609 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.092985 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 48.908397 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.568144 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 78.442748 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks -system.cpu0.dcache.writebacks::total 256512 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203095 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203095 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454344 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454344 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 453 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 453 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657439 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657439 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188695 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188695 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130482 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130482 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8289 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8289 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7480 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7480 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319177 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319177 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319177 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319177 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2406687867 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2406687867 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110325446 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110325446 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66640768 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66640768 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30961371 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30961371 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7517013313 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7517013313 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7517013313 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7517013313 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504611525 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504611525 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131834379 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131834379 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636445904 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636445904 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030566 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030566 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051744 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051744 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029235 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029235 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.380704 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.380704 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39164.984028 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39164.984028 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.663168 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.663168 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4139.220722 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4139.220722 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256484 # number of writebacks +system.cpu0.dcache.writebacks::total 256484 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203289 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203289 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454440 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1454440 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 445 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 445 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657729 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657729 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657729 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657729 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188801 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188801 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130485 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130485 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8285 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8285 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7449 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7449 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319286 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319286 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319286 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319286 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2419086873 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2419086873 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5310990170 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5310990170 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68672765 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68672765 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30919365 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30919365 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7730077043 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7730077043 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7730077043 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7730077043 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504888791 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504888791 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131913883 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131913883 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636802674 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636802674 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030598 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030598 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056029 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056029 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051535 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051535 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029255 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029255 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12812.892268 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12812.892268 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40701.921064 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40701.921064 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8288.806880 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8288.806880 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4150.807491 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4150.807491 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1713,38 +1936,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8782132 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7168426 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 407819 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5819499 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4955017 # Number of BTB hits +system.cpu1.branchPred.lookups 8781819 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7169373 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 406881 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5765537 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4953289 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.145079 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 773793 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42171 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.912015 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772113 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42948 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42691295 # DTB read hits -system.cpu1.dtb.read_misses 36496 # DTB read misses -system.cpu1.dtb.write_hits 6824033 # DTB write hits -system.cpu1.dtb.write_misses 10597 # DTB write misses +system.cpu1.dtb.read_hits 42694682 # DTB read hits +system.cpu1.dtb.read_misses 36199 # DTB read misses +system.cpu1.dtb.write_hits 6825983 # DTB write hits +system.cpu1.dtb.write_misses 10603 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2020 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2612 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2691 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 287 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42727791 # DTB read accesses -system.cpu1.dtb.write_accesses 6834630 # DTB write accesses +system.cpu1.dtb.perms_faults 664 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42730881 # DTB read accesses +system.cpu1.dtb.write_accesses 6836586 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49515328 # DTB hits -system.cpu1.dtb.misses 47093 # DTB misses -system.cpu1.dtb.accesses 49562421 # DTB accesses -system.cpu1.itb.inst_hits 7577708 # ITB inst hits -system.cpu1.itb.inst_misses 5297 # ITB inst misses +system.cpu1.dtb.hits 49520665 # DTB hits +system.cpu1.dtb.misses 46802 # DTB misses +system.cpu1.dtb.accesses 49567467 # DTB accesses +system.cpu1.itb.inst_hits 7578103 # ITB inst hits +system.cpu1.itb.inst_misses 5415 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1753,114 +1976,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1529 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1545 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1496 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7583005 # ITB inst accesses -system.cpu1.itb.hits 7577708 # DTB hits -system.cpu1.itb.misses 5297 # DTB misses -system.cpu1.itb.accesses 7583005 # DTB accesses -system.cpu1.numCycles 408491180 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7583518 # ITB inst accesses +system.cpu1.itb.hits 7578103 # DTB hits +system.cpu1.itb.misses 5415 # DTB misses +system.cpu1.itb.accesses 7583518 # DTB accesses +system.cpu1.numCycles 409882606 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18854224 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 60287918 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8782132 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5728810 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13124144 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3307681 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 62009 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77240238 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4754 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42673 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1437796 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7575877 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 546214 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2648 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 113028448 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.652235 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.978835 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18878139 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 60299044 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8781819 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5725402 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13123323 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3309042 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63154 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78443797 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5020 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42366 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1440662 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7576329 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 547353 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2737 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114261108 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.645293 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.969526 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99911588 88.40% 88.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796149 0.70% 89.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 938672 0.83% 89.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1688468 1.49% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1396344 1.24% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 570472 0.50% 93.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1929580 1.71% 94.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410359 0.36% 95.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5386816 4.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 101145087 88.52% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796077 0.70% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 936773 0.82% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1687391 1.48% 91.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1395150 1.22% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 571856 0.50% 93.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1930284 1.69% 94.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 409373 0.36% 95.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5389117 4.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 113028448 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.021499 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.147587 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20182430 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78186513 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11968696 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 524734 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2166075 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1104186 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 97997 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69821372 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 325725 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2166075 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21372370 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33233612 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40763249 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11209012 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4284130 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 65907040 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18855 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668466 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3042854 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 1130 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 69218982 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 302521919 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 280703259 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6508 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49058929 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20160053 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444772 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387840 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7873214 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12591353 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7935523 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1036537 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1457992 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60681374 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157953 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 87712578 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93570 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13421216 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 35924412 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277156 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 113028448 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.776022 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519284 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114261108 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021425 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.147113 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20196476 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 79405562 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11967958 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523276 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2167836 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1103528 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98181 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69822224 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 326370 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2167836 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21386304 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34427825 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40782107 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11206546 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4290490 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 65904089 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18821 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 671145 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3046869 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 355 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 69217965 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 302501585 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 280690851 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6493 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49057579 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20160386 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444741 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387793 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7877859 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12590402 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7938263 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1041211 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1447247 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60694774 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157845 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 87723814 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94478 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13427979 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 35976172 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277080 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114261108 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.767749 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.513486 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83202776 73.61% 73.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8275815 7.32% 80.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4119768 3.64% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3698740 3.27% 87.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10372542 9.18% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1968067 1.74% 98.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1039899 0.92% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 275618 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 75223 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84436887 73.90% 73.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8271726 7.24% 81.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4125209 3.61% 84.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3692140 3.23% 87.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10373138 9.08% 97.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1967895 1.72% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1041724 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 276233 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 76156 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 113028448 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114261108 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32070 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32226 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 994 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -1888,395 +2111,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7550021 95.87% 96.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 292311 3.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7551636 95.89% 96.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 290793 3.69% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36603154 41.73% 42.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59244 0.07% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36606472 41.73% 42.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59249 0.07% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.16% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43563118 49.67% 91.82% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7171472 8.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43568189 49.67% 91.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7174305 8.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 87712578 # Type of FU issued -system.cpu1.iq.rate 0.214723 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7875398 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089786 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 296453915 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 75268930 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53141218 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15550 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8086 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6819 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95265602 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8312 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 341261 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 87723814 # Type of FU issued +system.cpu1.iq.rate 0.214022 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7875649 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089778 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 297709996 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 75289267 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53144243 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15477 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8000 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95277128 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8273 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 341654 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2835568 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3737 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17004 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1095143 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2834942 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3919 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1098203 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31913350 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 674872 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31919752 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 674526 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2166075 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25455774 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 362563 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 61943028 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112233 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12591353 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7935523 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869270 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64753 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6199 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17004 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 201423 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154723 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 356146 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 85989556 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43061283 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1723022 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2167836 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26657812 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 361941 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 61957280 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112544 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12590402 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7938263 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869014 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64925 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17226 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 200285 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154811 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 355096 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85998990 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43064757 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1724824 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103701 # number of nop insts executed -system.cpu1.iew.exec_refs 50171461 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6912906 # Number of branches executed -system.cpu1.iew.exec_stores 7110178 # Number of stores executed -system.cpu1.iew.exec_rate 0.210505 # Inst execution rate -system.cpu1.iew.wb_sent 85230378 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53148037 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29710424 # num instructions producing a value -system.cpu1.iew.wb_consumers 52969976 # num instructions consuming a value +system.cpu1.iew.exec_nop 104661 # number of nop insts executed +system.cpu1.iew.exec_refs 50176981 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6911907 # Number of branches executed +system.cpu1.iew.exec_stores 7112224 # Number of stores executed +system.cpu1.iew.exec_rate 0.209814 # Inst execution rate +system.cpu1.iew.wb_sent 85240093 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53151046 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29713379 # num instructions producing a value +system.cpu1.iew.wb_consumers 52980753 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.130108 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560892 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.129674 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560833 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13294883 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880797 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 311444 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 110862373 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.434393 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.404754 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13311701 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880765 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 310263 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112093272 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.429609 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.397405 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94147475 84.92% 84.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8220753 7.42% 92.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2089215 1.88% 94.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1249683 1.13% 95.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1247924 1.13% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 575753 0.52% 96.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 991767 0.89% 97.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 529898 0.48% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1809905 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95372912 85.08% 85.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8221460 7.33% 92.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2092695 1.87% 94.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1254196 1.12% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1248841 1.11% 96.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 572620 0.51% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 992421 0.89% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 531111 0.47% 98.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1807016 1.61% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 110862373 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38066252 # Number of instructions committed -system.cpu1.commit.committedOps 48157821 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112093272 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38065083 # Number of instructions committed +system.cpu1.commit.committedOps 48156333 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16596165 # Number of memory references committed -system.cpu1.commit.loads 9755785 # Number of loads committed -system.cpu1.commit.membars 190126 # Number of memory barriers committed -system.cpu1.commit.branches 5967905 # Number of branches committed +system.cpu1.commit.refs 16595520 # Number of memory references committed +system.cpu1.commit.loads 9755460 # Number of loads committed +system.cpu1.commit.membars 190120 # Number of memory barriers committed +system.cpu1.commit.branches 5967695 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42692526 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534650 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1809905 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42691207 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534629 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1807016 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 169461098 # The number of ROB reads -system.cpu1.rob.rob_writes 125154390 # The number of ROB writes -system.cpu1.timesIdled 1414583 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295462732 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1798949280 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37996613 # Number of Instructions Simulated -system.cpu1.committedOps 48088182 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37996613 # Number of Instructions Simulated -system.cpu1.cpi 10.750726 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.750726 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.093017 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.093017 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 384900722 # number of integer regfile reads -system.cpu1.int_regfile_writes 55276259 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5045 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18451458 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405460 # number of misc regfile writes -system.cpu1.icache.tags.replacements 594712 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.460982 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6935744 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 595224 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.652326 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74833132000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.460982 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938400 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938400 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 6935744 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6935744 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6935744 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6935744 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6935744 # number of overall hits -system.cpu1.icache.overall_hits::total 6935744 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 640085 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 640085 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 640085 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 640085 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 640085 # number of overall misses -system.cpu1.icache.overall_misses::total 640085 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8700934064 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8700934064 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8700934064 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8700934064 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8700934064 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8700934064 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7575829 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7575829 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7575829 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7575829 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7575829 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7575829 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084490 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084490 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084490 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084490 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084490 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084490 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13593.404101 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13593.404101 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13593.404101 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13593.404101 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2623 # number of cycles access was blocked +system.cpu1.rob.rob_reads 170710273 # The number of ROB reads +system.cpu1.rob.rob_writes 125186848 # The number of ROB writes +system.cpu1.timesIdled 1415125 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295621498 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1799013115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37995444 # Number of Instructions Simulated +system.cpu1.committedOps 48086694 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37995444 # Number of Instructions Simulated +system.cpu1.cpi 10.787678 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.787678 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092698 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092698 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 384930549 # number of integer regfile reads +system.cpu1.int_regfile_writes 55277579 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5074 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18448778 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405411 # number of misc regfile writes +system.cpu1.icache.tags.replacements 596659 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.521199 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6934084 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 597171 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.611555 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74930526000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.521199 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938518 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938518 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 6934084 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6934084 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6934084 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6934084 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6934084 # number of overall hits +system.cpu1.icache.overall_hits::total 6934084 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 642197 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 642197 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 642197 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 642197 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 642197 # number of overall misses +system.cpu1.icache.overall_misses::total 642197 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8716898620 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8716898620 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8716898620 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8716898620 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8716898620 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8716898620 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576281 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7576281 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7576281 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7576281 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7576281 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7576281 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084764 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084764 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084764 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084764 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084764 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084764 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.558612 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.558612 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13573.558612 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13573.558612 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3156 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 183 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.333333 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.610526 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44828 # 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number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7103878279 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7103878279 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7103878279 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7103878279 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7103878279 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3410750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3410750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3410750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3410750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078573 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.078573 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.078573 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11934.136481 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11934.136481 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11934.136481 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44987 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44987 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44987 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44987 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44987 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44987 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597210 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 597210 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 597210 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 597210 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 597210 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 597210 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7115046481 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7115046481 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7115046481 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7115046481 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7115046481 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7115046481 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3356250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3356250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3356250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3356250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078826 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.078826 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.078826 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11913.810018 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 360690 # number of replacements -system.cpu1.dcache.tags.tagsinuse 473.926621 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12678192 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 361043 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.115463 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70882645000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.926621 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925638 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.925638 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8311339 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8311339 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4138952 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4138952 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97545 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97545 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94900 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94900 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12450291 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12450291 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12450291 # number of overall hits -system.cpu1.dcache.overall_hits::total 12450291 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 397118 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 397118 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1557827 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1557827 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13956 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13956 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10582 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10582 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1954945 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1954945 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1954945 # number of overall misses -system.cpu1.dcache.overall_misses::total 1954945 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6022716747 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6022716747 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 76093468282 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 76093468282 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129448993 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129448993 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53146420 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53146420 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 82116185029 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 82116185029 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 82116185029 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 82116185029 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8708457 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8708457 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696779 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5696779 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111501 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111501 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105482 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105482 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14405236 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14405236 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14405236 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14405236 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045601 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045601 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273458 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273458 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100320 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100320 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15166.063354 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15166.063354 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48845.904123 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 48845.904123 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9275.508240 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9275.508240 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5022.341712 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5022.341712 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 42004.345406 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 42004.345406 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29557 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18184 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3279 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.014029 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 108.238095 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 360813 # number of replacements +system.cpu1.dcache.tags.tagsinuse 473.792536 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 12672687 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 361164 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.088456 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70971728000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.792536 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925376 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.925376 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8306232 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8306232 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4138701 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4138701 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97355 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97355 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94895 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94895 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12444933 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12444933 # 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number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 86277258695 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 86277258695 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 86277258695 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8704948 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8704948 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5696560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111292 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111292 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105470 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105470 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14401508 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14401508 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14401508 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14401508 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045803 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045803 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273474 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273474 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125229 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125229 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100265 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100265 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135859 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135859 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135859 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135859 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.359434 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.359434 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51480.325677 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 51480.325677 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9227.684868 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9227.684868 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 4996.492388 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4996.492388 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 44096.065162 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 44096.065162 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 44096.065162 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 44096.065162 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 31164 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18449 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3306 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.426497 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 111.138554 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324751 # number of writebacks -system.cpu1.dcache.writebacks::total 324751 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168850 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 168850 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396175 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1396175 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565025 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1565025 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565025 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1565025 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228268 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228268 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161652 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161652 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12509 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12509 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10578 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10578 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389920 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389920 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389920 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389920 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2830993566 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2830993566 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6516328872 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6516328872 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88639506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88639506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31988580 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31988580 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9347322438 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9347322438 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9347322438 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9347322438 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168914513007 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168914513007 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25825904490 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25825904490 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194740417497 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194740417497 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026212 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026212 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028376 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028376 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112187 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112187 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027068 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027068 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12402.060587 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12402.060587 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40310.845965 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40310.845965 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7086.058518 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7086.058518 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.066931 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.066931 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324902 # number of writebacks +system.cpu1.dcache.writebacks::total 324902 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170345 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 170345 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396167 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1396167 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1435 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1435 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566512 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1566512 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566512 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1566512 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228371 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228371 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161692 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161692 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12502 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12502 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10574 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10574 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 390063 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 390063 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 390063 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 390063 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2847018297 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2847018297 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7247965426 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7247965426 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87929505 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87929505 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31688093 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31688093 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10094983723 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 10094983723 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10094983723 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 10094983723 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925175261 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925175261 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25838951416 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25838951416 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194764126677 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194764126677 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026235 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028384 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028384 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112335 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112335 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100256 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100256 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027085 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027085 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12466.636731 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12466.636731 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44825.751589 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44825.751589 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7033.235082 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7033.235082 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 2996.793361 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2996.793361 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2298,18 +2521,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 582931892511 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 582931892511 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 582931892511 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 582931892511 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612781961046 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 612781961046 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612781961046 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 612781961046 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41731 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41730 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48851 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index ab328c798..b60e42a06 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,132 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.524310 # Number of seconds simulated -sim_ticks 2524309551500 # Number of ticks simulated -final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525141 # Number of seconds simulated +sim_ticks 2525141046500 # Number of ticks simulated +final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65403 # Simulator instruction rate (inst/s) -host_op_rate 84155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2737677908 # Simulator tick rate (ticks/s) -host_mem_usage 401408 # Number of bytes of host memory used -host_seconds 922.06 # Real time elapsed on the host -sim_insts 60305560 # Number of instructions simulated -sim_ops 77596391 # Number of ops (including micro ops) simulated +host_inst_rate 61643 # Simulator instruction rate (inst/s) +host_op_rate 79318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2581152882 # Simulator tick rate (ticks/s) +host_mem_usage 426780 # Number of bytes of host memory used +host_seconds 978.30 # Real time elapsed on the host +sim_insts 60305756 # Number of instructions simulated +sim_ops 77596741 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory -system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 966197440 # Total number of bytes read from memory -system.physmem.bytesWritten 52040704 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2524308440000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14942208 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154591 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754018 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59118 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096843 # Number of read requests accepted +system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue +system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943582 # Per bank write bursts +system.physmem.perBankRdBursts::1 943145 # Per bank write bursts +system.physmem.perBankRdBursts::2 939291 # Per bank write bursts +system.physmem.perBankRdBursts::3 939307 # Per bank write bursts +system.physmem.perBankRdBursts::4 943115 # Per bank write bursts +system.physmem.perBankRdBursts::5 943141 # Per bank write bursts +system.physmem.perBankRdBursts::6 939138 # Per bank write bursts +system.physmem.perBankRdBursts::7 938546 # Per bank write bursts +system.physmem.perBankRdBursts::8 943996 # Per bank write bursts +system.physmem.perBankRdBursts::9 943390 # Per bank write bursts +system.physmem.perBankRdBursts::10 938426 # Per bank write bursts +system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.perBankRdBursts::12 943928 # Per bank write bursts +system.physmem.perBankRdBursts::13 943533 # Per bank write bursts +system.physmem.perBankRdBursts::14 939234 # Per bank write bursts +system.physmem.perBankRdBursts::15 938672 # Per bank write bursts +system.physmem.perBankWrBursts::0 6704 # Per bank write bursts +system.physmem.perBankWrBursts::1 6457 # Per bank write bursts +system.physmem.perBankWrBursts::2 6598 # Per bank write bursts +system.physmem.perBankWrBursts::3 6635 # Per bank write bursts +system.physmem.perBankWrBursts::4 6561 # Per bank write bursts +system.physmem.perBankWrBursts::5 6794 # Per bank write bursts +system.physmem.perBankWrBursts::6 6789 # Per bank write bursts +system.physmem.perBankWrBursts::7 6723 # Per bank write bursts +system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankWrBursts::9 6877 # Per bank write bursts +system.physmem.perBankWrBursts::10 6538 # Per bank write bursts +system.physmem.perBankWrBursts::11 6183 # Per bank write bursts +system.physmem.perBankWrBursts::12 7149 # Per bank write bursts +system.physmem.perBankWrBursts::13 6765 # Per bank write bursts +system.physmem.perBankWrBursts::14 7038 # Per bank write bursts +system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 36 # Read request sizes (log2) +system.physmem.readPktSize::3 14942208 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 154599 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 59125 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -140,294 +142,604 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation -system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests -system.physmem.totBusLat 75453215000 # Total cycles spent in databus access -system.physmem.totBankLat 15307050000 # Total cycles spent in bank access -system.physmem.avgQLat 19314.15 # Average queueing delay per request -system.physmem.avgBankLat 1014.34 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25328.49 # Average memory access latency -system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 14.41 # Average write queue length over time -system.physmem.readRowHits 15065383 # Number of row buffer hits during reads -system.physmem.writeRowHits 94229 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes -system.physmem.avgGap 158662.04 # Average gap between requests +system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 84 0.10% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 98 0.11% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 5 0.01% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 17 0.02% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 80 0.09% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 74 0.09% 71.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 645 0.75% 72.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 72 0.08% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 78 0.09% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 28 0.03% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 5 0.01% 72.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 407 0.47% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 18 0.02% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 3 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 147 0.17% 73.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 144 0.17% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 279 0.32% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 73 0.08% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 77 0.09% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 5 0.01% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 263 0.31% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 82 0.10% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 140 0.16% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 343 0.40% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 96 0.11% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 2 0.00% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 82 0.10% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 14 0.02% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 17 0.02% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 2 0.00% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 77 0.09% 75.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 84 0.10% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 400 0.46% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 80 0.09% 76.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 136 0.16% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.02% 76.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 351 0.41% 76.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 2 0.00% 76.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 73 0.08% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 83 0.10% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 83 0.10% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 387 0.45% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 78 0.09% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 89 0.10% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 72 0.08% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 4 0.00% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 349 0.41% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 19 0.02% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 133 0.15% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 78 0.09% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 401 0.47% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 2 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 82 0.10% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 77 0.09% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 15 0.02% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 403 0.47% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 11 0.01% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 83 0.10% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 97 0.11% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 341 0.40% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 143 0.17% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 77 0.09% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 85 0.10% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 2 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 268 0.31% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 76 0.09% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 74 0.09% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 2 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 271 0.31% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 145 0.17% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 148 0.17% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 4 0.00% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 398 0.46% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 18 0.02% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 78 0.09% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 83 0.10% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 642 0.75% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 73 0.08% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 78 0.09% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 27 0.03% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 406 0.47% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 16 0.02% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 144 0.17% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 147 0.17% 84.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 269 0.31% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 87 0.10% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 72 0.08% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 2 0.00% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 77 0.09% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 268 0.31% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 81 0.09% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 77 0.09% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 1 0.00% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 144 0.17% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 2 0.00% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 338 0.39% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 1 0.00% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 91 0.11% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 83 0.10% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 11 0.01% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 404 0.47% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 15 0.02% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 77 0.09% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 84 0.10% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 401 0.47% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation +system.physmem.totQLat 365610387500 # Total ticks spent queuing +system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks +system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing +system.physmem.readRowHits 14986740 # Number of row buffer hits during reads +system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes +system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -440,50 +752,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54917647 # Throughput (bytes/s) +system.membus.throughput 54899945 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16149440 # Transaction distribution system.membus.trans_dist::ReadResp 16149440 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59118 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution -system.membus.trans_dist::ReadExReq 131433 # Transaction distribution -system.membus.trans_dist::ReadExResp 131433 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 59125 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution +system.membus.trans_dist::ReadExReq 131442 # Transaction distribution +system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138629141 # Total data (bytes) +system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630105 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -491,13 +803,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48301509 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution +system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution system.iobus.trans_dist::WriteResp 8157 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -519,12 +831,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -546,14 +858,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121927961 # Total data (bytes) +system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121927965 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -599,42 +911,42 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14390442 # Number of BP lookups -system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits +system.cpu.branchPred.lookups 14384905 # Number of BP lookups +system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51188083 # DTB read hits -system.cpu.dtb.read_misses 64353 # DTB read misses -system.cpu.dtb.write_hits 11697459 # DTB write hits -system.cpu.dtb.write_misses 15788 # DTB write misses +system.cpu.dtb.read_hits 51179212 # DTB read hits +system.cpu.dtb.read_misses 64531 # DTB read misses +system.cpu.dtb.write_hits 11698539 # DTB write hits +system.cpu.dtb.write_misses 15837 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3571 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51252436 # DTB read accesses -system.cpu.dtb.write_accesses 11713247 # DTB write accesses +system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51243743 # DTB read accesses +system.cpu.dtb.write_accesses 11714376 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62885542 # DTB hits -system.cpu.dtb.misses 80141 # DTB misses -system.cpu.dtb.accesses 62965683 # DTB accesses -system.cpu.itb.inst_hits 11520428 # ITB inst hits -system.cpu.itb.inst_misses 11439 # ITB inst misses +system.cpu.dtb.hits 62877751 # DTB hits +system.cpu.dtb.misses 80368 # DTB misses +system.cpu.dtb.accesses 62958119 # DTB accesses +system.cpu.itb.inst_hits 11513998 # ITB inst hits +system.cpu.itb.inst_misses 11344 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -643,114 +955,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2486 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2483 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11531867 # ITB inst accesses -system.cpu.itb.hits 11520428 # DTB hits -system.cpu.itb.misses 11439 # DTB misses -system.cpu.itb.accesses 11531867 # DTB accesses -system.cpu.numCycles 473080437 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11525342 # ITB inst accesses +system.cpu.itb.hits 11513998 # DTB hits +system.cpu.itb.misses 11344 # DTB misses +system.cpu.itb.accesses 11525342 # DTB accesses +system.cpu.numCycles 474882944 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available @@ -778,13 +1090,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -797,397 +1109,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued -system.cpu.iq.rate 0.259812 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued +system.cpu.iq.rate 0.258795 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221034 # number of nop insts executed -system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed -system.cpu.iew.exec_branches 11474602 # Number of branches executed -system.cpu.iew.exec_stores 12209197 # Number of stores executed -system.cpu.iew.exec_rate 0.255417 # Inst execution rate -system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47030253 # num instructions producing a value -system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value +system.cpu.iew.exec_nop 221869 # number of nop insts executed +system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475076 # Number of branches executed +system.cpu.iew.exec_stores 12210518 # Number of stores executed +system.cpu.iew.exec_rate 0.254424 # Inst execution rate +system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47026181 # num instructions producing a value +system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60455941 # Number of instructions committed -system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456137 # Number of instructions committed +system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385481 # Number of memory references committed -system.cpu.commit.loads 15653838 # Number of loads committed -system.cpu.commit.membars 403568 # Number of memory barriers committed -system.cpu.commit.branches 9961054 # Number of branches committed +system.cpu.commit.refs 27385736 # Number of memory references committed +system.cpu.commit.loads 15654008 # Number of loads committed +system.cpu.commit.membars 403573 # Number of memory barriers committed +system.cpu.commit.branches 9961077 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852229 # Number of committed integer instructions. -system.cpu.commit.function_calls 991205 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. +system.cpu.commit.function_calls 991208 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239241509 # The number of ROB reads -system.cpu.rob.rob_writes 195965670 # The number of ROB writes -system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305560 # Number of Instructions Simulated -system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated -system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547265501 # number of integer regfile reads -system.cpu.int_regfile_writes 87536109 # number of integer regfile writes -system.cpu.fp_regfile_reads 8349 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads -system.cpu.misc_regfile_writes 831835 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution +system.cpu.rob.rob_reads 240636318 # The number of ROB reads +system.cpu.rob.rob_writes 195934369 # The number of ROB writes +system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305756 # Number of Instructions Simulated +system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated +system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547208469 # number of integer regfile reads +system.cpu.int_regfile_writes 87526188 # number of integer regfile writes +system.cpu.fp_regfile_reads 8624 # number of floating regfile reads +system.cpu.fp_regfile_writes 3008 # number of floating regfile writes +system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.misc_regfile_writes 831837 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 979660 # number of replacements -system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits -system.cpu.icache.overall_hits::total 10456897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses -system.cpu.icache.overall_misses::total 1059959 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked +system.cpu.icache.tags.replacements 980741 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits +system.cpu.icache.overall_hits::total 10449649 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses +system.cpu.icache.overall_misses::total 1060761 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79476 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981285 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981285 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981285 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981285 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64363 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.183198 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.182382 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563463 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000589 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 64371 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51366.694603 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1308,161 +1620,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643614 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits -system.cpu.dcache.overall_hits::total 21018772 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses -system.cpu.dcache.overall_misses::total 3700946 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits +system.cpu.dcache.overall_hits::total 21010251 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses +system.cpu.dcache.overall_misses::total 3701471 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks -system.cpu.dcache.writebacks::total 607864 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks +system.cpu.dcache.writebacks::total 607699 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1484,10 +1796,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 2afd1181d..506582551 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,182 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403596 # Number of seconds simulated -sim_ticks 2403595690000 # Number of ticks simulated -final_tick 2403595690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403658 # Number of seconds simulated +sim_ticks 2403657545000 # Number of ticks simulated +final_tick 2403657545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196358 # Simulator instruction rate (inst/s) -host_op_rate 252199 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7823307249 # Simulator tick rate (ticks/s) -host_mem_usage 401444 # Number of bytes of host memory used -host_seconds 307.24 # Real time elapsed on the host -sim_insts 60328186 # Number of instructions simulated -sim_ops 77484426 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 183148 # Simulator instruction rate (inst/s) +host_op_rate 235229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7297160965 # Simulator tick rate (ticks/s) +host_mem_usage 427808 # Number of bytes of host memory used +host_seconds 329.40 # Real time elapsed on the host +sim_insts 60328152 # Number of instructions simulated +sim_ops 77483430 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7050896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7048656 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 64832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 677568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 64128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 675392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 187392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1347680 # Number of bytes read from this memory -system.physmem.bytes_read::total 124659728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu2.data 1353632 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 64128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 187392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743680 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298324 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759496 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 763936 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3744384 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298192 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159304 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558320 # Number of bytes written to this memory +system.physmem.bytes_written::total 6760200 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110169 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10587 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1002 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10553 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 2928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21065 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512388 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58495 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324581 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389548 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812449 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47769711 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.data 21158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58506 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324548 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39826 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389580 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812460 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47768482 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 212814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2933478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2932471 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 281898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 560693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 212814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77963 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557533 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 563155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557786 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540090 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812243 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47769711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648312 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47768482 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 212814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3473637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3472561 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1208969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54676094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13479442 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 446461 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 13479442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 446461 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 862684288 # Total number of bytes read from memory -system.physmem.bytesWritten 28573504 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 109828768 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2811124 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 837727 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 837365 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 837535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 838843 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 839834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 839919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 839832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 840753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 841921 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 844340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 845026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 846543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 848256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 848014 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 846904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 846630 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2603 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2565 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 3057 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 3449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 3230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2572 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 3826 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 3451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2556 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2402560453500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 8 # Categorize read packet sizes -system.physmem.readPktSize::3 13443840 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35594 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 429373 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17088 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 871692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 848345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 868847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3321058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2492431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2492072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2465727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 13341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 25821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 38140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.bw_total::cpu1.inst 26679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 347261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1211467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54675779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13467317 # Number of read requests accepted +system.physmem.writeReqs 446508 # Number of write requests accepted +system.physmem.readBursts 13467317 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446508 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 861908288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 2866432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109734624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2812152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 401719 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2372 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 837719 # Per bank write bursts +system.physmem.perBankRdBursts::1 837389 # Per bank write bursts +system.physmem.perBankRdBursts::2 837556 # Per bank write bursts +system.physmem.perBankRdBursts::3 837999 # Per bank write bursts +system.physmem.perBankRdBursts::4 838842 # Per bank write bursts +system.physmem.perBankRdBursts::5 838880 # Per bank write bursts +system.physmem.perBankRdBursts::6 838796 # Per bank write bursts +system.physmem.perBankRdBursts::7 839742 # Per bank write bursts +system.physmem.perBankRdBursts::8 840911 # Per bank write bursts +system.physmem.perBankRdBursts::9 843323 # Per bank write bursts +system.physmem.perBankRdBursts::10 844015 # Per bank write bursts +system.physmem.perBankRdBursts::11 845500 # Per bank write bursts +system.physmem.perBankRdBursts::12 847242 # Per bank write bursts +system.physmem.perBankRdBursts::13 846993 # Per bank write bursts +system.physmem.perBankRdBursts::14 845867 # Per bank write bursts +system.physmem.perBankRdBursts::15 846543 # Per bank write bursts +system.physmem.perBankWrBursts::0 2729 # Per bank write bursts +system.physmem.perBankWrBursts::1 2587 # Per bank write bursts +system.physmem.perBankWrBursts::2 2574 # Per bank write bursts +system.physmem.perBankWrBursts::3 3045 # Per bank write bursts +system.physmem.perBankWrBursts::4 3468 # Per bank write bursts +system.physmem.perBankWrBursts::5 3206 # Per bank write bursts +system.physmem.perBankWrBursts::6 2544 # Per bank write bursts +system.physmem.perBankWrBursts::7 2321 # Per bank write bursts +system.physmem.perBankWrBursts::8 2236 # Per bank write bursts +system.physmem.perBankWrBursts::9 2427 # Per bank write bursts +system.physmem.perBankWrBursts::10 2367 # Per bank write bursts +system.physmem.perBankWrBursts::11 2798 # Per bank write bursts +system.physmem.perBankWrBursts::12 3813 # Per bank write bursts +system.physmem.perBankWrBursts::13 3444 # Per bank write bursts +system.physmem.perBankWrBursts::14 2680 # Per bank write bursts +system.physmem.perBankWrBursts::15 2549 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2402622305000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 8 # Read request sizes (log2) +system.physmem.readPktSize::3 13431664 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 35645 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 429406 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 17102 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 965936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 943404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 937737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3274872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2367219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2366833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2384991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 47923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 55146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 17633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 17582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -190,30 +176,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 28 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -222,473 +208,633 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22080 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 39201.023188 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 6463.207550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31878.388388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 3036 13.75% 13.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 1347 6.10% 19.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 793 3.59% 23.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 589 2.67% 26.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 391 1.77% 27.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 355 1.61% 29.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 279 1.26% 30.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 235 1.06% 31.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 172 0.78% 32.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 146 0.66% 33.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 130 0.59% 33.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 164 0.74% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 77 0.35% 34.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 80 0.36% 35.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 63 0.29% 35.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 74 0.34% 35.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 30 0.14% 36.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 39 0.18% 36.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 22 0.10% 36.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 39 0.18% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 28 0.13% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 83 0.38% 37.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 95 0.43% 37.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 108 0.49% 37.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 17 0.08% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 45 0.20% 38.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 23 0.10% 38.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 32 0.14% 38.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 10 0.05% 38.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 20 0.09% 38.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 6 0.03% 38.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 23 0.10% 38.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 8 0.04% 38.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 15 0.07% 38.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 1 0.00% 38.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 6 0.03% 38.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 4 0.02% 38.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 10 0.05% 38.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 3 0.01% 38.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 2 0.01% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 1 0.00% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 3 0.01% 38.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 5 0.02% 38.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 8 0.04% 39.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 3 0.01% 39.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 3 0.01% 39.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 1 0.00% 39.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 6 0.03% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 2 0.01% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 2 0.01% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 5 0.02% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 6 0.03% 39.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 2 0.01% 39.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 3 0.01% 39.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 1 0.00% 39.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 2 0.01% 39.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 2 0.01% 39.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 2 0.01% 39.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 39.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 1 0.00% 39.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 3 0.01% 39.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 7 0.03% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 3 0.01% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 1 0.00% 39.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 2 0.01% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 2 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 1 0.00% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 2 0.01% 39.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 1 0.00% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 2 0.01% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 1 0.00% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 1 0.00% 39.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 15 0.07% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 2 0.01% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6991 1 0.00% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 3 0.01% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 2 0.01% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 1 0.00% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7759 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 2 0.01% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 1 0.00% 39.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 3 0.01% 39.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 45 0.20% 39.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 150 0.68% 40.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 12 0.05% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8975 1 0.00% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 1 0.00% 40.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 1 0.00% 40.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12047 2 0.01% 40.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14863 1 0.00% 40.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16335 1 0.00% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 1 0.00% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 1 0.00% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20239 1 0.00% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22799 1 0.00% 40.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 1 0.00% 40.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25871 1 0.00% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 1 0.00% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 40.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 2 0.01% 40.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31247 1 0.00% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33039 1 0.00% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33295 3 0.01% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 1 0.00% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34319 1 0.00% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34831 1 0.00% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35855 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37903 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38927 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40207 1 0.00% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40975 1 0.00% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41999 1 0.00% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47887 1 0.00% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52239 1 0.00% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53263 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53504-53519 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56064-56079 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59407 1 0.00% 40.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 13109 59.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22080 # Bytes accessed per row activation -system.physmem.totQLat 259652718750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 339530350000 # Sum of mem lat for all requests -system.physmem.totBusLat 67397210000 # Total cycles spent in databus access -system.physmem.totBankLat 12480421250 # Total cycles spent in bank access -system.physmem.avgQLat 19262.87 # Average queueing delay per request -system.physmem.avgBankLat 925.89 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25188.75 # Average memory access latency -system.physmem.avgRdBW 358.91 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 11.89 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 45.69 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.17 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.90 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 13462207 # Number of row buffer hits during reads -system.physmem.writeRowHits 40077 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 8.98 # Row buffer hit rate for writes -system.physmem.avgGap 172524.57 # Average gap between requests -system.membus.throughput 55673401 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13817014 # Transaction distribution -system.membus.trans_dist::ReadResp 13817014 # Transaction distribution -system.membus.trans_dist::WriteReq 432240 # Transaction distribution -system.membus.trans_dist::WriteResp 432240 # Transaction distribution -system.membus.trans_dist::Writeback 17088 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2349 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2349 # Transaction distribution -system.membus.trans_dist::ReadExReq 28007 # Transaction distribution -system.membus.trans_dist::ReadExResp 28007 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1688628 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26887680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28576308 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740538 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5089172 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5830178 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107550720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113380898 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133816346 # Total data (bytes) +system.physmem.bytesPerActivate::samples 48451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 17848.429795 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3200.071202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 18346.519598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 8608 17.77% 17.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 4824 9.96% 27.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 1006 2.08% 29.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 654 1.35% 31.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 399 0.82% 31.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 406 0.84% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 283 0.58% 33.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 297 0.61% 34.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 176 0.36% 34.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 170 0.35% 34.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 172 0.35% 35.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 155 0.32% 35.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 77 0.16% 35.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 80 0.17% 35.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 48 0.10% 35.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 416 0.86% 36.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 18 0.04% 36.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 23 0.05% 36.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 23 0.05% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 108 0.22% 37.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 17 0.04% 37.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 165 0.34% 37.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 12 0.02% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 112 0.23% 37.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 15 0.03% 37.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 32 0.07% 37.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 7 0.01% 37.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 140 0.29% 38.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 6 0.01% 38.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 13 0.03% 38.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 455 0.94% 39.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 12 0.02% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 2 0.00% 39.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 72 0.15% 39.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 5 0.01% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 6 0.01% 39.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 5 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 10 0.02% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 5 0.01% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 8 0.02% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 2 0.00% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 505 1.04% 40.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 5 0.01% 40.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 5 0.01% 40.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 65 0.13% 40.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 5 0.01% 40.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.02% 40.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 15 0.03% 40.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 3 0.01% 40.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 4 0.01% 40.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 6 0.01% 40.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 66 0.14% 40.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 3 0.01% 40.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 327 0.67% 41.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 5 0.01% 41.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 8 0.02% 41.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 2 0.00% 41.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 130 0.27% 41.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 6 0.01% 41.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 4 0.01% 41.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.01% 41.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 68 0.14% 41.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.01% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 5 0.01% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 4 0.01% 42.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.01% 42.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 7 0.01% 42.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 258 0.53% 42.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 42.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 4 0.01% 42.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 3 0.01% 42.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 88 0.18% 42.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 3 0.01% 42.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 8 0.02% 42.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.01% 42.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 92 0.19% 42.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 4 0.01% 43.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 7 0.01% 43.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 43.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 102 0.21% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 2 0.00% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 3 0.01% 43.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 481 0.99% 44.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 2 0.00% 44.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 3 0.01% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 1 0.00% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 3 0.01% 44.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 67 0.14% 44.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 5 0.01% 44.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 6 0.01% 44.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 131 0.27% 44.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 1 0.00% 44.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 1 0.00% 44.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 72 0.15% 44.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 2 0.00% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 13 0.03% 44.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 133 0.27% 45.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 66 0.14% 45.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 64 0.13% 45.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 385 0.79% 46.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 65 0.13% 46.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 128 0.26% 46.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 73 0.15% 46.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 128 0.26% 47.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 64 0.13% 47.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 478 0.99% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 63 0.13% 48.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 1 0.00% 48.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 89 0.18% 48.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 86 0.18% 48.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 257 0.53% 49.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 1 0.00% 49.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 65 0.13% 49.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 320 0.66% 50.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 64 0.13% 50.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 14 0.03% 50.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 50.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 64 0.13% 50.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 499 1.03% 51.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 64 0.13% 51.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 442 0.91% 52.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 66 0.14% 53.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 72 0.15% 53.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 362 0.75% 54.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 2 0.00% 54.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 6 0.01% 54.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 781 1.61% 55.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 7 0.01% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 362 0.75% 56.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 72 0.15% 56.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 64 0.13% 56.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 128 0.26% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 57.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 442 0.91% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 64 0.13% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 499 1.03% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 64 0.13% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 12 0.02% 59.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 66 0.14% 59.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 320 0.66% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 128 0.26% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 256 0.53% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 85 0.18% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 87 0.18% 61.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 64 0.13% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 478 0.99% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 67 0.14% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 128 0.26% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 71 0.15% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 129 0.27% 63.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 64 0.13% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 384 0.79% 64.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 64 0.13% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 64 0.13% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 129 0.27% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 70 0.14% 64.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 128 0.26% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26048-26055 1 0.00% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 66 0.14% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 480 0.99% 66.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 64 0.13% 66.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 89 0.18% 66.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 86 0.18% 66.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 1 0.00% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 67.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 127 0.26% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 320 0.66% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 65 0.13% 68.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 13 0.03% 68.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 64 0.13% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 497 1.03% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 64 0.13% 69.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 442 0.91% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 65 0.13% 71.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 72 0.15% 71.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 362 0.75% 72.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 1 0.00% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 6 0.01% 72.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 778 1.61% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 5 0.01% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 1 0.00% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 2 0.00% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 362 0.75% 74.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 72 0.15% 74.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 66 0.14% 74.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 443 0.91% 75.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 499 1.03% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 64 0.13% 77.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 13 0.03% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 321 0.66% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 127 0.26% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 1 0.00% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 257 0.53% 79.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 1 0.00% 79.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 86 0.18% 79.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 89 0.18% 79.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 479 0.99% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39495 1 0.00% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 128 0.26% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 71 0.15% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 128 0.26% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 64 0.13% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 64 0.13% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 384 0.79% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 129 0.27% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 71 0.15% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 128 0.26% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 67 0.14% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 477 0.98% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 64 0.13% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 87 0.18% 84.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 84 0.17% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 128 0.26% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 320 0.66% 86.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 65 0.13% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 12 0.02% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 64 0.13% 86.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 498 1.03% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 1 0.00% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 64 0.13% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 443 0.91% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 66 0.14% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 72 0.15% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 362 0.75% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 2 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 2 0.00% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 1 0.00% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 7 0.01% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4749 9.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48451 # Bytes accessed per row activation +system.physmem.totQLat 326245474250 # Total ticks spent queuing +system.physmem.totMemAccLat 407559786750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67336585000 # Total ticks spent in databus transfers +system.physmem.totBankLat 13977727500 # Total ticks spent accessing banks +system.physmem.avgQLat 24224.98 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1037.90 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30262.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.81 # Data bus utilization in percentage +system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing +system.physmem.readRowHits 13424164 # Number of row buffer hits during reads +system.physmem.writeRowHits 39490 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 88.17 # Row buffer hit rate for writes +system.physmem.avgGap 172678.78 # Average gap between requests +system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.76 # Percentage of time for which DRAM has all the banks in precharge state +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55673060 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13803640 # Transaction distribution +system.membus.trans_dist::ReadResp 13803640 # Transaction distribution +system.membus.trans_dist::WriteReq 432247 # Transaction distribution +system.membus.trans_dist::WriteResp 432247 # Transaction distribution +system.membus.trans_dist::Writeback 17102 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2372 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2372 # Transaction distribution +system.membus.trans_dist::ReadExReq 28053 # Transaction distribution +system.membus.trans_dist::ReadExResp 28053 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 734214 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1686398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26863328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26863328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28549726 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 738102 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5093464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5832006 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107453312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107453312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113285318 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133818970 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 415555000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 417653000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 219000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14607219000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14595653500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1602404901 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1597948868 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30345557250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30334798000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 63232 # number of replacements -system.l2c.tags.tagsinuse 50385.545216 # Cycle average of tags in use -system.l2c.tags.total_refs 1748703 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128626 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.595253 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375561795000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36863.517049 # Average occupied blocks per requestor +system.l2c.tags.replacements 63262 # number of replacements +system.l2c.tags.tagsinuse 50391.923695 # Cycle average of tags in use +system.l2c.tags.total_refs 1749292 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128659 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.596344 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375568862000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36846.357046 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5225.910742 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3838.689123 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 514.601539 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 693.553663 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.833611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974677 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1665.560742 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1574.910611 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562493 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5224.016956 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3834.498559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 503.830830 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 691.484420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832714 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1696.766805 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1584.142905 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562231 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # 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number of ReadReq hits -system.l2c.ReadReq_hits::total 1290694 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597529 # number of Writeback hits -system.l2c.Writeback_hits::total 597529 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.007688 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010551 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000150 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024172 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768920 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8708 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3160 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 467622 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 176862 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 57728.391859 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56914.939240 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61819.101678 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52489.875253 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 57728.391859 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56914.939240 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu2.data 21755 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 36522 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 58877500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 71259000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 687500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 182826500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 164184000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 477897000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4670967 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10281528 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14952495 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606681022 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1218059105 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1824740127 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 58877500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 677940022 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 687500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 182826500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1382243105 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2302637127 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 58877500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 677940022 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 687500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 182826500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1382243105 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2302637127 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25057289000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26363515500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51420804500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 935323010 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8517824000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9453147010 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25992612010 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34881339500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60873951510 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017158 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018765 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005785 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991507 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.986564 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.508676 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.344249 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.366927 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117133 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.115680 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116263 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023420 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115680 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116263 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023420 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63510.695187 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64946.202532 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62947.444679 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.070664 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001.486381 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.668896 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62525.097599 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 63351.490352 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63074.321708 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -853,52 +987,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58805533 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1021031 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1021030 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432240 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432240 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 264941 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1503 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1506 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80714 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80714 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830128 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423683 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15492 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51832 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3321135 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26541184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37337186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 63984874 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141242678 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 102048 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2176255494 # Layer occupancy (ticks) +system.toL2Bus.throughput 58815755 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1021426 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1021425 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432247 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432247 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265552 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1513 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1515 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80586 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80586 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831264 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423236 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15497 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52067 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3322064 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26578304 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37416070 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21580 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84860 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64100814 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141271334 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 101600 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2179143758 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1870489205 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1872769954 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1849664390 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1848854181 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10070717 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10116966 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30771737 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30973250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48764104 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13809372 # Transaction distribution -system.iobus.trans_dist::ReadResp 13809372 # Transaction distribution -system.iobus.trans_dist::WriteReq 2797 # Transaction distribution -system.iobus.trans_dist::WriteResp 2797 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11494 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 22 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48762849 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13795996 # Transaction distribution +system.iobus.trans_dist::ReadResp 13795996 # Transaction distribution +system.iobus.trans_dist::WriteReq 2775 # Transaction distribution +system.iobus.trans_dist::WriteResp 2775 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11418 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721570 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 719202 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -914,18 +1048,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 736658 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887680 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26887680 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27624338 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15458 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6052 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 44 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 734214 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26863328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26863328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27597542 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15382 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715532 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -941,18 +1075,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 740538 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550720 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550720 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108291258 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 738102 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107453312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107453312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108191414 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 117209190 # Total data (bytes) -system.iobus.reqLayer0.occupancy 8031000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 7974000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1513000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1515000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 128000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -960,7 +1094,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 361287000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 360101000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -992,444 +1126,444 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13443840000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13431664000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 733861000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 731439000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36856295750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36823110000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8004008 # DTB read hits -system.cpu0.dtb.read_misses 6222 # DTB read misses -system.cpu0.dtb.write_hits 6595133 # DTB write hits -system.cpu0.dtb.write_misses 2001 # DTB write misses +system.cpu0.dtb.read_hits 7991455 # DTB read hits +system.cpu0.dtb.read_misses 6184 # DTB read misses +system.cpu0.dtb.write_hits 6591541 # DTB write hits +system.cpu0.dtb.write_misses 1989 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5693 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 118 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8010230 # DTB read accesses -system.cpu0.dtb.write_accesses 6597134 # DTB write accesses +system.cpu0.dtb.perms_faults 208 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7997639 # DTB read accesses +system.cpu0.dtb.write_accesses 6593530 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14599141 # DTB hits -system.cpu0.dtb.misses 8223 # DTB misses -system.cpu0.dtb.accesses 14607364 # DTB accesses -system.cpu0.itb.inst_hits 32379967 # ITB inst hits -system.cpu0.itb.inst_misses 3492 # ITB inst misses +system.cpu0.dtb.hits 14582996 # DTB hits +system.cpu0.dtb.misses 8173 # DTB misses +system.cpu0.dtb.accesses 14591169 # DTB accesses +system.cpu0.itb.inst_hits 32325256 # ITB inst hits +system.cpu0.itb.inst_misses 3454 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2598 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2571 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32383459 # ITB inst accesses -system.cpu0.itb.hits 32379967 # DTB hits -system.cpu0.itb.misses 3492 # DTB misses -system.cpu0.itb.accesses 32383459 # DTB accesses -system.cpu0.numCycles 113662532 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32328710 # ITB inst accesses +system.cpu0.itb.hits 32325256 # DTB hits +system.cpu0.itb.misses 3454 # DTB misses +system.cpu0.itb.accesses 32328710 # DTB accesses +system.cpu0.numCycles 113673861 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31896171 # Number of instructions committed -system.cpu0.committedOps 42061376 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37196625 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5021 # Number of float alu accesses -system.cpu0.num_func_calls 1200231 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4252287 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37196625 # number of integer instructions -system.cpu0.num_fp_insts 5021 # number of float instructions -system.cpu0.num_int_register_reads 189594254 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39319391 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3591 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1432 # number of times the floating registers were written -system.cpu0.num_mem_refs 15267333 # number of memory refs -system.cpu0.num_load_insts 8373046 # Number of load instructions -system.cpu0.num_store_insts 6894287 # Number of store instructions -system.cpu0.num_idle_cycles 110849279.389256 # Number of idle cycles -system.cpu0.num_busy_cycles 2813252.610744 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024751 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975249 # Percentage of idle cycles +system.cpu0.committedInsts 31847112 # Number of instructions committed +system.cpu0.committedOps 42008964 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37152656 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses +system.cpu0.num_func_calls 1198427 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4245737 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37152656 # number of integer instructions +system.cpu0.num_fp_insts 5018 # number of float instructions +system.cpu0.num_int_register_reads 189368889 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39264582 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written +system.cpu0.num_mem_refs 15250074 # number of memory refs +system.cpu0.num_load_insts 8359762 # Number of load instructions +system.cpu0.num_store_insts 6890312 # Number of store instructions +system.cpu0.num_idle_cycles 110868175.114613 # Number of idle cycles +system.cpu0.num_busy_cycles 2805685.885387 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024682 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975318 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891479 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.603901 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43691974 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891991 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.982528 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8175687500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.614782 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.336202 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.652916 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964091 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014329 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020806 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31906072 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8054900 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3731002 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43691974 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31906072 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8054900 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3731002 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43691974 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31906072 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8054900 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3731002 # number of overall hits -system.cpu0.icache.overall_hits::total 43691974 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 476577 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 130192 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 309459 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916228 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 476577 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 130192 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 309459 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916228 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 476577 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 130192 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 309459 # number of overall misses -system.cpu0.icache.overall_misses::total 916228 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1761830250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4180298881 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5942129131 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1761830250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4180298881 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5942129131 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1761830250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4180298881 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5942129131 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32382649 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8185092 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4040461 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44608202 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32382649 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8185092 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4040461 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44608202 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32382649 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8185092 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4040461 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44608202 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014717 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015906 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076590 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020539 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014717 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015906 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076590 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020539 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014717 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015906 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076590 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020539 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13532.553844 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13508.409453 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6485.426260 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13532.553844 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13508.409453 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6485.426260 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13532.553844 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13508.409453 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6485.426260 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4261 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 891412 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.602619 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43641790 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 891924 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.929942 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8178595250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 492.265032 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.623785 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 11.713802 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.961455 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014890 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.022879 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 31851952 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8051251 # 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number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8182654 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4047070 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44557635 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32327911 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8182654 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4047070 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44557635 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014723 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016059 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076224 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020554 # 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average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13497.336438 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13493.936833 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6481.708822 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13497.336438 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13493.936833 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6481.708822 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3646 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 235 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.131915 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3402203278 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4903155028 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1500951750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3402203278 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4903155028 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015906 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070593 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009313 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015906 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070593 # 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number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 556206 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 431 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 431 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 695055 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 695055 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 695055 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 695055 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63959 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 130326 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 194285 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28874 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53313 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1629798751 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3452469351 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5082268102 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1629798751 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3452469351 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5082268102 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27446152500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28893354250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56339506750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1446442000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341405748 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14787847748 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28892594500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42234759998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71127354498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033937 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026616 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014044 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008045 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049643 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043290 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011496 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011496 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12194.749762 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12898.277013 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12666.674473 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29432.525836 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33228.077598 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31894.621436 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11128.319861 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11672.760264 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11486.733281 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597747 # number of writebacks +system.cpu0.dcache.writebacks::total 597747 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 140335 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 140335 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556925 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 556925 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 415 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 415 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 697260 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 697260 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 697260 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 697260 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63653 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131409 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 195062 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28657 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53411 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82068 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1738 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3341 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5079 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92310 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 184820 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 277130 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92310 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 184820 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 277130 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 778293250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1698666084 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2476959334 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 952956511 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1898218478 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2851174989 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19339250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38699751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58039001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1731249761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3596884562 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5328134323 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1731249761 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3596884562 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5328134323 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27375287500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28782575500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56157863000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442314990 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341314242 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14783629232 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28817602490 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42123889742 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70941492232 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033793 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026760 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014101 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019463 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008033 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049937 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043150 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011523 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011523 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12227.125980 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12926.558181 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12698.318145 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33253.882507 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35539.841568 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34741.616574 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.301496 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11583.283747 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11427.249655 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1442,388 +1576,388 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2098287 # DTB read hits -system.cpu1.dtb.read_misses 2070 # DTB read misses -system.cpu1.dtb.write_hits 1420937 # DTB write hits -system.cpu1.dtb.write_misses 371 # DTB write misses +system.cpu1.dtb.read_hits 2096740 # DTB read hits +system.cpu1.dtb.read_misses 2075 # DTB read misses +system.cpu1.dtb.write_hits 1419315 # DTB write hits +system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1726 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1735 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 38 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2100357 # DTB read accesses -system.cpu1.dtb.write_accesses 1421308 # DTB write accesses +system.cpu1.dtb.read_accesses 2098815 # DTB read accesses +system.cpu1.dtb.write_accesses 1419688 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3519224 # DTB hits -system.cpu1.dtb.misses 2441 # DTB misses -system.cpu1.dtb.accesses 3521665 # DTB accesses -system.cpu1.itb.inst_hits 8185092 # ITB inst hits -system.cpu1.itb.inst_misses 1172 # ITB inst misses +system.cpu1.dtb.hits 3516055 # DTB hits +system.cpu1.dtb.misses 2448 # DTB misses +system.cpu1.dtb.accesses 3518503 # DTB accesses +system.cpu1.itb.inst_hits 8182654 # ITB inst hits +system.cpu1.itb.inst_misses 1200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 867 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 888 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8186264 # ITB inst accesses -system.cpu1.itb.hits 8185092 # DTB hits -system.cpu1.itb.misses 1172 # DTB misses -system.cpu1.itb.accesses 8186264 # DTB accesses -system.cpu1.numCycles 580203625 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8183854 # ITB inst accesses +system.cpu1.itb.hits 8182654 # DTB hits +system.cpu1.itb.misses 1200 # DTB misses +system.cpu1.itb.accesses 8183854 # DTB accesses +system.cpu1.numCycles 581318737 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7980801 # Number of instructions committed -system.cpu1.committedOps 10142634 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9072894 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses -system.cpu1.num_func_calls 304668 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1116676 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9072894 # number of integer instructions -system.cpu1.num_fp_insts 2143 # number of float instructions -system.cpu1.num_int_register_reads 52281658 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9864872 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written -system.cpu1.num_mem_refs 3686646 # number of memory refs -system.cpu1.num_load_insts 2191239 # Number of load instructions -system.cpu1.num_store_insts 1495407 # Number of store instructions -system.cpu1.num_idle_cycles 544226668.771142 # Number of idle cycles -system.cpu1.num_busy_cycles 35976956.228858 # Number of busy cycles -system.cpu1.not_idle_fraction 0.062007 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.937993 # Percentage of idle cycles +system.cpu1.committedInsts 7974693 # Number of instructions committed +system.cpu1.committedOps 10126531 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9058549 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1938 # Number of float alu accesses +system.cpu1.num_func_calls 304877 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1114107 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9058549 # number of integer instructions +system.cpu1.num_fp_insts 1938 # number of float instructions +system.cpu1.num_int_register_reads 52214198 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9844324 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1424 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_mem_refs 3684398 # number of memory refs +system.cpu1.num_load_insts 2190368 # Number of load instructions +system.cpu1.num_store_insts 1494030 # Number of store instructions +system.cpu1.num_idle_cycles 546218260.044225 # Number of idle cycles +system.cpu1.num_busy_cycles 35100476.955774 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060381 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939619 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4715473 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3836739 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223495 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3141743 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2527502 # Number of BTB hits +system.cpu2.branchPred.lookups 4723221 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3843292 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 222521 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3120017 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2528037 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.449037 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 411571 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21589 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 81.026385 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 412365 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21211 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10976033 # DTB read hits -system.cpu2.dtb.read_misses 22752 # DTB read misses -system.cpu2.dtb.write_hits 3346841 # DTB write hits -system.cpu2.dtb.write_misses 6453 # DTB write misses +system.cpu2.dtb.read_hits 10969613 # DTB read hits +system.cpu2.dtb.read_misses 23045 # DTB read misses +system.cpu2.dtb.write_hits 3352330 # DTB write hits +system.cpu2.dtb.write_misses 6440 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2303 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 671 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 173 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2328 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 460 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10998785 # DTB read accesses -system.cpu2.dtb.write_accesses 3353294 # DTB write accesses +system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10992658 # DTB read accesses +system.cpu2.dtb.write_accesses 3358770 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14322874 # DTB hits -system.cpu2.dtb.misses 29205 # DTB misses -system.cpu2.dtb.accesses 14352079 # DTB accesses -system.cpu2.itb.inst_hits 4041881 # ITB inst hits -system.cpu2.itb.inst_misses 4586 # ITB inst misses +system.cpu2.dtb.hits 14321943 # DTB hits +system.cpu2.dtb.misses 29485 # DTB misses +system.cpu2.dtb.accesses 14351428 # DTB accesses +system.cpu2.itb.inst_hits 4048520 # ITB inst hits +system.cpu2.itb.inst_misses 4581 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1634 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1671 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1002 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1028 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4046467 # ITB inst accesses -system.cpu2.itb.hits 4041881 # DTB hits -system.cpu2.itb.misses 4586 # DTB misses -system.cpu2.itb.accesses 4046467 # DTB accesses -system.cpu2.numCycles 88343562 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4053101 # ITB inst accesses +system.cpu2.itb.hits 4048520 # DTB hits +system.cpu2.itb.misses 4581 # DTB misses +system.cpu2.itb.accesses 4053101 # DTB accesses +system.cpu2.numCycles 88363580 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9345666 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32463757 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4715473 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2939073 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6849430 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1758819 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50954 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18707448 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 820 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32452 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 720275 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 489 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4040467 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 290046 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2014 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36916106 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.056921 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.443441 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9342746 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32497136 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4723221 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2940402 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6855397 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1756636 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50446 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18848050 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 925 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 34178 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 721824 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4047074 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289511 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37061318 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.053700 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.440521 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30071749 81.46% 81.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 384570 1.04% 82.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 513519 1.39% 83.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 818109 2.22% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 634612 1.72% 87.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 341178 0.92% 88.75% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1041484 2.82% 91.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 228835 0.62% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2882050 7.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30210914 81.52% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385385 1.04% 82.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 515477 1.39% 83.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 820134 2.21% 86.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 628486 1.70% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 342820 0.93% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1044433 2.82% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 229207 0.62% 92.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2884462 7.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36916106 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053377 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367472 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9928442 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19318553 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6233841 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 278394 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1155918 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 607967 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53425 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36920328 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 180410 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1155918 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10478416 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6754031 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11105712 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5942637 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1478447 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34829842 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2448 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 324847 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 890462 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 131 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37304234 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 159387361 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148242103 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3218 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26430435 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10873798 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231762 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 208068 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3242623 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6608021 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3899448 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530191 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 761841 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32138723 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 510591 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34782251 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 56051 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7186073 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19057300 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 153940 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36916106 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.942197 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.600639 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37061318 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053452 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367766 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9926500 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19460558 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6238388 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 279816 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1155131 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608208 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53066 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36958585 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 178391 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1155131 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10476553 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6920166 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11076723 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5947862 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1483966 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34870863 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2458 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 328650 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 889849 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 96 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37358262 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 159586833 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148423376 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3369 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26507725 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10850536 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 232822 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 209087 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3256835 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6623705 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3904787 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 530493 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 775113 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32195808 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 505146 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34809127 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54913 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7172484 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19086467 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 147942 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37061318 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.939231 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.598560 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24329752 65.91% 65.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3820331 10.35% 76.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2317804 6.28% 82.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2003808 5.43% 87.96% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2797781 7.58% 95.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 970796 2.63% 98.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 496090 1.34% 99.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144708 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35036 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24455957 65.99% 65.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3833682 10.34% 76.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2322342 6.27% 82.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2005181 5.41% 88.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2795966 7.54% 95.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 971107 2.62% 98.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 498292 1.34% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144261 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34530 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36916106 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37061318 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19314 1.26% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407095 91.52% 92.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 111138 7.23% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19660 1.28% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1402550 91.51% 92.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110445 7.21% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61377 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19718575 56.69% 56.87% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 27760 0.08% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 9 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 371 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11459171 32.95% 89.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3514969 10.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61175 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19747110 56.73% 56.91% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 27980 0.08% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 388 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11452276 32.90% 89.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3520179 10.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34782251 # Type of FU issued -system.cpu2.iq.rate 0.393716 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1537548 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044205 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108096303 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39840742 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28020326 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6981 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3693 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3127 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36254698 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3724 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 204617 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34809127 # Type of FU issued +system.cpu2.iq.rate 0.393931 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1532656 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044030 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108288948 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39878610 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28070823 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7546 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3965 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3367 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36276582 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4026 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205280 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1527306 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1908 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9375 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562929 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1528845 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1875 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9489 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562920 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5348773 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344308 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5328051 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344229 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1155918 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5077664 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 88593 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32732277 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60627 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6608021 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3899448 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 368370 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29616 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2740 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9375 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107393 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89251 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196644 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33865771 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11188559 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 916480 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1155131 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5244365 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 89322 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32783919 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60352 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6623705 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3904787 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362611 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 30261 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2481 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9489 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 106879 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89021 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 195900 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33894861 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11182187 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 914266 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82963 # number of nop insts executed -system.cpu2.iew.exec_refs 14669578 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3700003 # Number of branches executed -system.cpu2.iew.exec_stores 3481019 # Number of stores executed -system.cpu2.iew.exec_rate 0.383342 # Inst execution rate -system.cpu2.iew.wb_sent 33465265 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28023453 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16087448 # num instructions producing a value -system.cpu2.iew.wb_consumers 29114707 # num instructions consuming a value +system.cpu2.iew.exec_nop 82965 # number of nop insts executed +system.cpu2.iew.exec_refs 14668868 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3706634 # Number of branches executed +system.cpu2.iew.exec_stores 3486681 # Number of stores executed +system.cpu2.iew.exec_rate 0.383584 # Inst execution rate +system.cpu2.iew.wb_sent 33494578 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28074190 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16115456 # num instructions producing a value +system.cpu2.iew.wb_consumers 29164308 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317210 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.552554 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317712 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.552575 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7129352 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356651 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 170839 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35759991 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.708498 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.752281 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7126752 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357204 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 170224 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35906001 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.707499 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.751012 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27025739 75.58% 75.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4219923 11.80% 87.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1248297 3.49% 90.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 635334 1.78% 92.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 557295 1.56% 94.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 319233 0.89% 95.09% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 417712 1.17% 96.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 309905 0.87% 97.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1026553 2.87% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27147368 75.61% 75.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4230684 11.78% 87.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1251387 3.49% 90.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 639812 1.78% 92.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 559957 1.56% 94.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 318640 0.89% 95.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 417979 1.16% 96.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 311730 0.87% 97.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1028444 2.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35759991 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20506693 # Number of instructions committed -system.cpu2.commit.committedOps 25335895 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35906001 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20561870 # Number of instructions committed +system.cpu2.commit.committedOps 25403458 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8417234 # Number of memory references committed -system.cpu2.commit.loads 5080715 # Number of loads committed -system.cpu2.commit.membars 94304 # Number of memory barriers committed -system.cpu2.commit.branches 3173719 # Number of branches committed -system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22548127 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294799 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1026553 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8436727 # Number of memory references committed +system.cpu2.commit.loads 5094860 # Number of loads committed +system.cpu2.commit.membars 94449 # Number of memory barriers committed +system.cpu2.commit.branches 3185060 # Number of branches committed +system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22606405 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295605 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1028444 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66675347 # The number of ROB reads -system.cpu2.rob.rob_writes 66130617 # The number of ROB writes -system.cpu2.timesIdled 360964 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51427456 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3556668435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20451214 # Number of Instructions Simulated -system.cpu2.committedOps 25280416 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20451214 # Number of Instructions Simulated -system.cpu2.cpi 4.319722 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.319722 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.231496 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.231496 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 156902302 # number of integer regfile reads -system.cpu2.int_regfile_writes 29839836 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22382 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20836 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9252861 # number of misc regfile reads -system.cpu2.misc_regfile_writes 241910 # number of misc regfile writes +system.cpu2.rob.rob_reads 66885510 # The number of ROB reads +system.cpu2.rob.rob_writes 66259648 # The number of ROB writes +system.cpu2.timesIdled 359925 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51302262 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3553994827 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20506347 # Number of Instructions Simulated +system.cpu2.committedOps 25347935 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20506347 # Number of Instructions Simulated +system.cpu2.cpi 4.309084 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.309084 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232068 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232068 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157055367 # number of integer regfile reads +system.cpu2.int_regfile_writes 29889640 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22622 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9269321 # number of misc regfile reads +system.cpu2.misc_regfile_writes 242794 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1838,10 +1972,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1279629373750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1279629373750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1346583006000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1346583006000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index b715fd89b..cc97b6f9f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,150 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.548576 # Number of seconds simulated -sim_ticks 2548576209000 # Number of ticks simulated -final_tick 2548576209000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.549325 # Number of seconds simulated +sim_ticks 2549325180000 # Number of ticks simulated +final_tick 2549325180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64501 # Simulator instruction rate (inst/s) -host_op_rate 82996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2725389479 # Simulator tick rate (ticks/s) -host_mem_usage 403492 # Number of bytes of host memory used -host_seconds 935.12 # Real time elapsed on the host -sim_insts 60316464 # Number of instructions simulated -sim_ops 77611603 # Number of ops (including micro ops) simulated +host_inst_rate 61075 # Simulator instruction rate (inst/s) +host_op_rate 78588 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2581455626 # Simulator tick rate (ticks/s) +host_mem_usage 428832 # Number of bytes of host memory used +host_seconds 987.55 # Real time elapsed on the host +sim_insts 60314884 # Number of instructions simulated +sim_ops 77609482 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 483776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5166800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 315264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3924504 # Number of bytes read from this memory -system.physmem.bytes_read::total 131003560 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 483776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 315264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783488 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1522020 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494080 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799588 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 507840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4720464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 291712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4372184 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 507840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 291712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785664 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521520 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494580 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801764 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7559 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 80765 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 61326 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293434 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59117 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380505 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373520 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813142 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47520858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73791 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68321 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293464 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59151 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380380 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373645 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813176 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47506897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 678 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 189822 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2027328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 123702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1539881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51402646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 189822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 123702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313524 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484550 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 597204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586241 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47520858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 199206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1851652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1715036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51388297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 199206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114427 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313633 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586265 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2668064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47506897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 678 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 189822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2624532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 123702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2126122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54070641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293434 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 813142 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15293434 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 813142 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 978779776 # Total number of bytes read from memory -system.physmem.bytesWritten 52041088 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131003560 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799588 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 13 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 955864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955684 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 955879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 955769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955947 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955508 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955111 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956226 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955972 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956075 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955979 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6690 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6478 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6630 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6589 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6842 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6779 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7114 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6901 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6563 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6214 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6772 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7070 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6922 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2548575024500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 42 # Categorize read packet sizes -system.physmem.readPktSize::3 15138816 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154576 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754025 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59117 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1061686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 987876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 978214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2813374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2806969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2769477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 43265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 29260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.bw_total::cpu0.inst 199206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2448485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2301301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54056362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293464 # Number of read requests accepted +system.physmem.writeReqs 813176 # Number of write requests accepted +system.physmem.readBursts 15293464 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813176 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978217536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 564160 # Total number of bytes read from write queue +system.physmem.bytesWritten 6910272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131005480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801764 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8815 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705189 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4711 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955865 # Per bank write bursts +system.physmem.perBankRdBursts::1 955523 # Per bank write bursts +system.physmem.perBankRdBursts::2 954611 # Per bank write bursts +system.physmem.perBankRdBursts::3 954852 # Per bank write bursts +system.physmem.perBankRdBursts::4 955764 # Per bank write bursts +system.physmem.perBankRdBursts::5 955945 # Per bank write bursts +system.physmem.perBankRdBursts::6 954843 # Per bank write bursts +system.physmem.perBankRdBursts::7 954680 # Per bank write bursts +system.physmem.perBankRdBursts::8 956251 # Per bank write bursts +system.physmem.perBankRdBursts::9 955822 # Per bank write bursts +system.physmem.perBankRdBursts::10 954302 # Per bank write bursts +system.physmem.perBankRdBursts::11 954022 # Per bank write bursts +system.physmem.perBankRdBursts::12 956218 # Per bank write bursts +system.physmem.perBankRdBursts::13 955977 # Per bank write bursts +system.physmem.perBankRdBursts::14 955052 # Per bank write bursts +system.physmem.perBankRdBursts::15 954922 # Per bank write bursts +system.physmem.perBankWrBursts::0 6685 # Per bank write bursts +system.physmem.perBankWrBursts::1 6462 # Per bank write bursts +system.physmem.perBankWrBursts::2 6616 # Per bank write bursts +system.physmem.perBankWrBursts::3 6625 # Per bank write bursts +system.physmem.perBankWrBursts::4 6578 # Per bank write bursts +system.physmem.perBankWrBursts::5 6834 # Per bank write bursts +system.physmem.perBankWrBursts::6 6825 # Per bank write bursts +system.physmem.perBankWrBursts::7 6778 # Per bank write bursts +system.physmem.perBankWrBursts::8 7112 # Per bank write bursts +system.physmem.perBankWrBursts::9 6876 # Per bank write bursts +system.physmem.perBankWrBursts::10 6540 # Per bank write bursts +system.physmem.perBankWrBursts::11 6189 # Per bank write bursts +system.physmem.perBankWrBursts::12 7142 # Per bank write bursts +system.physmem.perBankWrBursts::13 6759 # Per bank write bursts +system.physmem.perBankWrBursts::14 7042 # Per bank write bursts +system.physmem.perBankWrBursts::15 6910 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2549324058500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 42 # Read request sizes (log2) +system.physmem.readPktSize::3 15138816 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 154606 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754025 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 59151 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1187642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1126920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1081304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3687011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2647213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2642028 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2655762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 54010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 60825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -157,31 +171,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -189,456 +203,675 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39284 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 25091.701456 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2070.748672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31471.829892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 6644 16.91% 16.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 3436 8.75% 25.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2300 5.85% 31.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 1832 4.66% 36.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1227 3.12% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1105 2.81% 42.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 800 2.04% 44.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 812 2.07% 46.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 554 1.41% 47.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 516 1.31% 48.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 427 1.09% 50.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 432 1.10% 51.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 277 0.71% 51.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 299 0.76% 52.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 172 0.44% 53.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 211 0.54% 53.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 136 0.35% 53.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 132 0.34% 54.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 101 0.26% 54.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 106 0.27% 54.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 70 0.18% 54.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 391 1.00% 55.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 264 0.67% 56.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 450 1.15% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 85 0.22% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 167 0.43% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 56 0.14% 58.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 95 0.24% 58.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 44 0.11% 58.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 79 0.20% 59.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 30 0.08% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 69 0.18% 59.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 18 0.05% 59.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 44 0.11% 59.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 15 0.04% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 32 0.08% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 19 0.05% 59.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 8 0.02% 59.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 26 0.07% 59.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 6 0.02% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 18 0.05% 59.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 15 0.04% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 16 0.04% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 7 0.02% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 13 0.03% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 4 0.01% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 18 0.05% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 6 0.02% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 6 0.02% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 11 0.03% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 6 0.02% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 10 0.03% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 5 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 3 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 1 0.00% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 13 0.03% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 4 0.01% 60.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 32 0.08% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 5 0.01% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 3 0.01% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 6 0.02% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 5 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 4 0.01% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 6 0.02% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 3 0.01% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 4 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 7 0.02% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 8 0.02% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5199 2 0.01% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 2 0.01% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 3 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 3 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 4 0.01% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5583 1 0.00% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 2 0.01% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 2 0.01% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6095 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 3 0.01% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 2 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6351 1 0.00% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 2 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6607 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 20 0.05% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 3 0.01% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7119 2 0.01% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 3 0.01% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 2 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 4 0.01% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 9 0.02% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7631 1 0.00% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 7 0.02% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 3 0.01% 60.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 4 0.01% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 2 0.01% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 11 0.03% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 1 0.00% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 311 0.79% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 63 0.16% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 194 0.49% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 13 0.03% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 3 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20495 1 0.00% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25615 2 0.01% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28367 1 0.00% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32192-32207 1 0.00% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33359 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33679 2 0.01% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 2 0.01% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34575 1 0.00% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37199 1 0.00% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39503 1 0.00% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45071 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58112-58127 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64768-64783 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 14685 37.38% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::68736-68751 1 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 9 0.02% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 43 0.11% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 33 0.08% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39284 # Bytes accessed per row activation -system.physmem.totQLat 294283871250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 386089225000 # Sum of mem lat for all requests -system.physmem.totBusLat 76467105000 # Total cycles spent in databus access -system.physmem.totBankLat 15338248750 # Total cycles spent in bank access -system.physmem.avgQLat 19242.51 # Average queueing delay per request -system.physmem.avgBankLat 1002.93 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25245.45 # Average memory access latency -system.physmem.avgRdBW 384.05 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.40 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 1.08 # Average write queue length over time -system.physmem.readRowHits 15268174 # Number of row buffer hits during reads -system.physmem.writeRowHits 94166 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.58 # Row buffer hit rate for writes -system.physmem.avgGap 158231.96 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55011549 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346066 # Transaction distribution -system.membus.trans_dist::ReadResp 16346069 # Transaction distribution +system.physmem.bytesPerActivate::samples 86834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11344.953359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1015.074534 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16830.192081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23626 27.21% 27.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14089 16.23% 43.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2724 3.14% 46.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2126 2.45% 49.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1310 1.51% 50.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1204 1.39% 51.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 811 0.93% 52.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1018 1.17% 54.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 572 0.66% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 583 0.67% 55.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 533 0.61% 55.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 603 0.69% 56.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 265 0.31% 57.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 147 0.17% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 578 0.67% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 113 0.13% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 129 0.15% 58.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 237 0.27% 58.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 56 0.06% 58.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 502 0.58% 59.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 39 0.04% 59.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 171 0.20% 59.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 11 0.01% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 115 0.13% 59.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 15 0.02% 59.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 109 0.13% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 18 0.02% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 54 0.06% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 24 0.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 490 0.56% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 17 0.02% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 7 0.01% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 154 0.18% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 14 0.02% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 32 0.04% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 7 0.01% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 95 0.11% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 14 0.02% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 9 0.01% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 155 0.18% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 16 0.02% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 10 0.01% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 408 0.47% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 96 0.11% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 10 0.01% 61.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 20 0.02% 61.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.01% 61.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 86 0.10% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 6 0.01% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 21 0.02% 62.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 12 0.01% 62.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 58 0.07% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 407 0.47% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 10 0.01% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 18 0.02% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 3 0.00% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 75 0.09% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 12 0.01% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 7 0.01% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 139 0.16% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 8 0.01% 62.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 72 0.08% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 17 0.02% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 76 0.09% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 9 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 13 0.01% 63.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 144 0.17% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 9 0.01% 63.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 13 0.01% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 12 0.01% 64.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 6 0.01% 64.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 262 0.30% 64.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 5 0.01% 64.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 136 0.16% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 8 0.01% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 21 0.02% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 74 0.09% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 8 0.01% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 452 0.52% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 4 0.00% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 13 0.01% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 23 0.03% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 4 0.00% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 73 0.08% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 3 0.00% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 132 0.15% 65.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 243 0.28% 66.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 128 0.15% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 66 0.08% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 67 0.08% 66.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 450 0.52% 66.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 67 0.08% 66.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 2 0.00% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 1 0.00% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 251 0.29% 67.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 128 0.15% 67.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 66 0.08% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 387 0.45% 68.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 67 0.08% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11719 1 0.00% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 121 0.14% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 66 0.08% 68.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 380 0.44% 68.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 37 0.04% 68.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 69 0.08% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 65 0.07% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 389 0.45% 69.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 129 0.15% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 66 0.08% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 120 0.14% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 443 0.51% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 57 0.07% 70.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 13 0.01% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 119 0.14% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 388 0.45% 71.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 123 0.14% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15751 1 0.00% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 64 0.07% 71.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 66 0.08% 71.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16327 1 0.00% 71.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 526 0.61% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 68 0.08% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 64 0.07% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 122 0.14% 72.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 391 0.45% 72.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 120 0.14% 72.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 15 0.02% 72.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 57 0.07% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 72.89% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 253 0.29% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 68 0.08% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 129 0.15% 78.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 78.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 68 0.08% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 384 0.44% 79.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 66 0.08% 79.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 119 0.14% 79.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 64 0.07% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 380 0.44% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 1 0.00% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 37 0.04% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 72 0.08% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 65 0.07% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 385 0.44% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 129 0.15% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 64 0.07% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 119 0.14% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 443 0.51% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 56 0.06% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 13 0.01% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 119 0.14% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 389 0.45% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31808-31815 1 0.00% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 124 0.14% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 66 0.08% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 66 0.08% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 65 0.07% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 125 0.14% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 390 0.45% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 119 0.14% 84.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 13 0.01% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 56 0.06% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 441 0.51% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 119 0.14% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 64 0.07% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 129 0.15% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 385 0.44% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 64 0.07% 85.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 72 0.08% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36416-36423 1 0.00% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 37 0.04% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 380 0.44% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 64 0.07% 86.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 119 0.14% 86.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 66 0.08% 86.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 384 0.44% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 67 0.08% 87.02% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 129 0.15% 88.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 137 0.16% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 129 0.15% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 67 0.08% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 449 0.52% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 67 0.08% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 132 0.15% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 251 0.29% 90.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 67 0.08% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43392-43399 2 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 128 0.15% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 67 0.08% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 384 0.44% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 68 0.08% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44480-44487 1 0.00% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 119 0.14% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44736-44743 1 0.00% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 66 0.08% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 383 0.44% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 41 0.05% 91.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 70 0.08% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 65 0.07% 91.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 385 0.44% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 129 0.15% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 64 0.07% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 119 0.14% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 440 0.51% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 1 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 58 0.07% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 14 0.02% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 120 0.14% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 388 0.45% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 122 0.14% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 64 0.07% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 65 0.07% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5147 5.93% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49472-49479 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50816-50823 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86834 # Bytes accessed per row activation +system.physmem.totQLat 369633946000 # Total ticks spent queuing +system.physmem.totMemAccLat 463601929750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76423245000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17544738750 # Total ticks spent accessing banks +system.physmem.avgQLat 24183.35 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1147.87 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30331.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.02 # Data bus utilization in percentage +system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing +system.physmem.readRowHits 15212610 # Number of row buffer hits during reads +system.physmem.writeRowHits 93178 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.29 # Row buffer hit rate for writes +system.physmem.avgGap 158277.83 # Average gap between requests +system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.88 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54996997 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346113 # Transaction distribution +system.membus.trans_dist::ReadResp 16346116 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59117 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4675 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4677 # Transaction distribution -system.membus.trans_dist::ReadExReq 131414 # Transaction distribution -system.membus.trans_dist::ReadExResp 131414 # Transaction distribution +system.membus.trans_dist::Writeback 59151 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4708 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4711 # Transaction distribution +system.membus.trans_dist::ReadExReq 131399 # Transaction distribution +system.membus.trans_dist::ReadExResp 131399 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382956 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382960 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885757 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272507 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885919 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272673 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550139 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390329 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550305 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390337 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692620 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19090597 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696716 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19094701 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140201125 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140201125 # Total data (bytes) +system.membus.tot_pkt_size::total 140205229 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140205229 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475672000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487741000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3601000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17572541000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17567405000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4757385335 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4737923280 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34173123993 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34188515482 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 64349 # number of replacements -system.l2c.tags.tagsinuse 51432.213982 # Cycle average of tags in use -system.l2c.tags.total_refs 1904557 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129741 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.679685 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2511462555500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36971.376669 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.336615 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000368 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4863.234399 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3340.353025 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.819885 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3340.869034 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2888.223986 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564138 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000295 # Average percentage of cache occupancy +system.l2c.tags.replacements 64379 # number of replacements +system.l2c.tags.tagsinuse 51427.622498 # Cycle average of tags in use +system.l2c.tags.total_refs 1904241 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129768 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.674195 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2512188924000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36951.825179 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.926736 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4986.850446 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3336.949611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.947160 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3226.583152 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2894.539843 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563840 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000289 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050970 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.050978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044071 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784793 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 31056 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 489944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 180708 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 32283 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 480968 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 206794 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435577 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608201 # number of Writeback hits -system.l2c.Writeback_hits::total 608201 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 22 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.076093 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050918 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.049234 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044167 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784723 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32603 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 505956 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 182118 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30730 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464492 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 205502 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435201 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608382 # number of Writeback hits +system.l2c.Writeback_hits::total 608382 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 22 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56719 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56246 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112965 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 31056 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 489944 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 237427 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 32283 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7013 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 480968 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 263040 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548542 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 31056 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6811 # number of overall hits -system.l2c.overall_hits::cpu0.inst 489944 # number of overall hits -system.l2c.overall_hits::cpu0.data 237427 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 32283 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7013 # number of overall hits -system.l2c.overall_hits::cpu1.inst 480968 # number of overall hits -system.l2c.overall_hits::cpu1.data 263040 # number of overall hits -system.l2c.overall_hits::total 1548542 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 15 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58173 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54780 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112953 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32603 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7139 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 505956 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 240291 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30730 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6661 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 464492 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260282 # number of demand (read+write) hits +system.l2c.demand_hits::total 1548154 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32603 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7139 # number of overall hits +system.l2c.overall_hits::cpu0.inst 505956 # number of overall hits +system.l2c.overall_hits::cpu0.data 240291 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30730 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6661 # number of overall hits +system.l2c.overall_hits::cpu1.inst 464492 # number of overall hits +system.l2c.overall_hits::cpu1.data 260282 # number of overall hits +system.l2c.overall_hits::total 1548154 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7450 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6327 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4932 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4374 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1313 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1598 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu0.inst 7825 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6187 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4565 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4551 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23171 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1285 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1631 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2916 # 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number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6023999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93382533238 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90909138000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184297695237 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033619 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020586 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015800 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986476 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986420 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.986445 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.570099 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.255522 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.191498 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091636 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 59880.367207 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62924.545204 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61076.105220 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6012999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93527432009 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90776841250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184310286258 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021547 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015834 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.983168 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989084 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986468 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.166667 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091688 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.236922 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.210114 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091688 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61701.627339 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65461.720946 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61973.540577 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.816020 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.545861 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.065604 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.714678 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57104.629002 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 54811.358977 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56106.547358 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61956.189415 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63673.743808 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62790.742558 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -829,49 +1066,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58475740 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676749 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676751 # Transaction distribution +system.toL2Bus.throughput 58456334 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2676393 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2676395 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608201 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2951 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246143 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246143 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608382 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2974 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246144 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246144 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967991 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797697 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37845 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149237 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952770 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62938176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85577189 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253516 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148824185 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148824185 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 205696 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4963674463 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798220 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37803 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149157 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7952295 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62908992 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85598765 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148816461 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148816461 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 207744 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4964319701 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4434137240 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4431802148 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4494378467 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4486267320 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24064152 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24046904 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86310594 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86228845 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48458766 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322134 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322134 # Transaction distribution +system.iobus.throughput 48444532 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322136 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322136 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution system.iobus.trans_dist::WriteResp 8160 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -893,12 +1130,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382960 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660588 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660592 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -920,14 +1157,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390329 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390337 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500857 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500857 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500865 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500865 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -973,684 +1210,684 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374796000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41501700007 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41492591518 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7055231 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5603867 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 360036 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4627391 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3766189 # Number of BTB hits +system.cpu0.branchPred.lookups 7178846 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5689563 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 376334 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4735029 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3823898 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.389038 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 696378 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 37374 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 80.757647 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 708733 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25604020 # DTB read hits -system.cpu0.dtb.read_misses 37101 # DTB read misses -system.cpu0.dtb.write_hits 6019786 # DTB write hits -system.cpu0.dtb.write_misses 10089 # DTB write misses +system.cpu0.dtb.read_hits 25686724 # DTB read hits +system.cpu0.dtb.read_misses 37672 # DTB read misses +system.cpu0.dtb.write_hits 5882199 # DTB write hits +system.cpu0.dtb.write_misses 9157 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5563 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1360 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5402 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1359 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 227 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 609 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25641121 # DTB read accesses -system.cpu0.dtb.write_accesses 6029875 # DTB write accesses +system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25724396 # DTB read accesses +system.cpu0.dtb.write_accesses 5891356 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31623806 # DTB hits -system.cpu0.dtb.misses 47190 # DTB misses -system.cpu0.dtb.accesses 31670996 # DTB accesses -system.cpu0.itb.inst_hits 5711817 # ITB inst hits -system.cpu0.itb.inst_misses 6786 # ITB inst misses +system.cpu0.dtb.hits 31568923 # DTB hits +system.cpu0.dtb.misses 46829 # DTB misses +system.cpu0.dtb.accesses 31615752 # DTB accesses +system.cpu0.itb.inst_hits 5794960 # ITB inst hits +system.cpu0.itb.inst_misses 6979 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2537 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1280 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5718603 # ITB inst accesses -system.cpu0.itb.hits 5711817 # DTB hits -system.cpu0.itb.misses 6786 # DTB misses -system.cpu0.itb.accesses 5718603 # DTB accesses -system.cpu0.numCycles 240384739 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5801939 # ITB inst accesses +system.cpu0.itb.hits 5794960 # DTB hits +system.cpu0.itb.misses 6979 # DTB misses +system.cpu0.itb.accesses 5801939 # DTB accesses +system.cpu0.numCycles 241329954 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15036708 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 44324460 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7055231 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4462567 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 9979880 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2348952 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 79920 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48371030 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1557 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 40136 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1395788 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 332 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5710035 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 358939 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3057 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 76524952 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.728839 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.080650 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15402359 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 44612176 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7178846 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4532631 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10046821 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2409329 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 81802 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 48777724 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1779 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1966 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 42894 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1416575 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 470 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5793020 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 368373 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3163 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77432013 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.722773 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.070911 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 66552751 86.97% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 648002 0.85% 87.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 843291 1.10% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1146450 1.50% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1051496 1.37% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 533927 0.70% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1248962 1.63% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 369566 0.48% 94.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4130507 5.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67393349 87.04% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 663167 0.86% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 850708 1.10% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1161944 1.50% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1070979 1.38% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 538004 0.69% 92.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1258402 1.63% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 372673 0.48% 94.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4122787 5.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76524952 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.029350 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.184390 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15988793 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49427885 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9067900 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 506950 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1531254 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 959604 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 89006 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53104636 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 296594 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1531254 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16866391 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20063365 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 26274348 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8616750 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3170765 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50610961 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7411 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 529520 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2115247 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 208 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 52034450 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 231667374 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 214169305 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4937 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 38251156 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13783293 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411980 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 362796 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6588533 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9723453 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6830710 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1010499 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1245426 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 47056287 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 968125 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61041577 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 84130 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9522170 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23883479 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 244384 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76524952 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.797669 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.517362 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77432013 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.029747 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.184860 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16324291 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49901037 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9152885 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 482910 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1568783 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 985989 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 93507 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53239353 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 312067 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1568783 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17193647 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20516369 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 26371209 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8691714 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3088262 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50703360 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7236 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 484563 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2089605 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 237 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 52223867 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 231534090 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 214067803 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5431 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 38086867 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14136999 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 416413 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 366902 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6391113 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9801074 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6698586 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1023553 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1394670 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47085778 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 981191 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 61028996 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87181 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9766291 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24255892 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256976 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77432013 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.788162 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.509612 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54759555 71.56% 71.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6733047 8.80% 80.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3420180 4.47% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2920085 3.82% 88.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6164290 8.06% 96.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1467950 1.92% 98.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 772657 1.01% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 222441 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 64747 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55649099 71.87% 71.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6737778 8.70% 80.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3435441 4.44% 85.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2925983 3.78% 88.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6185685 7.99% 96.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1437832 1.86% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 773159 1.00% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 224755 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 62281 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76524952 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77432013 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27542 0.62% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4220431 94.60% 95.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 213140 4.78% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29912 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4221653 94.70% 95.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 206360 4.63% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 171568 0.28% 0.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 28242983 46.27% 46.55% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47431 0.08% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1218 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26256845 43.01% 89.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6321515 10.36% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 165947 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 28282024 46.34% 46.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46844 0.08% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1271 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26348641 43.17% 89.87% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6184237 10.13% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61041577 # Type of FU issued -system.cpu0.iq.rate 0.253933 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4461113 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.073083 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 203189112 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57554843 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 42164489 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11244 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5997 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4944 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 65325122 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6000 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306679 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 61028996 # Type of FU issued +system.cpu0.iq.rate 0.252886 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4457926 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.073046 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 204069737 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57841875 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 42095336 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12029 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6474 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5396 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 65314591 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6384 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 305188 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2052481 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3874 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 14810 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 826086 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2103037 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3902 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15671 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 837358 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17207144 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348104 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17232684 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348213 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1531254 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15306015 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 241273 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 48127004 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 101529 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9723453 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6830710 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 683062 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 53931 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 11240 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 14810 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 174193 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 137584 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 311777 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 60001377 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 25939220 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1040200 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1568783 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15829049 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 237688 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 48167223 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105126 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9801074 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6698586 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 691561 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54422 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4242 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15671 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 182031 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 143561 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 325592 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 59970791 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26024613 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1058205 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 102592 # number of nop insts executed -system.cpu0.iew.exec_refs 32204815 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5606114 # Number of branches executed -system.cpu0.iew.exec_stores 6265595 # Number of stores executed -system.cpu0.iew.exec_rate 0.249606 # Inst execution rate -system.cpu0.iew.wb_sent 59520960 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 42169433 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22855569 # num instructions producing a value -system.cpu0.iew.wb_consumers 42162980 # num instructions consuming a value +system.cpu0.iew.exec_nop 100254 # number of nop insts executed +system.cpu0.iew.exec_refs 32151728 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5674244 # Number of branches executed +system.cpu0.iew.exec_stores 6127115 # Number of stores executed +system.cpu0.iew.exec_rate 0.248501 # Inst execution rate +system.cpu0.iew.wb_sent 59482820 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 42100732 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22797313 # num instructions producing a value +system.cpu0.iew.wb_consumers 41683102 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.175425 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.542077 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.174453 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.546920 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9402485 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 723741 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 272429 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 74993698 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.510414 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.487877 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9635326 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 724215 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 284304 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75863230 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.501725 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.477269 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61390308 81.86% 81.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6607868 8.81% 90.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1921399 2.56% 93.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1064491 1.42% 94.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 990154 1.32% 95.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 565334 0.75% 96.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 721378 0.96% 97.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 343964 0.46% 98.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1388802 1.85% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 62300247 82.12% 82.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6632163 8.74% 90.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1905948 2.51% 93.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1063803 1.40% 94.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 963459 1.27% 96.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 539688 0.71% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 720050 0.95% 97.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 348558 0.46% 98.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1389314 1.83% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 74993698 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29384265 # Number of instructions committed -system.cpu0.commit.committedOps 38277857 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75863230 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29321704 # Number of instructions committed +system.cpu0.commit.committedOps 38062462 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13675596 # Number of memory references committed -system.cpu0.commit.loads 7670972 # Number of loads committed -system.cpu0.commit.membars 201047 # Number of memory barriers committed -system.cpu0.commit.branches 4859392 # Number of branches committed -system.cpu0.commit.fp_insts 4891 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 33962414 # Number of committed integer instructions. -system.cpu0.commit.function_calls 491145 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1388802 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13559265 # Number of memory references committed +system.cpu0.commit.loads 7698037 # Number of loads committed +system.cpu0.commit.membars 204059 # Number of memory barriers committed +system.cpu0.commit.branches 4889328 # Number of branches committed +system.cpu0.commit.fp_insts 5354 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 33742241 # Number of committed integer instructions. +system.cpu0.commit.function_calls 497179 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1389314 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 120378043 # The number of ROB reads -system.cpu0.rob.rob_writes 96934970 # The number of ROB writes -system.cpu0.timesIdled 903993 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 163859787 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2252055071 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29315772 # Number of Instructions Simulated -system.cpu0.committedOps 38209364 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29315772 # Number of Instructions Simulated -system.cpu0.cpi 8.199843 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.199843 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.121954 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.121954 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 271685631 # number of integer regfile reads -system.cpu0.int_regfile_writes 42795201 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22306 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19768 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15093810 # number of misc regfile reads -system.cpu0.misc_regfile_writes 401151 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983925 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.538497 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10508756 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984437 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.674889 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6941856250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 321.486243 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 190.052254 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.627903 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.371196 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999099 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5171009 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5337747 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10508756 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5171009 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5337747 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10508756 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5171009 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5337747 # number of overall hits -system.cpu0.icache.overall_hits::total 10508756 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 538904 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 526390 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065294 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 538904 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 526390 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065294 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 538904 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 526390 # number of overall misses -system.cpu0.icache.overall_misses::total 1065294 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7446919215 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7105468986 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14552388201 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7446919215 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7105468986 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14552388201 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7446919215 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7105468986 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14552388201 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5709913 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5864137 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11574050 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5709913 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5864137 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11574050 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5709913 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5864137 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11574050 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094380 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089764 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092042 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094380 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089764 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092042 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094380 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089764 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092042 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13818.637856 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13498.487787 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13660.443221 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13818.637856 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13498.487787 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13660.443221 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13818.637856 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13498.487787 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13660.443221 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6869 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1025 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 398 # number of cycles access was blocked +system.cpu0.rob.rob_reads 121250209 # The number of ROB reads +system.cpu0.rob.rob_writes 97007351 # The number of ROB writes +system.cpu0.timesIdled 906901 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 163897941 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2251401803 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 29254206 # Number of Instructions Simulated +system.cpu0.committedOps 37994964 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 29254206 # Number of Instructions Simulated +system.cpu0.cpi 8.249410 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.249410 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.121221 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.121221 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 271506841 # number of integer regfile reads +system.cpu0.int_regfile_writes 42814380 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22646 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19918 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15055897 # number of misc regfile reads +system.cpu0.misc_regfile_writes 404161 # number of misc regfile writes +system.cpu0.icache.tags.replacements 983492 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.574238 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10516196 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 984004 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.687148 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6986136250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 318.901478 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 192.672760 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.622854 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.376314 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999168 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5235281 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5280915 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10516196 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5235281 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5280915 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10516196 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5235281 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5280915 # number of overall hits +system.cpu0.icache.overall_hits::total 10516196 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 557620 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 507749 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065369 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 557620 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 507749 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065369 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 557620 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 507749 # number of overall misses +system.cpu0.icache.overall_misses::total 1065369 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7715888650 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6834076460 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14549965110 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7715888650 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6834076460 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14549965110 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7715888650 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6834076460 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14549965110 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5792901 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5788664 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11581565 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5792901 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5788664 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11581565 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5792901 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5788664 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11581565 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.096259 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087714 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.091988 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.096259 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087714 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.091988 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096259 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087714 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.091988 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13837.180607 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13459.556710 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.207137 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13657.207137 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13657.207137 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6518 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 829 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 410 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.258794 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 1025 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.897561 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 829 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40970 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39858 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80828 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 40970 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39858 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80828 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 40970 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39858 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80828 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 497934 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 486532 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984466 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 497934 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 486532 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984466 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 497934 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 486532 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984466 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6047465345 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5786819388 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11834284733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6047465345 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5786819388 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11834284733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6047465345 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5786819388 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11834284733 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8439000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8439000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8439000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8439000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085058 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087205 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5567069659 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11826064063 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6258994404 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5567069659 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11826064063 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6258994404 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5567069659 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11826064063 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8426500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8426500 # 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mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.084967 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.795980 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643834 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993352 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21533253 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644346 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.418773 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 42568250 # 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number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 626 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1537855 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1538038 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3075893 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1537855 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1538038 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3075893 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181645 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 204625 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386270 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127901 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 121091 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248992 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6713 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5483 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12196 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 12 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 18 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309546 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 325716 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635262 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309546 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 325716 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635262 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2539210775 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2715181297 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5254392072 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5938244941 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5721716845 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11659961786 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84451251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63563504 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148014755 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 156998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 235497 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8477455716 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8436898142 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16914353858 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8477455716 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 8436898142 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16914353858 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92366768250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 89963955251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330723501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13704367995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13062365000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26766732995 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105913252575 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103169567324 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209082819899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025398 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027718 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025297 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023351 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054662 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040875 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047357 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000061 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025662 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025662 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14012.307711 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13132.732332 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13543.853343 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45601.040815 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40630.023477 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43289.619476 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12437.272741 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11673.862745 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12088.132785 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13499.800000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106071136245 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103026320251 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209097456496 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025358 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027786 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024970 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023736 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055086 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040661 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047508 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000051 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000092 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13978.974235 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13269.059484 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.899713 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46428.448104 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47251.379913 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46828.660302 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12580.254879 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11592.833121 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12136.336094 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1665,324 +1902,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7417918 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5931932 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 364646 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4881678 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3917644 # Number of BTB hits +system.cpu1.branchPred.lookups 7299586 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5849815 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 347289 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4589899 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3862662 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 80.251995 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 703527 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35801 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.155708 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 691728 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34987 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25617777 # DTB read hits -system.cpu1.dtb.read_misses 38543 # DTB read misses -system.cpu1.dtb.write_hits 5691491 # DTB write hits -system.cpu1.dtb.write_misses 8859 # DTB write misses +system.cpu1.dtb.read_hits 25535708 # DTB read hits +system.cpu1.dtb.read_misses 37819 # DTB read misses +system.cpu1.dtb.write_hits 5832824 # DTB write hits +system.cpu1.dtb.write_misses 9748 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5585 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2011 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2100 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 659 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25656320 # DTB read accesses -system.cpu1.dtb.write_accesses 5700350 # DTB write accesses +system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25573527 # DTB read accesses +system.cpu1.dtb.write_accesses 5842572 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31309268 # DTB hits -system.cpu1.dtb.misses 47402 # DTB misses -system.cpu1.dtb.accesses 31356670 # DTB accesses -system.cpu1.itb.inst_hits 5866342 # ITB inst hits -system.cpu1.itb.inst_misses 7403 # ITB inst misses +system.cpu1.dtb.hits 31368532 # DTB hits +system.cpu1.dtb.misses 47567 # DTB misses +system.cpu1.dtb.accesses 31416099 # DTB accesses +system.cpu1.itb.inst_hits 5790816 # ITB inst hits +system.cpu1.itb.inst_misses 7158 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2684 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1687 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1580 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5873745 # ITB inst accesses -system.cpu1.itb.hits 5866342 # DTB hits -system.cpu1.itb.misses 7403 # DTB misses -system.cpu1.itb.accesses 5873745 # DTB accesses -system.cpu1.numCycles 234836749 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5797974 # ITB inst accesses +system.cpu1.itb.hits 5790816 # DTB hits +system.cpu1.itb.misses 7158 # DTB misses +system.cpu1.itb.accesses 5797974 # DTB accesses +system.cpu1.numCycles 235384601 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14958684 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46343438 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7417918 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4621171 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10240931 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2382000 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 84846 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47705916 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1885 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 51796 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1300956 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.icacheStallCycles 14589178 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46084175 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7299586 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4554390 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10179964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2322435 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 82610 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48394674 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1151 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1760 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 51069 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1300436 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5864138 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 361139 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3128 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 75991069 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.753206 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.110012 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 5788667 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 351586 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2955 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76205210 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.749083 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.107109 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 65758157 86.53% 86.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 661623 0.87% 87.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 874095 1.15% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1155735 1.52% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1058337 1.39% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 579833 0.76% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1309635 1.72% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 379645 0.50% 94.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4214009 5.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66032287 86.65% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 647062 0.85% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 866139 1.14% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1142625 1.50% 90.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1039142 1.36% 91.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 573208 0.75% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1303078 1.71% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 377648 0.50% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4224021 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 75991069 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031588 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.197343 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15934805 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 48666188 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9324612 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 504366 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1558997 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1010894 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 88249 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54549781 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 295589 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1558997 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16808618 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19027959 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 26571393 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8885070 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3136997 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 52018175 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13230 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 586421 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2033878 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 525 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 54353089 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 236755846 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 219276243 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5446 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 40151278 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14201811 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 419760 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 374760 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6443032 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10070258 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6501681 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 951169 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1220754 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 48367033 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1016747 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62006899 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 95474 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9693963 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24244292 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 257471 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 75991069 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.815976 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521890 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76205210 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.031011 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.195782 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15588837 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49317422 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9252055 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 521656 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1523167 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 986244 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 83403 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54452083 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 278013 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1523167 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16469267 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19674049 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 26510190 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8818021 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3208448 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51956781 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13421 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 604219 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2079670 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 451 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 54191440 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237039699 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 219510796 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 4998 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 40313487 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13877953 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 415796 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 370913 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6599828 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9995387 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6641278 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 924791 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1180275 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 48354458 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1004264 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62036555 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93414 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9463744 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23885542 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 245582 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76205210 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.814072 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.522064 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53638566 70.59% 70.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7003056 9.22% 79.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3617950 4.76% 84.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3068918 4.04% 88.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6184871 8.14% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1401826 1.84% 98.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 782382 1.03% 99.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 229717 0.30% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 63783 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53886192 70.71% 70.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6968313 9.14% 79.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3603419 4.73% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3067011 4.02% 88.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6180907 8.11% 96.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1416351 1.86% 98.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 790440 1.04% 99.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 228268 0.30% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 64309 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 75991069 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76205210 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 31911 0.73% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 5 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4158175 94.76% 95.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 198234 4.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29954 0.68% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 6 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4154847 94.70% 95.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 202692 4.62% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 192098 0.31% 0.31% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 29460264 47.51% 47.82% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45939 0.07% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 896 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26296905 42.41% 90.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6010767 9.69% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 197719 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 29431617 47.44% 47.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46723 0.08% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 843 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26206761 42.24% 90.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6152865 9.92% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62006899 # Type of FU issued -system.cpu1.iq.rate 0.264043 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4388325 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.070772 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 204523942 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59086561 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 43409940 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11938 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6483 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5383 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 66196788 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6338 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 319760 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62036555 # Type of FU issued +system.cpu1.iq.rate 0.263554 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4387499 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.070724 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 204795562 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58831312 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 43493604 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11047 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6062 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4926 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 66220464 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5871 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 319800 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2083716 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3064 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15874 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 772589 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2036379 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2915 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15518 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 769053 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16902604 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 332952 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16877667 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 333288 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1558997 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14375191 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 227377 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 49504406 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10070258 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6501681 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 727587 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 51733 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 9370 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15874 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 179251 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 141654 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 320905 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 60955471 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25970384 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1051428 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1523167 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14985510 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 225691 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 49480647 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96107 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9995387 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6641278 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 719443 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50947 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6143 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15518 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 171517 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 135143 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 306660 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 61000330 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25886068 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1036225 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 120626 # number of nop insts executed -system.cpu1.iew.exec_refs 31928214 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5888736 # Number of branches executed -system.cpu1.iew.exec_stores 5957830 # Number of stores executed -system.cpu1.iew.exec_rate 0.259565 # Inst execution rate -system.cpu1.iew.wb_sent 60476945 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 43415323 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24094324 # num instructions producing a value -system.cpu1.iew.wb_consumers 44023151 # num instructions consuming a value +system.cpu1.iew.exec_nop 121925 # number of nop insts executed +system.cpu1.iew.exec_refs 31986182 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5823905 # Number of branches executed +system.cpu1.iew.exec_stores 6100114 # Number of stores executed +system.cpu1.iew.exec_rate 0.259152 # Inst execution rate +system.cpu1.iew.wb_sent 60530443 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 43498530 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24164344 # num instructions producing a value +system.cpu1.iew.wb_consumers 44485345 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.184874 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.547310 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.184798 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.543198 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9567264 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 759276 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 277731 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74432072 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.530472 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.515537 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9351616 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 758682 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 265186 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74682043 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.531552 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.520144 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60336914 81.06% 81.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6930423 9.31% 90.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1972494 2.65% 93.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1094851 1.47% 94.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1021489 1.37% 95.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 524731 0.70% 96.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 707921 0.95% 97.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 378966 0.51% 98.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1464283 1.97% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60574973 81.11% 81.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6925092 9.27% 90.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1956264 2.62% 93.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1088628 1.46% 94.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1022152 1.37% 95.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 532797 0.71% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 718663 0.96% 97.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 378466 0.51% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1485008 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74432072 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31082580 # Number of instructions committed -system.cpu1.commit.committedOps 39484127 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74682043 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31143561 # Number of instructions committed +system.cpu1.commit.committedOps 39697401 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13715634 # Number of memory references committed -system.cpu1.commit.loads 7986542 # Number of loads committed -system.cpu1.commit.membars 202747 # Number of memory barriers committed -system.cpu1.commit.branches 5103464 # Number of branches committed -system.cpu1.commit.fp_insts 5321 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34903456 # Number of committed integer instructions. -system.cpu1.commit.function_calls 500366 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1464283 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13831233 # Number of memory references committed +system.cpu1.commit.loads 7959008 # Number of loads committed +system.cpu1.commit.membars 199700 # Number of memory barriers committed +system.cpu1.commit.branches 5073252 # Number of branches committed +system.cpu1.commit.fp_insts 4858 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 35121772 # Number of committed integer instructions. +system.cpu1.commit.function_calls 494294 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1485008 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 121076761 # The number of ROB reads -system.cpu1.rob.rob_writes 99705340 # The number of ROB writes -system.cpu1.timesIdled 873554 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 158845680 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2319747272 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31000692 # Number of Instructions Simulated -system.cpu1.committedOps 39402239 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 31000692 # Number of Instructions Simulated -system.cpu1.cpi 7.575210 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.575210 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.132010 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.132010 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 276194442 # number of integer regfile reads -system.cpu1.int_regfile_writes 44861664 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22699 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19852 # number of floating regfile writes -system.cpu1.misc_regfile_reads 15196533 # number of misc regfile reads -system.cpu1.misc_regfile_writes 431717 # number of misc regfile writes +system.cpu1.rob.rob_reads 121317994 # The number of ROB reads +system.cpu1.rob.rob_writes 99664484 # The number of ROB writes +system.cpu1.timesIdled 865516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159179391 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2318646728 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31060678 # Number of Instructions Simulated +system.cpu1.committedOps 39614518 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 31060678 # Number of Instructions Simulated +system.cpu1.cpi 7.578218 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.578218 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.131957 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.131957 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 276434717 # number of integer regfile reads +system.cpu1.int_regfile_writes 44854574 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22375 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19728 # number of floating regfile writes +system.cpu1.misc_regfile_reads 15285924 # number of misc regfile reads +system.cpu1.misc_regfile_writes 428613 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1997,17 +2234,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1441896554007 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1441896554007 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1518441783518 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1518441783518 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83067 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 820046126..87a0dc109 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,143 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.630640 # Number of seconds simulated -sim_ticks 2630640106500 # Number of ticks simulated -final_tick 2630640106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.631415 # Number of seconds simulated +sim_ticks 2631415171500 # Number of ticks simulated +final_tick 2631415171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 544255 # Simulator instruction rate (inst/s) -host_op_rate 692557 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23778611565 # Simulator tick rate (ticks/s) -host_mem_usage 394548 # Number of bytes of host memory used -host_seconds 110.63 # Real time elapsed on the host -sim_insts 60211209 # Number of instructions simulated -sim_ops 76617916 # Number of ops (including micro ops) simulated +host_inst_rate 471038 # Simulator instruction rate (inst/s) +host_op_rate 599389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20585916294 # Simulator tick rate (ticks/s) +host_mem_usage 424736 # Number of bytes of host memory used +host_seconds 127.83 # Real time elapsed on the host +sim_insts 60210883 # Number of instructions simulated +sim_ops 76617506 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 310496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4767440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 278752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4724944 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 393856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4293936 # Number of bytes read from this memory -system.physmem.bytes_read::total 134022176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 310496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 393856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1534960 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1481192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706776 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 425732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4336188 # Number of bytes read from this memory +system.physmem.bytes_read::total 134022064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 278752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 425732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704484 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3690496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1530592 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1485560 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706648 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11054 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73861 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6154 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 67119 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 383740 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 370298 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811704 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47234229 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 67782 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690904 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 382648 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 371390 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811702 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47220316 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 118031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1812274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 105932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1795590 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 149719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1632278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50946603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 118031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 149719 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1402938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 583493 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 563054 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2549484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1402938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47234229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 161788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1647854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50931554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 105932 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 161788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1402476 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 581661 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 564548 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2548685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1402476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47220316 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 118031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2395767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 105932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2377252 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 149719 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2195332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53496087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690887 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 811704 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15690887 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 811704 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 1004216768 # Total number of bytes read from memory -system.physmem.bytesWritten 51949056 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 134022176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6706776 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4522 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 980391 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 980205 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 980224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 980428 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 986950 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 980709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 980611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 980420 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 980615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 980431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 979815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 979555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 980154 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 980076 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 980165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 980109 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6740 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6615 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6627 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6678 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7054 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6898 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7014 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6836 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6411 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6640 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6624 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2630635687000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6680 # Categorize read packet sizes -system.physmem.readPktSize::3 15532032 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152175 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754038 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57666 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1132703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 975077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1005041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3836885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2878586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2878042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2847020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 44009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 29620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 761 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 748 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 10 # What read queue length does an incoming req see +system.physmem.bw_total::cpu1.inst 161788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2212402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53480239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690904 # Number of read requests accepted +system.physmem.writeReqs 811702 # Number of write requests accepted +system.physmem.readBursts 15690904 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811702 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004216000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue +system.physmem.bytesWritten 6838848 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134022064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 704845 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 980392 # Per bank write bursts +system.physmem.perBankRdBursts::1 980205 # Per bank write bursts +system.physmem.perBankRdBursts::2 980222 # Per bank write bursts +system.physmem.perBankRdBursts::3 980428 # Per bank write bursts +system.physmem.perBankRdBursts::4 986950 # Per bank write bursts +system.physmem.perBankRdBursts::5 980709 # Per bank write bursts +system.physmem.perBankRdBursts::6 980611 # Per bank write bursts +system.physmem.perBankRdBursts::7 980420 # Per bank write bursts +system.physmem.perBankRdBursts::8 980615 # Per bank write bursts +system.physmem.perBankRdBursts::9 980431 # Per bank write bursts +system.physmem.perBankRdBursts::10 979815 # Per bank write bursts +system.physmem.perBankRdBursts::11 979555 # Per bank write bursts +system.physmem.perBankRdBursts::12 980153 # Per bank write bursts +system.physmem.perBankRdBursts::13 980095 # Per bank write bursts +system.physmem.perBankRdBursts::14 980165 # Per bank write bursts +system.physmem.perBankRdBursts::15 980109 # Per bank write bursts +system.physmem.perBankWrBursts::0 6734 # Per bank write bursts +system.physmem.perBankWrBursts::1 6600 # Per bank write bursts +system.physmem.perBankWrBursts::2 6608 # Per bank write bursts +system.physmem.perBankWrBursts::3 6671 # Per bank write bursts +system.physmem.perBankWrBursts::4 6747 # Per bank write bursts +system.physmem.perBankWrBursts::5 7057 # Per bank write bursts +system.physmem.perBankWrBursts::6 7034 # Per bank write bursts +system.physmem.perBankWrBursts::7 6884 # Per bank write bursts +system.physmem.perBankWrBursts::8 7000 # Per bank write bursts +system.physmem.perBankWrBursts::9 6825 # Per bank write bursts +system.physmem.perBankWrBursts::10 6323 # Per bank write bursts +system.physmem.perBankWrBursts::11 6129 # Per bank write bursts +system.physmem.perBankWrBursts::12 6612 # Per bank write bursts +system.physmem.perBankWrBursts::13 6395 # Per bank write bursts +system.physmem.perBankWrBursts::14 6622 # Per bank write bursts +system.physmem.perBankWrBursts::15 6616 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2631410752000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 6700 # Read request sizes (log2) +system.physmem.readPktSize::3 15532032 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 152172 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754038 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 57664 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1280991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1124435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1124568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3790382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2700913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2699740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2717442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 51875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -153,29 +155,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -185,193 +187,315 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37970 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 26627.977877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2487.931344 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31806.056461 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5445 14.34% 14.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3318 8.74% 23.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2184 5.75% 28.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1677 4.42% 33.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1130 2.98% 36.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1067 2.81% 39.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 805 2.12% 41.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 712 1.88% 43.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 588 1.55% 44.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 469 1.24% 45.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 450 1.19% 47.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 409 1.08% 48.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 266 0.70% 48.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 255 0.67% 49.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 222 0.58% 50.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 208 0.55% 50.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 140 0.37% 50.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 130 0.34% 51.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 95 0.25% 51.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 109 0.29% 51.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 83 0.22% 52.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 158 0.42% 52.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 757 1.99% 54.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 208 0.55% 55.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 141 0.37% 55.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 116 0.31% 55.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 79 0.21% 55.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 86 0.23% 56.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 52 0.14% 56.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 50 0.13% 56.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 43 0.11% 56.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 55 0.14% 56.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 50 0.13% 56.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 19 0.05% 56.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 19 0.05% 56.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 17 0.04% 56.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 20 0.05% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 17 0.04% 57.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 12 0.03% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 10 0.03% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 7 0.02% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 4 0.01% 57.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 9 0.02% 57.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 14 0.04% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 6 0.02% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 9 0.02% 57.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 11 0.03% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 5 0.01% 57.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 7 0.02% 57.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 8 0.02% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 10 0.03% 57.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 14 0.04% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 5 0.01% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 7 0.02% 57.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 5 0.01% 57.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 35 0.09% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 3 0.01% 57.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 2 0.01% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 2 0.01% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 8 0.02% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 5 0.01% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 2 0.01% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 2 0.01% 57.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 7 0.02% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 3 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 2 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 2 0.01% 57.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 8 0.02% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 3 0.01% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 1 0.00% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 5 0.01% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 1 0.00% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 1 0.00% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 4 0.01% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 3 0.01% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 2 0.01% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 8 0.02% 57.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 4 0.01% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 3 0.01% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 2 0.01% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 2 0.01% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 2 0.01% 57.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 2 0.01% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 2 0.01% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 17 0.04% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 1 0.00% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 3 0.01% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 5 0.01% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 6 0.02% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 7 0.02% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 5 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 5 0.01% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 9 0.02% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 309 0.81% 59.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 22 0.06% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8575 151 0.40% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8639 180 0.47% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8703 3 0.01% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8831 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 2 0.01% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 2 0.01% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 2 0.01% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21055 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 1 0.00% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 7 0.02% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 12 0.03% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55872-55935 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 15142 39.88% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::67392-67455 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37970 # Bytes accessed per row activation -system.physmem.totQLat 300039544000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 394721941500 # Sum of mem lat for all requests -system.physmem.totBusLat 78454290000 # Total cycles spent in databus access -system.physmem.totBankLat 16228107500 # Total cycles spent in bank access -system.physmem.avgQLat 19121.93 # Average queueing delay per request -system.physmem.avgBankLat 1034.24 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25156.17 # Average memory access latency -system.physmem.avgRdBW 381.74 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.75 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.95 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.55 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 1.25 # Average write queue length over time -system.physmem.readRowHits 15666199 # Number of row buffer hits during reads -system.physmem.writeRowHits 93719 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.55 # Row buffer hit rate for writes -system.physmem.avgGap 159407.43 # Average gap between requests +system.physmem.bytesPerActivate::samples 90271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11200.204894 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1031.239605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16762.903946 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23441 25.97% 25.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14726 16.31% 42.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2829 3.13% 45.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2153 2.39% 47.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1359 1.51% 49.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1176 1.30% 50.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 955 1.06% 51.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1145 1.27% 52.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 612 0.68% 53.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 559 0.62% 54.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 621 0.69% 54.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 534 0.59% 55.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 322 0.36% 55.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 268 0.30% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 218 0.24% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 586 0.65% 57.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 164 0.18% 57.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 127 0.14% 57.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 130 0.14% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 257 0.28% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 89 0.10% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 142 0.16% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 48 0.05% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 45 0.05% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 41 0.05% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 166 0.18% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 19 0.02% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 18 0.02% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 150 0.17% 61.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 341 0.38% 61.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 19 0.02% 61.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 17 0.02% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 76 0.08% 61.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 15 0.02% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 8 0.01% 61.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 16 0.02% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 76 0.08% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 11 0.01% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 6 0.01% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 22 0.02% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 3 0.00% 61.90% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 2 0.00% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 1 0.00% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 71 0.08% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 129 0.14% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 3 0.00% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 75 0.08% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 261 0.29% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 1 0.00% 64.25% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 69 0.08% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 128 0.14% 68.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 328 0.36% 69.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 133 0.15% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 193 0.21% 69.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 136 0.15% 69.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 377 0.42% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 11 0.01% 70.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 64 0.07% 70.18% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 2 0.00% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 391 0.43% 73.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 128 0.14% 73.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 67 0.07% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 131 0.15% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 320 0.35% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 67 0.07% 73.80% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 121 0.13% 76.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 253 0.28% 77.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 133 0.15% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 10 0.01% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 70 0.08% 77.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 519 0.57% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 69 0.08% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 10 0.01% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 133 0.15% 78.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 251 0.28% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 120 0.13% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 70 0.08% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 64 0.07% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 387 0.43% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 134 0.15% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 119 0.13% 79.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 56 0.06% 79.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 259 0.29% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 71 0.08% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 68 0.08% 79.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 125 0.14% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 325 0.36% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 133 0.15% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 192 0.21% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 377 0.42% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 11 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 65 0.07% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 69 0.08% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 321 0.36% 81.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 130 0.14% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 67 0.07% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 128 0.14% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 390 0.43% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 1 0.00% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 67 0.07% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 130 0.14% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 640 0.71% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 132 0.15% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 70 0.08% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 1 0.00% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 389 0.43% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 128 0.14% 84.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 67 0.07% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 130 0.14% 84.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 318 0.35% 84.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 68 0.08% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 64 0.07% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 10 0.01% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 377 0.42% 85.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 136 0.15% 85.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 192 0.21% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 132 0.15% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 324 0.36% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 125 0.14% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 68 0.08% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 71 0.08% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 259 0.29% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 56 0.06% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 119 0.13% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 134 0.15% 87.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 387 0.43% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 64 0.07% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 69 0.08% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 119 0.13% 88.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 251 0.28% 88.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 133 0.15% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 9 0.01% 88.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 68 0.08% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 518 0.57% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 69 0.08% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 10 0.01% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 133 0.15% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 252 0.28% 89.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 120 0.13% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 67 0.07% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 64 0.07% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 388 0.43% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 134 0.15% 90.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 119 0.13% 90.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 56 0.06% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 260 0.29% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 71 0.08% 91.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 69 0.08% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 124 0.14% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 325 0.36% 91.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 131 0.15% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 191 0.21% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 137 0.15% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 375 0.42% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 11 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 66 0.07% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 66 0.07% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 319 0.35% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 133 0.15% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 67 0.07% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 129 0.14% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 390 0.43% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 67 0.07% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 131 0.15% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5359 5.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90271 # Bytes accessed per row activation +system.physmem.totQLat 377292466250 # Total ticks spent queuing +system.physmem.totMemAccLat 474547986250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454375000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18801145000 # Total ticks spent accessing banks +system.physmem.avgQLat 24045.34 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1198.22 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30243.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing +system.physmem.readRowHits 15616441 # Number of row buffer hits during reads +system.physmem.writeRowHits 91020 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.18 # Row buffer hit rate for writes +system.physmem.avgGap 159454.26 # Average gap between requests +system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -384,249 +508,249 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54407704 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743613 # Transaction distribution -system.membus.trans_dist::ReadResp 16743613 # Transaction distribution +system.membus.throughput 54391586 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743633 # Transaction distribution +system.membus.trans_dist::ReadResp 16743633 # Transaction distribution system.membus.trans_dist::WriteReq 763392 # Transaction distribution system.membus.trans_dist::WriteResp 763392 # Transaction distribution -system.membus.trans_dist::Writeback 57666 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution -system.membus.trans_dist::ReadExReq 131350 # Transaction distribution -system.membus.trans_dist::ReadExResp 131350 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57664 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution +system.membus.trans_dist::ReadExReq 131346 # Transaction distribution +system.membus.trans_dist::ReadExResp 131346 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892496 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279356 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279376 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343420 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35343440 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18870833 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18870589 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143127089 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143127089 # Total data (bytes) +system.membus.tot_pkt_size::total 143126845 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143126845 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1209125000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1220589500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3743000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3747000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18109707000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18118484000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4946568726 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4951896724 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35058992750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35075499000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 62061 # number of replacements -system.l2c.tags.tagsinuse 51615.718916 # Cycle average of tags in use -system.l2c.tags.total_refs 1699022 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127446 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.331309 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2575798778500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38215.031353 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2892.274749 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3021.606158 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4129.656737 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3357.149045 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583115 # Average percentage of cache occupancy +system.l2c.tags.replacements 62057 # number of replacements +system.l2c.tags.tagsinuse 51615.015118 # Cycle average of tags in use +system.l2c.tags.total_refs 1699237 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127445 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.333101 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2576505750500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38217.986822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2603.292629 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3037.110347 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4418.327235 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3338.297198 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583160 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.044133 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046106 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.039723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046343 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.063014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.051226 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787593 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9999 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 436599 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 185177 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9919 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3623 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 407829 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 185133 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241869 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596358 # number of Writeback hits -system.l2c.Writeback_hits::total 596358 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.067418 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050938 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787583 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9914 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3649 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 415311 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 183212 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10008 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3517 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 429187 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 187142 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241940 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596380 # number of Writeback hits +system.l2c.Writeback_hits::total 596380 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 59730 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54783 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114513 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9999 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 436599 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 244907 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9919 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3623 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 407829 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 239916 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356382 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9999 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3590 # number of overall hits -system.l2c.overall_hits::cpu0.inst 436599 # number of overall hits -system.l2c.overall_hits::cpu0.data 244907 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9919 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3623 # number of overall hits -system.l2c.overall_hits::cpu1.inst 407829 # number of overall hits -system.l2c.overall_hits::cpu1.data 239916 # number of overall hits -system.l2c.overall_hits::total 1356382 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 56696 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57849 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114545 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9914 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3649 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 415311 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 239908 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10008 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3517 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 429187 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 244991 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356485 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9914 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3649 # number of overall hits +system.l2c.overall_hits::cpu0.inst 415311 # number of overall hits +system.l2c.overall_hits::cpu0.data 239908 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10008 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3517 # number of overall hits +system.l2c.overall_hits::cpu1.inst 429187 # number of overall hits +system.l2c.overall_hits::cpu1.data 244991 # number of overall hits +system.l2c.overall_hits::total 1356485 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4438 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5378 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 3942 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5224 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6154 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4852 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20825 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1446 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1435 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2881 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 69963 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 63028 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132991 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 6651 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 5006 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20826 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1375 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1512 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63889.532561 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60684.612984 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.696864 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.347102 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 51487.266155 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51542.073190 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 51513.240678 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51802.963884 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58415.657469 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58335.455393 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58377.311545 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51802.963884 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -765,6 +892,7 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate @@ -774,45 +902,45 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52764048 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471787 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471787 # Transaction distribution +system.toL2Bus.throughput 52751818 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471631 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471631 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596358 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247504 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247504 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1724904 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753314 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20307 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50676 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549201 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54747764 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83776253 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79676 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138632553 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138632553 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 170668 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808102000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 596380 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2913 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2913 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247521 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247521 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725079 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753474 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20108 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50543 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549204 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54752376 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83781573 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138642313 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138642313 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 169620 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808134500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865742750 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865505750 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4428115774 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4420696776 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13092500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12940000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30757250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30620250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48142902 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715359 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715359 # Transaction distribution +system.iobus.throughput 48128720 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715358 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715358 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution system.iobus.trans_dist::WriteResp 8167 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -834,12 +962,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447050 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -861,14 +989,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646649 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646649 # Total data (bytes) +system.iobus.tot_pkt_size::total 126646645 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646645 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -914,141 +1042,141 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374821000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374819000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42581193250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42584048000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7542817 # DTB read hits -system.cpu0.dtb.read_misses 7082 # DTB read misses -system.cpu0.dtb.write_hits 5717425 # DTB write hits -system.cpu0.dtb.write_misses 1778 # DTB write misses +system.cpu0.dtb.read_hits 7352406 # DTB read hits +system.cpu0.dtb.read_misses 6766 # DTB read misses +system.cpu0.dtb.write_hits 5599485 # DTB write hits +system.cpu0.dtb.write_misses 1847 # DTB write misses system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6542 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6337 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 149 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 131 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7549899 # DTB read accesses -system.cpu0.dtb.write_accesses 5719203 # DTB write accesses +system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7359172 # DTB read accesses +system.cpu0.dtb.write_accesses 5601332 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13260242 # DTB hits -system.cpu0.dtb.misses 8860 # DTB misses -system.cpu0.dtb.accesses 13269102 # DTB accesses -system.cpu0.itb.inst_hits 30610477 # ITB inst hits -system.cpu0.itb.inst_misses 3712 # ITB inst misses +system.cpu0.dtb.hits 12951891 # DTB hits +system.cpu0.dtb.misses 8613 # DTB misses +system.cpu0.dtb.accesses 12960504 # DTB accesses +system.cpu0.itb.inst_hits 30170189 # ITB inst hits +system.cpu0.itb.inst_misses 3579 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2775 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30614189 # ITB inst accesses -system.cpu0.itb.hits 30610477 # DTB hits -system.cpu0.itb.misses 3712 # DTB misses -system.cpu0.itb.accesses 30614189 # DTB accesses -system.cpu0.numCycles 2629428479 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30173768 # ITB inst accesses +system.cpu0.itb.hits 30170189 # DTB hits +system.cpu0.itb.misses 3579 # DTB misses +system.cpu0.itb.accesses 30173768 # DTB accesses +system.cpu0.numCycles 2629696361 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30009354 # Number of instructions committed -system.cpu0.committedOps 38372334 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34511671 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5157 # Number of float alu accesses -system.cpu0.num_func_calls 1080838 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3989390 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34511671 # number of integer instructions -system.cpu0.num_fp_insts 5157 # number of float instructions -system.cpu0.num_int_register_reads 198034256 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36980567 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3554 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1606 # number of times the floating registers were written -system.cpu0.num_mem_refs 13842126 # number of memory refs -system.cpu0.num_load_insts 7871888 # Number of load instructions -system.cpu0.num_store_insts 5970238 # Number of store instructions -system.cpu0.num_idle_cycles 2283161569.446249 # Number of idle cycles -system.cpu0.num_busy_cycles 346266909.553751 # Number of busy cycles -system.cpu0.not_idle_fraction 0.131689 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.868311 # Percentage of idle cycles +system.cpu0.committedInsts 29597158 # Number of instructions committed +system.cpu0.committedOps 37762240 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33970200 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4584 # Number of float alu accesses +system.cpu0.num_func_calls 1050225 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3920547 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33970200 # number of integer instructions +system.cpu0.num_fp_insts 4584 # number of float instructions +system.cpu0.num_int_register_reads 194623734 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36521551 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3225 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1362 # number of times the floating registers were written +system.cpu0.num_mem_refs 13522491 # number of memory refs +system.cpu0.num_load_insts 7673972 # Number of load instructions +system.cpu0.num_store_insts 5848519 # Number of store instructions +system.cpu0.num_idle_cycles 2290697984.129271 # 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number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 315551 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 303842 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 619393 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 315551 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 303842 # number of overall misses -system.cpu0.dcache.overall_misses::total 619393 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2725468500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2705402500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5430871000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5537493548 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5008087224 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10545580772 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82157000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77679750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 159836750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8262962048 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 7713489724 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15976451772 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8262962048 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 7713489724 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15976451772 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6818455 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6749390 # 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number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12025221 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11767828 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23793049 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12025221 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11767828 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23793049 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027043 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027349 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027195 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025190 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023763 # 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average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14656.437580 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14718.525565 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42220.343161 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41995.129924 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42113.089169 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13335.010550 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14393.135075 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13829.101056 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25793.723487 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25793.723487 # average overall miss latency +system.cpu0.dcache.tags.replacements 627593 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.877442 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23660330 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628105 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.669386 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.884282 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 328.993161 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.357196 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642565 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6452957 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6745780 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13198737 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4964348 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 5010385 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9974733 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118524 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117664 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236188 # 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number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 122951 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250434 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6110 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5462 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11572 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 309809 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 309637 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 619446 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 309809 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 309637 # number of overall misses +system.cpu0.dcache.overall_misses::total 619446 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2717177250 # 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average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14372.665690 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13859.726063 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 27325.781451 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 27325.781451 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1217,77 +1349,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596358 # number of writebacks -system.cpu0.dcache.writebacks::total 596358 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184394 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 184588 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 368982 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131157 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 119254 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250411 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6161 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5397 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11558 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 315551 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 303842 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619393 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 315551 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 303842 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619393 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2354074500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2333925500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4688000000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5241357452 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4739135776 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9980493228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69822000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66822250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136644250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7595431952 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7073061276 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 14668493228 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7595431952 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7073061276 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14668493228 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91831657250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90223318750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182054976000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13223525999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13011841499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235367498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105055183249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103235160249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208290343498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027043 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027349 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027195 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025190 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023763 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048594 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044613 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046650 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12766.546092 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12643.971981 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.226813 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39962.468278 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.847519 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39856.448910 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11332.900503 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12381.369279 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.482263 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596380 # number of writebacks +system.cpu0.dcache.writebacks::total 596380 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182326 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186686 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369012 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127483 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 122951 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250434 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6110 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11572 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309809 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 309637 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619446 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309809 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 309637 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619446 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2351238750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2390198500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741437250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5650406828 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5242308905 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10892715733 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69656750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67531500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137188250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8001645578 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7632507405 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15634152983 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8001645578 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7632507405 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15634152983 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91105263250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90961118500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182066381750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13264461491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12970911500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235372991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104369724741 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103932030000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208301754741 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027478 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026929 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027198 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025037 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023951 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049024 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044361 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046706 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12895.795169 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.308764 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12849.005588 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44322.826008 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42637.383226 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43495.354996 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11400.450082 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12363.877700 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11855.189250 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1300,68 +1432,68 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7456887 # DTB read hits -system.cpu1.dtb.read_misses 7096 # DTB read misses -system.cpu1.dtb.write_hits 5515190 # DTB write hits -system.cpu1.dtb.write_misses 1853 # DTB write misses -system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7647205 # DTB read hits +system.cpu1.dtb.read_misses 7298 # DTB read misses +system.cpu1.dtb.write_hits 5633094 # DTB write hits +system.cpu1.dtb.write_misses 1843 # DTB write misses +system.cpu1.dtb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6662 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6730 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7463983 # DTB read accesses -system.cpu1.dtb.write_accesses 5517043 # DTB write accesses +system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7654503 # DTB read accesses +system.cpu1.dtb.write_accesses 5634937 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12972077 # DTB hits -system.cpu1.dtb.misses 8949 # DTB misses -system.cpu1.dtb.accesses 12981026 # DTB accesses -system.cpu1.itb.inst_hits 30894824 # ITB inst hits -system.cpu1.itb.inst_misses 3669 # ITB inst misses +system.cpu1.dtb.hits 13280299 # DTB hits +system.cpu1.dtb.misses 9141 # DTB misses +system.cpu1.dtb.accesses 13289440 # DTB accesses +system.cpu1.itb.inst_hits 31334771 # ITB inst hits +system.cpu1.itb.inst_misses 3728 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2813 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2858 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30898493 # ITB inst accesses -system.cpu1.itb.hits 30894824 # DTB hits -system.cpu1.itb.misses 3669 # DTB misses -system.cpu1.itb.accesses 30898493 # DTB accesses -system.cpu1.numCycles 2631851734 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31338499 # ITB inst accesses +system.cpu1.itb.hits 31334771 # DTB hits +system.cpu1.itb.misses 3728 # DTB misses +system.cpu1.itb.accesses 31338499 # DTB accesses +system.cpu1.numCycles 2633133982 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30201855 # Number of instructions committed -system.cpu1.committedOps 38245582 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34372038 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5112 # Number of float alu accesses -system.cpu1.num_func_calls 1059508 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3959978 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34372038 # number of integer instructions -system.cpu1.num_fp_insts 5112 # number of float instructions -system.cpu1.num_int_register_reads 196814123 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37215593 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3939 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1174 # number of times the floating registers were written -system.cpu1.num_mem_refs 13557754 # number of memory refs -system.cpu1.num_load_insts 7792008 # Number of load instructions -system.cpu1.num_store_insts 5765746 # Number of store instructions -system.cpu1.num_idle_cycles 2293589601.195636 # Number of idle cycles -system.cpu1.num_busy_cycles 338262132.804364 # Number of busy cycles -system.cpu1.not_idle_fraction 0.128526 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.871474 # Percentage of idle cycles +system.cpu1.committedInsts 30613725 # Number of instructions committed +system.cpu1.committedOps 38855266 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34913201 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5685 # Number of float alu accesses +system.cpu1.num_func_calls 1090107 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4028756 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34913201 # number of integer instructions +system.cpu1.num_fp_insts 5685 # number of float instructions +system.cpu1.num_int_register_reads 200222637 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37674133 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4268 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written +system.cpu1.num_mem_refs 13877284 # number of memory refs +system.cpu1.num_load_insts 7989860 # Number of load instructions +system.cpu1.num_store_insts 5887424 # Number of store instructions +system.cpu1.num_idle_cycles 2288817928.029144 # Number of idle cycles +system.cpu1.num_busy_cycles 344316053.970855 # Number of busy cycles +system.cpu1.not_idle_fraction 0.130763 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.869237 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1378,10 +1510,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1478384126250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1478384126250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1557205456000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1557205456000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |