diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
| commit | d6283445744d5be2a9ac33f0adbc729d48e22c40 (patch) | |
| tree | 67910602fd144f50fa86b1c8a90e0e4f0e66ee90 /tests/long/fs/10.linux-boot/ref/arm | |
| parent | cf5935445f23d0ba2f41debc50952fe45d7c9f4a (diff) | |
| download | gem5-d6283445744d5be2a9ac33f0adbc729d48e22c40.tar.xz | |
Device: Update stats for PIO and PCI latency change
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
3 files changed, 2864 insertions, 2860 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 0e9aa5888..5540dd947 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,209 +1,209 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503329 # Number of seconds simulated -sim_ticks 2503329223500 # Number of ticks simulated -final_tick 2503329223500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.538055 # Number of seconds simulated +sim_ticks 2538055224500 # Number of ticks simulated +final_tick 2538055224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55645 # Simulator instruction rate (inst/s) -host_op_rate 71576 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2298862295 # Simulator tick rate (ticks/s) -host_mem_usage 394936 # Number of bytes of host memory used -host_seconds 1088.94 # Real time elapsed on the host -sim_insts 60594713 # Number of instructions simulated -sim_ops 77942287 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory +host_inst_rate 74782 # Simulator instruction rate (inst/s) +host_op_rate 96192 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3131579061 # Simulator tick rate (ticks/s) +host_mem_usage 390232 # Number of bytes of host memory used +host_seconds 810.47 # Real time elapsed on the host +sim_insts 60608338 # Number of instructions simulated +sim_ops 77960937 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory -system.physmem.bytes_read::total 129435024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9090192 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3781888 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6797960 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12493 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096888 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12492 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142068 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293438 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59092 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47751475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 319395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3632775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51705154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 319395 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319395 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1512073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1204824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2716897 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1512073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47751475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 319395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4837599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54422052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813110 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47717846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3581558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51615968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1490073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188340 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2678413 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1490073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47717846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4769898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54294380 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64407 # number of replacements -system.l2c.tagsinuse 51237.721374 # Cycle average of tags in use -system.l2c.total_refs 1963815 # Total number of references to valid blocks. -system.l2c.sampled_refs 129804 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.129079 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2492699118000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36773.515896 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 46.128401 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.000184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8177.854263 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6240.222629 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.561119 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000704 # Average percentage of cache occupancy +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 64349 # number of replacements +system.l2c.tagsinuse 51370.291201 # Cycle average of tags in use +system.l2c.total_refs 1966684 # Total number of references to valid blocks. +system.l2c.sampled_refs 129742 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.158422 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2527049892000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36909.964338 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 48.537302 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 8186.541319 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6225.247998 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563201 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000741 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124784 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.095218 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781826 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 123734 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11927 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 976636 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 387128 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1499425 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 607519 # number of Writeback hits -system.l2c.Writeback_hits::total 607519 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 41 # number of UpgradeReq hits +system.l2c.occ_percent::cpu.inst 0.124917 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.094990 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783848 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 122661 # 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number of overall misses +system.l2c.overall_misses::cpu.data 143855 # number of overall misses +system.l2c.overall_misses::total 156289 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3190500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 659327498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 562370998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1224793496 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 994500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 994500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7086596499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7086596499 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 3035000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 658900997 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 562244999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1224396496 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7068682495 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7068682495 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3190500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 659327498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7648967497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8311389995 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 3035000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu.inst 658900997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7630927494 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8293078991 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 3190500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 659327498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7648967497 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8311389995 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 123792 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11928 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 989010 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166750976500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32068433085 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32068433085 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5323000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 162829894011 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 162835217011 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000469 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012503 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026721 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015142 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.111111 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.111111 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541649 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541649 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000469 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012503 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.223448 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088365 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000469 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012503 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.223448 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088365 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu.data 198814086585 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 198819409585 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026679 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015132 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.987079 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.987079 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541115 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541115 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088264 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088264 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41080.219877 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40479.256820 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40800.975884 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.758336 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.758336 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41051.758835 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40465.011287 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40779.001605 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40066.999656 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40066.999656 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40966.138456 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40966.138456 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41080.219877 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40930.159396 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40941.772131 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41080.219877 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40930.159396 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40941.772131 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,26 +332,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048154 # DTB read hits -system.cpu.checker.dtb.read_misses 7314 # DTB read misses -system.cpu.checker.dtb.write_hits 11293808 # DTB write hits -system.cpu.checker.dtb.write_misses 2189 # DTB write misses +system.cpu.checker.dtb.read_hits 15052335 # DTB read hits +system.cpu.checker.dtb.read_misses 7317 # DTB read misses +system.cpu.checker.dtb.write_hits 11295995 # DTB write hits +system.cpu.checker.dtb.write_misses 2195 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 181 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15055468 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11295997 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15059652 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11298190 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26341962 # DTB hits -system.cpu.checker.dtb.misses 9503 # DTB misses -system.cpu.checker.dtb.accesses 26351465 # DTB accesses -system.cpu.checker.itb.inst_hits 61773470 # ITB inst hits +system.cpu.checker.dtb.hits 26348330 # DTB hits +system.cpu.checker.dtb.misses 9512 # DTB misses +system.cpu.checker.dtb.accesses 26357842 # DTB accesses +system.cpu.checker.itb.inst_hits 61787107 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -368,36 +368,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61777941 # ITB inst accesses -system.cpu.checker.itb.hits 61773470 # DTB hits +system.cpu.checker.itb.inst_accesses 61791578 # ITB inst accesses +system.cpu.checker.itb.hits 61787107 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61777941 # DTB accesses -system.cpu.checker.numCycles 78232851 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61791578 # DTB accesses +system.cpu.checker.numCycles 78251513 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51771178 # DTB read hits -system.cpu.dtb.read_misses 82022 # DTB read misses -system.cpu.dtb.write_hits 11879780 # DTB write hits -system.cpu.dtb.write_misses 18404 # DTB write misses +system.cpu.dtb.read_hits 51779226 # DTB read hits +system.cpu.dtb.read_misses 81574 # DTB read misses +system.cpu.dtb.write_hits 11882622 # DTB write hits +system.cpu.dtb.write_misses 18093 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8063 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2874 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 631 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 8066 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3293 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 606 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1260 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51853200 # DTB read accesses -system.cpu.dtb.write_accesses 11898184 # DTB write accesses +system.cpu.dtb.perms_faults 1237 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51860800 # DTB read accesses +system.cpu.dtb.write_accesses 11900715 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63650958 # DTB hits -system.cpu.dtb.misses 100426 # DTB misses -system.cpu.dtb.accesses 63751384 # DTB accesses -system.cpu.itb.inst_hits 13147400 # ITB inst hits -system.cpu.itb.inst_misses 12275 # ITB inst misses +system.cpu.dtb.hits 63661848 # DTB hits +system.cpu.dtb.misses 99667 # DTB misses +system.cpu.dtb.accesses 63761515 # DTB accesses +system.cpu.itb.inst_hits 13144692 # ITB inst hits +system.cpu.itb.inst_misses 11967 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -406,121 +406,121 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5278 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5259 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3416 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13159675 # ITB inst accesses -system.cpu.itb.hits 13147400 # DTB hits -system.cpu.itb.misses 12275 # DTB misses -system.cpu.itb.accesses 13159675 # DTB accesses -system.cpu.numCycles 415310668 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13156659 # ITB inst accesses +system.cpu.itb.hits 13144692 # DTB hits +system.cpu.itb.misses 11967 # DTB misses +system.cpu.itb.accesses 13156659 # DTB accesses +system.cpu.numCycles 487285069 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15527738 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12466555 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753811 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10646284 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8367014 # Number of BTB hits +system.cpu.BPredUnit.lookups 15533008 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12472748 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 753945 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10621013 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8369898 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1449693 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80905 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33357472 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101736318 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15527738 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9816707 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22310929 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6078281 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 161634 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94635812 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2484 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 132549 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208778 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 375 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13143214 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1025665 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6564 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154991090 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.809239 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.178893 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1450891 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 81082 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33390116 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101781554 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15533008 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9820789 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22319812 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6080499 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 158808 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102222011 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133571 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 207903 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13140422 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1021772 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6316 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162617823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.771724 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.134680 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132697054 85.62% 85.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1371702 0.89% 86.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1758298 1.13% 87.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2653739 1.71% 89.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2357523 1.52% 90.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1143564 0.74% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2918516 1.88% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 809258 0.52% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9281436 5.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140314971 86.29% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1367844 0.84% 87.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1761669 1.08% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2653320 1.63% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2361626 1.45% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1142802 0.70% 92.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2916048 1.79% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 808288 0.50% 94.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9291255 5.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154991090 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.037388 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.244964 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35540110 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94304374 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20024957 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1112327 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4009322 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100739 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174603 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118268322 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 570412 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4009322 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37657945 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39869078 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47822984 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18880557 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6751204 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110681454 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22988 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1160036 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4497834 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31020 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115504222 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 506609726 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506516210 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93516 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727449 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36776772 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 900485 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 799637 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13564830 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21065339 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13879000 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1961867 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2663971 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101316574 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2057711 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126458108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 199553 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24657438 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65563204 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 513311 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154991090 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.815906 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.514046 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162617823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031877 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208875 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35567426 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101892214 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20037549 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1109983 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4010651 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2100654 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174914 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118316762 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572114 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4010651 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37681511 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40491658 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54797467 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18895098 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6741438 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110776004 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22866 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1160313 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4487001 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30716 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115615239 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 507028919 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506935731 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 93188 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78747197 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36868041 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898954 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797959 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13563069 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21067127 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13877132 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1956196 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2590406 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101357427 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059773 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126494913 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 198538 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24680718 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65543860 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514575 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162617823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.777866 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488052 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108868078 70.24% 70.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14887887 9.61% 79.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7383585 4.76% 84.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6313472 4.07% 88.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12622401 8.14% 96.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2812506 1.81% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1537255 0.99% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 440277 0.28% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125629 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116473756 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14895850 9.16% 80.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7383355 4.54% 85.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6325930 3.89% 89.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12628751 7.77% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2810327 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536412 0.94% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438084 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125358 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154991090 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162617823 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 54148 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53829 0.61% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available @@ -549,397 +549,397 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8364176 94.75% 95.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 409089 4.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366722 94.73% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411335 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60068751 47.50% 47.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95236 0.08% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53417106 42.24% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12511205 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60100692 47.51% 47.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95407 0.08% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53419362 42.23% 90.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12513627 9.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126458108 # Type of FU issued -system.cpu.iq.rate 0.304490 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8827417 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069805 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417011386 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128052835 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87416470 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22950 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12920 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10331 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134909754 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12105 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 645788 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126494913 # Type of FU issued +system.cpu.iq.rate 0.259591 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8831890 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069820 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 424714403 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128119104 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87467949 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22973 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12866 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10326 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134951003 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12134 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 645792 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5350138 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11136 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35101 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2080838 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5347388 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11096 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35111 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2076739 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107263 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1048290 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107215 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052024 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4009322 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29478613 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 536036 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103628902 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 217385 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21065339 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13879000 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1466402 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126510 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 31155 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35101 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376939 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332400 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709339 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123236608 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52461044 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3221500 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4010651 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30083339 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540488 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103672693 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 219471 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21067127 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13877132 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1468075 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126042 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 41068 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35111 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 376458 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332668 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 709126 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123289616 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52469824 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3205297 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 254617 # number of nop insts executed -system.cpu.iew.exec_refs 64851969 # number of memory reference insts executed -system.cpu.iew.exec_branches 11926568 # Number of branches executed -system.cpu.iew.exec_stores 12390925 # Number of stores executed -system.cpu.iew.exec_rate 0.296734 # Inst execution rate -system.cpu.iew.wb_sent 121860265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87426801 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47494075 # num instructions producing a value -system.cpu.iew.wb_consumers 86379183 # num instructions consuming a value +system.cpu.iew.exec_nop 255493 # number of nop insts executed +system.cpu.iew.exec_refs 64863659 # number of memory reference insts executed +system.cpu.iew.exec_branches 11931891 # Number of branches executed +system.cpu.iew.exec_stores 12393835 # Number of stores executed +system.cpu.iew.exec_rate 0.253013 # Inst execution rate +system.cpu.iew.wb_sent 121912605 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87478275 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47524907 # num instructions producing a value +system.cpu.iew.wb_consumers 86445005 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.210509 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549832 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179522 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549770 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 60745094 # The number of committed instructions -system.cpu.commit.commitCommittedOps 78092668 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24728606 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544400 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625654 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151064180 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.516950 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.491641 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 60758719 # The number of committed instructions +system.cpu.commit.commitCommittedOps 78111318 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24740610 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545198 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625619 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158689613 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492227 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459221 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122872114 81.34% 81.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13991345 9.26% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3943128 2.61% 93.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2231050 1.48% 94.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2009345 1.33% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1063949 0.70% 96.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402638 0.93% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 655924 0.43% 98.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2894687 1.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130476861 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14004142 8.82% 91.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3942589 2.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2238161 1.41% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2017118 1.27% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1061710 0.67% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402075 0.88% 97.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657613 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889344 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151064180 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60745094 # Number of instructions committed -system.cpu.commit.committedOps 78092668 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158689613 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60758719 # Number of instructions committed +system.cpu.commit.committedOps 78111318 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513363 # Number of memory references committed -system.cpu.commit.loads 15715201 # Number of loads committed -system.cpu.commit.membars 413054 # Number of memory barriers committed -system.cpu.commit.branches 10161447 # Number of branches committed +system.cpu.commit.refs 27520132 # Number of memory references committed +system.cpu.commit.loads 15719739 # Number of loads committed +system.cpu.commit.membars 413350 # Number of memory barriers committed +system.cpu.commit.branches 10163894 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69131310 # Number of committed integer instructions. -system.cpu.commit.function_calls 995952 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2894687 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69148099 # Number of committed integer instructions. +system.cpu.commit.function_calls 996264 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889344 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 249075594 # The number of ROB reads -system.cpu.rob.rob_writes 209750294 # The number of ROB writes -system.cpu.timesIdled 1905944 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260319578 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591259733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60594713 # Number of Instructions Simulated -system.cpu.committedOps 77942287 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60594713 # Number of Instructions Simulated -system.cpu.cpi 6.853909 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.853909 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145902 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.145902 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 557815351 # number of integer regfile reads -system.cpu.int_regfile_writes 90098493 # number of integer regfile writes -system.cpu.fp_regfile_reads 8218 # number of floating regfile reads -system.cpu.fp_regfile_writes 2870 # number of floating regfile writes -system.cpu.misc_regfile_reads 134021846 # number of misc regfile reads -system.cpu.misc_regfile_writes 912706 # number of misc regfile writes -system.cpu.icache.replacements 989908 # number of replacements -system.cpu.icache.tagsinuse 511.610984 # Cycle average of tags in use -system.cpu.icache.total_refs 12068184 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990420 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.184915 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6426400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.610984 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999240 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999240 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12068184 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12068184 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12068184 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12068184 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12068184 # number of overall hits -system.cpu.icache.overall_hits::total 12068184 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1074896 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1074896 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1074896 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1074896 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1074896 # number of overall misses -system.cpu.icache.overall_misses::total 1074896 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16638687991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16638687991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16638687991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16638687991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16638687991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16638687991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13143080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13143080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13143080 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13143080 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13143080 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13143080 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081784 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081784 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081784 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081784 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081784 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081784 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15479.346831 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15479.346831 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15479.346831 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15479.346831 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15479.346831 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15479.346831 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2960492 # number of cycles access was blocked +system.cpu.rob.rob_reads 256736769 # The number of ROB reads +system.cpu.rob.rob_writes 209812510 # The number of ROB writes +system.cpu.timesIdled 1906775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324667246 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4588737338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60608338 # Number of Instructions Simulated +system.cpu.committedOps 77960937 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60608338 # Number of Instructions Simulated +system.cpu.cpi 8.039902 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.039902 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124380 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124380 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 558055788 # number of integer regfile reads +system.cpu.int_regfile_writes 90157821 # number of integer regfile writes +system.cpu.fp_regfile_reads 8288 # number of floating regfile reads +system.cpu.fp_regfile_writes 2908 # number of floating regfile writes +system.cpu.misc_regfile_reads 134082325 # number of misc regfile reads +system.cpu.misc_regfile_writes 913357 # number of misc regfile writes +system.cpu.icache.replacements 991945 # number of replacements +system.cpu.icache.tagsinuse 511.576100 # Cycle average of tags in use +system.cpu.icache.total_refs 12062971 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 992457 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.154654 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225347000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.576100 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12062971 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12062971 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12062971 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12062971 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12062971 # number of overall hits +system.cpu.icache.overall_hits::total 12062971 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1077319 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1077319 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1077319 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1077319 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1077319 # number of overall misses +system.cpu.icache.overall_misses::total 1077319 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16672871489 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16672871489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16672871489 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16672871489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16672871489 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16672871489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13140290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13140290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13140290 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13140290 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13140290 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13140290 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081986 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081986 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081986 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081986 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081986 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081986 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15476.262360 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15476.262360 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15476.262360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15476.262360 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2904990 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 448 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 436 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6608.241071 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6662.821101 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84437 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84437 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84437 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84437 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84437 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84437 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990459 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 990459 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 990459 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 990459 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 990459 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 990459 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12623481992 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12623481992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12623481992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12623481992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12623481992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12623481992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84824 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84824 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84824 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84824 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84824 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84824 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992495 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 992495 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 992495 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 992495 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 992495 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 992495 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12649346990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12649346990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12649346990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12649346990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12649346990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12649346990 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075360 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075360 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075360 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.082827 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.082827 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.082827 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.082827 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.082827 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.082827 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075531 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075531 # 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Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991338 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.991456 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13902749 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13902749 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7257426 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7257426 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 285261 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 285261 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285646 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285664 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285664 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24918184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24918184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24918184 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24918184 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052159 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052159 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.291985 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.291985 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046116 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046116 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000063 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000063 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.150814 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.150814 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.150814 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.150814 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19419.433138 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19419.433138 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43502.428225 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43502.428225 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16212.783700 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16212.783700 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19416.666667 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19416.666667 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38599.621520 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38599.621520 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38599.621520 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38599.621520 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 34077900 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7429000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7467 # 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number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21166629 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21166629 # number of overall hits +system.cpu.dcache.overall_hits::total 21166629 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 766922 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 766922 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2994004 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2994004 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13808 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13808 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3760926 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3760926 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3760926 # number of overall misses +system.cpu.dcache.overall_misses::total 3760926 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14892290500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14892290500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129258725578 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129258725578 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223775000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223775000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 402000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 402000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144151016078 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144151016078 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144151016078 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144151016078 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14675127 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14675127 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10252428 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10252428 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297121 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 297121 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285791 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285791 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24927555 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24927555 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24927555 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24927555 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052260 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052260 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292029 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046473 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046473 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.150874 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.150874 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.150874 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150874 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19418.259614 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19418.259614 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43172.529355 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43172.529355 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16206.184820 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16206.184820 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21157.894737 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21157.894737 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38328.596755 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38328.596755 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38328.596755 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38328.596755 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33707409 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7420000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7431 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 286 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4536.052887 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25944.055944 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607519 # number of writebacks -system.cpu.dcache.writebacks::total 607519 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379422 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 379422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744177 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744177 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1481 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1481 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3123599 # 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number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 289000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15548788530 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15548788530 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15548788530 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15548788530 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147078103000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147078103000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41268229410 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41268229410 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188346332410 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 188346332410 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026291 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026291 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024270 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024270 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041163 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041163 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000063 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000063 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025460 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025460 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025460 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025460 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.709690 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.709690 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37328.953666 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37328.953666 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13279.528838 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13279.528838 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16055.555556 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16055.555556 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.053341 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.053341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.053341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.053341 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 608398 # number of writebacks +system.cpu.dcache.writebacks::total 608398 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 380638 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 380638 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2745107 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2745107 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1447 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3125745 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3125745 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3125745 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3125745 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386284 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386284 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248897 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248897 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635181 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635181 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635181 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635181 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6271229149 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6271229149 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9237690949 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9237690949 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 163909000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 163909000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 338000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 338000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15508920098 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15508920098 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15508920098 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15508920098 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411312500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411312500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41911168414 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41911168414 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224322480914 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224322480914 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041603 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041603 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025481 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025481 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025481 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025481 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16234.762892 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16234.762892 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37114.513027 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37114.513027 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13260.173125 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13260.173125 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17789.473684 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17789.473684 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24416.536543 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24416.536543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24416.536543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24416.536543 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -961,16 +961,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305424568773 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1305424568773 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305424568773 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1305424568773 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323890643510 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88047 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88043 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 977ccc85a..6a50fad21 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,320 +1,320 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.582310 # Number of seconds simulated -sim_ticks 2582310281500 # Number of ticks simulated -final_tick 2582310281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.617033 # Number of seconds simulated +sim_ticks 2617033170500 # Number of ticks simulated +final_tick 2617033170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62666 # Simulator instruction rate (inst/s) -host_op_rate 80652 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2566586582 # Simulator tick rate (ticks/s) -host_mem_usage 395816 # Number of bytes of host memory used -host_seconds 1006.13 # Real time elapsed on the host -sim_insts 63050246 # Number of instructions simulated -sim_ops 81146063 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +host_inst_rate 88113 # Simulator instruction rate (inst/s) +host_op_rate 113402 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3655705591 # Simulator tick rate (ticks/s) +host_mem_usage 391256 # Number of bytes of host memory used +host_seconds 715.88 # Real time elapsed on the host +sim_insts 63077791 # Number of instructions simulated +sim_ops 81181923 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 396544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4372212 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5220016 # Number of bytes read from this memory -system.physmem.bytes_read::total 129953444 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 396544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4241024 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 395840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4357428 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 425152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5244336 # Number of bytes read from this memory +system.physmem.bytes_read::total 131535204 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 425152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 820992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4255104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7270160 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7284240 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6196 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68388 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6650 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81589 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15105053 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66266 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68157 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6643 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81969 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15301800 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66486 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823550 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46290976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 153562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1693140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 273 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 164814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2021452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50324488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 153562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 164814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318375 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1642337 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1166450 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2815370 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1642337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46290976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 153562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1699723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 164814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3187902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53139859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 823770 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46277796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1665026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 162456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2003924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50261191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 162456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1625927 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1150974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2783396 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1625927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46277796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 151255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1671522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 162456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3154898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53044587 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # 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number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036447 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030192 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016228 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.844692 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.841171 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.843170 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.793313 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.771696 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.783986 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566781 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565982 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566342 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.241696 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091700 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241696 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091700 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40423.598914 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40402.220460 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40740.913730 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40028.692132 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40049.083314 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.487487 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.794872 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40019.031142 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40020.618557 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41111.835957 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40931.189956 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41013.105098 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40411.328872 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40404.341603 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40734.530859 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.288451 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.098817 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.500000 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40019.795658 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.245675 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40016.164585 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41094.922774 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40730.693596 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40895.030032 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41050.012880 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40890.905956 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40971.489573 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41050.012880 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40890.905956 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40971.489573 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -507,27 +507,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9083896 # DTB read hits -system.cpu0.dtb.read_misses 37543 # DTB read misses -system.cpu0.dtb.write_hits 5286239 # DTB write hits -system.cpu0.dtb.write_misses 6882 # DTB write misses +system.cpu0.dtb.read_hits 9087709 # DTB read hits +system.cpu0.dtb.read_misses 37707 # DTB read misses +system.cpu0.dtb.write_hits 5292852 # DTB write hits +system.cpu0.dtb.write_misses 6797 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2244 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1393 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 382 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2252 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1465 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9121439 # DTB read accesses -system.cpu0.dtb.write_accesses 5293121 # DTB write accesses +system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9125416 # DTB read accesses +system.cpu0.dtb.write_accesses 5299649 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14370135 # DTB hits -system.cpu0.dtb.misses 44425 # DTB misses -system.cpu0.dtb.accesses 14414560 # DTB accesses -system.cpu0.itb.inst_hits 4418601 # ITB inst hits -system.cpu0.itb.inst_misses 6114 # ITB inst misses +system.cpu0.dtb.hits 14380561 # DTB hits +system.cpu0.dtb.misses 44504 # DTB misses +system.cpu0.dtb.accesses 14425065 # DTB accesses +system.cpu0.itb.inst_hits 4426363 # ITB inst hits +system.cpu0.itb.inst_misses 5791 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -540,118 +540,118 @@ system.cpu0.itb.flush_entries 1409 # Nu system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1633 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1661 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4424715 # ITB inst accesses -system.cpu0.itb.hits 4418601 # DTB hits -system.cpu0.itb.misses 6114 # DTB misses -system.cpu0.itb.accesses 4424715 # DTB accesses -system.cpu0.numCycles 66354055 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4432154 # ITB inst accesses +system.cpu0.itb.hits 4426363 # DTB hits +system.cpu0.itb.misses 5791 # DTB misses +system.cpu0.itb.accesses 4432154 # DTB accesses +system.cpu0.numCycles 73540541 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6346252 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4857071 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 316053 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 4075974 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3037671 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6354280 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4863798 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 316535 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 4079773 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3047693 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 700378 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 30829 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12963003 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33274045 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6346252 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3738049 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7812188 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1602844 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 89446 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 22023764 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5932 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 73578 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 90886 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4416774 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 175280 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3223 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 44209960 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.971808 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.352806 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 700511 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 30883 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12981968 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 33339853 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6354280 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3748204 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7827899 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1608255 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 88516 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 23525864 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 77679 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 91798 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4424514 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 175463 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2818 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 45755598 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.940589 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.320885 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 36406101 82.35% 82.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 622907 1.41% 83.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 820090 1.85% 85.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 691511 1.56% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 794774 1.80% 88.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 578673 1.31% 90.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 721468 1.63% 91.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 370773 0.84% 92.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3203663 7.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 37936221 82.91% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 625086 1.37% 84.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 819758 1.79% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 695394 1.52% 87.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 800497 1.75% 89.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 578636 1.26% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 719119 1.57% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 370554 0.81% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3210333 7.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 44209960 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.095642 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.501462 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13460475 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 22052761 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7004876 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 606078 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1085770 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 992839 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66349 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41502146 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 217622 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1085770 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14072541 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6178049 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13569314 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6948288 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2355998 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40249124 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2572 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 473537 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1335703 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 188 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40597200 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 181819083 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 181783808 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 35275 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31678350 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8918849 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 463403 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 418800 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5692374 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7927385 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5883720 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1132627 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1230816 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 38008933 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 947103 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38247071 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 93468 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6756686 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14324325 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 258267 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 44209960 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.865123 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.479533 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 45755598 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086405 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.453353 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 13479181 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 23559009 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7020718 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 606128 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1090562 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 996028 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 66487 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 41577642 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 218603 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1090562 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 14092626 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6784553 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14469405 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6963849 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2354603 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 40318960 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2633 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 472928 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1334672 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 351 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40667832 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 182121697 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 182086780 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34917 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31702592 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8965239 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 463825 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 419023 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5696158 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7936117 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5894118 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1139492 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1233570 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 38069002 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 950684 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 38295497 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6802670 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14391567 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 261548 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 45755598 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.836958 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.462966 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 28324155 64.07% 64.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6346765 14.36% 78.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3236431 7.32% 85.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2507997 5.67% 91.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2107881 4.77% 96.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 937016 2.12% 98.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 515116 1.17% 99.47% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 180639 0.41% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53960 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 29855724 65.25% 65.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6336412 13.85% 79.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3245721 7.09% 86.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2523061 5.51% 91.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2111675 4.62% 96.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 936021 2.05% 98.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 511535 1.12% 99.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 181147 0.40% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54302 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 44209960 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 45755598 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27715 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 460 0.04% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27761 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 464 0.04% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available @@ -679,401 +679,401 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 839091 78.45% 81.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 202283 18.91% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 835942 77.99% 80.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207752 19.38% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22968400 60.05% 60.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50115 0.13% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 11 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9563149 25.00% 85.33% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5612341 14.67% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 23003680 60.07% 60.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 50163 0.13% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9567598 24.98% 85.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5620993 14.68% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38247071 # Type of FU issued -system.cpu0.iq.rate 0.576409 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1069549 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.027964 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 121902835 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45721169 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35306324 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8427 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4840 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3930 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39259896 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4380 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 325721 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 38295497 # Type of FU issued +system.cpu0.iq.rate 0.520740 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1071919 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.027991 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 123548516 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45830842 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35351164 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8368 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 39310727 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4345 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 327037 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1504145 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3982 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13879 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 608088 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1508258 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3980 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13847 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 614652 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149487 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5263 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149655 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5288 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1085770 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4069341 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 129560 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39094255 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 87678 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7927385 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5883720 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 614122 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 49261 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17662 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13879 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 160370 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144551 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 304921 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37828601 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9401576 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 418470 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1090562 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4675196 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 127491 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 39158193 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 88903 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7936117 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5894118 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 617815 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 49276 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 17780 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13847 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 160769 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144529 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 305298 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37872918 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9405503 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 422579 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 138219 # number of nop insts executed -system.cpu0.iew.exec_refs 14960222 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5069889 # Number of branches executed -system.cpu0.iew.exec_stores 5558646 # Number of stores executed -system.cpu0.iew.exec_rate 0.570102 # Inst execution rate -system.cpu0.iew.wb_sent 37608832 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35310254 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18670977 # num instructions producing a value -system.cpu0.iew.wb_consumers 35573590 # num instructions consuming a value +system.cpu0.iew.exec_nop 138507 # number of nop insts executed +system.cpu0.iew.exec_refs 14971538 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5077620 # Number of branches executed +system.cpu0.iew.exec_stores 5566035 # Number of stores executed +system.cpu0.iew.exec_rate 0.514994 # Inst execution rate +system.cpu0.iew.wb_sent 37653849 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35355057 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18700837 # num instructions producing a value +system.cpu0.iew.wb_consumers 35658328 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.532149 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.524855 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.480756 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.524445 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 24262280 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 31997725 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6679991 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 688836 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 267429 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 43160582 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.741365 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.695624 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 24280608 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 32020757 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6703968 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 689136 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 267907 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 44701440 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.716325 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.672707 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 31020137 71.87% 71.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6071618 14.07% 85.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1950463 4.52% 90.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1036843 2.40% 92.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 799662 1.85% 94.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 507487 1.18% 95.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 407135 0.94% 96.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 202137 0.47% 97.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1165100 2.70% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 32554343 72.83% 72.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6077315 13.60% 86.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1947893 4.36% 90.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1038743 2.32% 93.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 803562 1.80% 94.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 505193 1.13% 96.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 401469 0.90% 96.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 200976 0.45% 97.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1171946 2.62% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 43160582 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24262280 # Number of instructions committed -system.cpu0.commit.committedOps 31997725 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 44701440 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24280608 # Number of instructions committed +system.cpu0.commit.committedOps 32020757 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11698872 # Number of memory references committed -system.cpu0.commit.loads 6423240 # Number of loads committed -system.cpu0.commit.membars 234547 # Number of memory barriers committed -system.cpu0.commit.branches 4415502 # Number of branches committed +system.cpu0.commit.refs 11707325 # Number of memory references committed +system.cpu0.commit.loads 6427859 # Number of loads committed +system.cpu0.commit.membars 234599 # Number of memory barriers committed +system.cpu0.commit.branches 4418672 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28265931 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499946 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1165100 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28286546 # Number of committed integer instructions. +system.cpu0.commit.function_calls 500309 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1171946 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 79788976 # The number of ROB reads -system.cpu0.rob.rob_writes 78443760 # The number of ROB writes -system.cpu0.timesIdled 426851 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 22144095 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5098222727 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24181538 # Number of Instructions Simulated -system.cpu0.committedOps 31916983 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24181538 # Number of Instructions Simulated -system.cpu0.cpi 2.743996 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.743996 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.364432 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.364432 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176533858 # number of integer regfile reads -system.cpu0.int_regfile_writes 35079827 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3404 # number of floating regfile reads -system.cpu0.fp_regfile_writes 942 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47584444 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527516 # number of misc regfile writes -system.cpu0.icache.replacements 406873 # number of replacements -system.cpu0.icache.tagsinuse 511.614484 # Cycle average of tags in use -system.cpu0.icache.total_refs 3975135 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 407385 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.757686 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6470209000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.614484 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999247 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999247 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3975135 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3975135 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3975135 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3975135 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3975135 # number of overall hits -system.cpu0.icache.overall_hits::total 3975135 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 441500 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 441500 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 441500 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 441500 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 441500 # number of overall misses -system.cpu0.icache.overall_misses::total 441500 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7129067996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7129067996 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7129067996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7129067996 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7129067996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7129067996 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4416635 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4416635 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4416635 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4416635 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4416635 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4416635 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099963 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099963 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099963 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099963 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099963 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099963 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16147.379379 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16147.379379 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16147.379379 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16147.379379 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16147.379379 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16147.379379 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1348496 # number of cycles access was blocked +system.cpu0.rob.rob_reads 81369547 # The number of ROB reads +system.cpu0.rob.rob_writes 78542452 # The number of ROB writes +system.cpu0.timesIdled 427204 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27784943 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5160481977 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24199866 # Number of Instructions Simulated +system.cpu0.committedOps 31940015 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24199866 # Number of Instructions Simulated +system.cpu0.cpi 3.038882 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.038882 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.329068 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.329068 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 176731885 # number of integer regfile reads +system.cpu0.int_regfile_writes 35129220 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3381 # number of floating regfile reads +system.cpu0.fp_regfile_writes 940 # number of floating regfile writes +system.cpu0.misc_regfile_reads 47656068 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527809 # number of misc regfile writes +system.cpu0.icache.replacements 407270 # number of replacements +system.cpu0.icache.tagsinuse 511.577657 # Cycle average of tags in use +system.cpu0.icache.total_refs 3982592 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 407782 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.766473 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 7275068000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.577657 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3982592 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3982592 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3982592 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3982592 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3982592 # number of overall hits +system.cpu0.icache.overall_hits::total 3982592 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 441782 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 441782 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 441782 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 441782 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 441782 # number of overall misses +system.cpu0.icache.overall_misses::total 441782 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7132710997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7132710997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7132710997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7132710997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7132710997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7132710997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4424374 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4424374 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4424374 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4424374 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4424374 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4424374 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099852 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.099852 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099852 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.099852 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099852 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.099852 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16145.318272 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16145.318272 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16145.318272 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16145.318272 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1383498 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 169 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8074.826347 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8186.378698 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 34106 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 34106 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 34106 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 34106 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 34106 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 34106 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407394 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 407394 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 407394 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 407394 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 407394 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 407394 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5468654996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5468654996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5468654996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5468654996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5468654996 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5468654996 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33988 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 33988 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 33988 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 33988 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 33988 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 33988 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407794 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 407794 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 407794 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 407794 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 407794 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 407794 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5471235499 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5471235499 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5471235499 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5471235499 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5471235499 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5471235499 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092241 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.092241 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.092241 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13423.504018 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13423.504018 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13423.504018 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092170 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.092170 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.092170 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13416.665029 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13416.665029 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13416.665029 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275592 # number of replacements -system.cpu0.dcache.tagsinuse 476.837382 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9554493 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276104 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.604689 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 275687 # number of replacements +system.cpu0.dcache.tagsinuse 476.019935 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9558592 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276199 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.607627 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.837382 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.931323 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.931323 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5935954 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5935954 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3226635 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3226635 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174405 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174405 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171548 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171548 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9162589 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9162589 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9162589 # number of overall hits -system.cpu0.dcache.overall_hits::total 9162589 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 400527 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 400527 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1594104 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1594104 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8985 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8985 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7776 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7776 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1994631 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1994631 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1994631 # number of overall misses -system.cpu0.dcache.overall_misses::total 1994631 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7261400500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 7261400500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71837415855 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71837415855 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113971500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 113971500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 93410500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 93410500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 79098816355 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 79098816355 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 79098816355 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 79098816355 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6336481 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6336481 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820739 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4820739 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183390 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183390 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179324 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179324 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11157220 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11157220 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11157220 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11157220 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063210 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063210 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330676 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.330676 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048994 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048994 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043363 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043363 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178775 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178775 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18129.615482 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18129.615482 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45064.447398 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45064.447398 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12684.641068 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12684.641068 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12012.667181 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12012.667181 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39655.864345 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39655.864345 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39655.864345 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39655.864345 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7527492 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1548500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1462 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 87 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5148.763338 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 17798.850575 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 476.019935 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.929726 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.929726 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5937166 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5937166 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3229422 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3229422 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174299 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174299 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171559 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171559 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9166588 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9166588 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9166588 # number of overall hits +system.cpu0.dcache.overall_hits::total 9166588 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 401556 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 401556 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1594295 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1594295 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9014 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9014 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7780 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7780 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1995851 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1995851 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1995851 # number of overall misses +system.cpu0.dcache.overall_misses::total 1995851 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7292954000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 7292954000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71657694355 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 71657694355 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113831500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 113831500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90370500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 90370500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 78950648355 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 78950648355 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 78950648355 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 78950648355 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6338722 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6338722 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4823717 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4823717 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183313 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183313 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179339 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 179339 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11162439 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11162439 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11162439 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11162439 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063350 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063350 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330512 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330512 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049173 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049173 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043382 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043382 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178801 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178801 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178801 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178801 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18161.735848 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18161.735848 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44946.320697 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44946.320697 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12628.300422 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12628.300422 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11615.745501 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11615.745501 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39557.385975 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39557.385975 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7317992 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1712000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1467 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 85 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4988.406271 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 20141.176471 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255542 # number of writebacks -system.cpu0.dcache.writebacks::total 255542 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211236 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 211236 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463026 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1463026 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 516 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 516 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1674262 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1674262 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1674262 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1674262 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189291 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189291 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131078 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131078 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8469 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks +system.cpu0.dcache.writebacks::total 255942 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 212150 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 212150 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463164 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1463164 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 530 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 530 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1675314 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1675314 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1675314 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1675314 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189406 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189406 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131131 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131131 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8484 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8484 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7773 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 7773 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320369 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320369 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320369 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320369 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2800937917 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2800937917 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685815512 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685815512 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79569505 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79569505 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 68924555 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 68924555 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320537 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320537 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320537 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320537 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2811014487 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2811014487 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4674099005 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4674099005 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79244002 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79244002 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65918035 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65918035 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7486753429 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7486753429 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7486753429 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7486753429 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315126500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315126500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849486399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849486399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164612899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164612899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029873 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029873 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027190 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027190 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046180 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046180 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043346 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043346 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028714 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028714 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028714 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028714 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14796.994664 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14796.994664 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.298814 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.298814 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9395.383753 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9395.383753 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8867.175479 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8867.175479 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7485113492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7485113492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7485113492 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7485113492 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13455989500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13455989500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1298746899 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1298746899 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14754736399 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14754736399 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029881 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029881 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027185 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027185 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046281 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046281 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043342 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043342 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028716 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028716 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14841.211403 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14841.211403 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35644.500576 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35644.500576 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9340.405705 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9340.405705 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8480.385308 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8480.385308 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23369.156907 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23369.156907 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23369.156907 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23369.156907 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1083,27 +1083,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43445270 # DTB read hits -system.cpu1.dtb.read_misses 46285 # DTB read misses -system.cpu1.dtb.write_hits 7088572 # DTB write hits -system.cpu1.dtb.write_misses 12217 # DTB write misses +system.cpu1.dtb.read_hits 43452334 # DTB read hits +system.cpu1.dtb.read_misses 46277 # DTB read misses +system.cpu1.dtb.write_hits 7091337 # DTB write hits +system.cpu1.dtb.write_misses 12150 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2504 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3688 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.flush_entries 2524 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3762 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 371 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 674 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43491555 # DTB read accesses -system.cpu1.dtb.write_accesses 7100789 # DTB write accesses +system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43498611 # DTB read accesses +system.cpu1.dtb.write_accesses 7103487 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50533842 # DTB hits -system.cpu1.dtb.misses 58502 # DTB misses -system.cpu1.dtb.accesses 50592344 # DTB accesses -system.cpu1.itb.inst_hits 9223213 # ITB inst hits -system.cpu1.itb.inst_misses 6180 # ITB inst misses +system.cpu1.dtb.hits 50543671 # DTB hits +system.cpu1.dtb.misses 58427 # DTB misses +system.cpu1.dtb.accesses 50602098 # DTB accesses +system.cpu1.itb.inst_hits 9232744 # ITB inst hits +system.cpu1.itb.inst_misses 6115 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1112,122 +1112,122 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1615 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1606 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1780 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1727 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9229393 # ITB inst accesses -system.cpu1.itb.hits 9223213 # DTB hits -system.cpu1.itb.misses 6180 # DTB misses -system.cpu1.itb.accesses 9229393 # DTB accesses -system.cpu1.numCycles 355232424 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9238859 # ITB inst accesses +system.cpu1.itb.hits 9232744 # DTB hits +system.cpu1.itb.misses 6115 # DTB misses +system.cpu1.itb.accesses 9238859 # DTB accesses +system.cpu1.numCycles 420389270 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9848764 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 8083275 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 447123 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6868345 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5662939 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9847995 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 8081754 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 448433 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6818773 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5657403 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 832004 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 49676 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 22148379 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 71952458 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9848764 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6494943 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 15333431 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4632908 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 88364 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 74838070 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 63991 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 141562 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 138 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9221022 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 859641 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3677 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 115781579 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.750934 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.109459 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 833939 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 50420 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 22177481 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 71987538 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9847995 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6491342 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 15338669 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4640041 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 86616 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 81067805 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5869 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 63713 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 142087 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9230611 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 860735 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3603 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 122048207 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.712843 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.062128 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100456410 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 829573 0.72% 87.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1015846 0.88% 88.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2061622 1.78% 90.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1645380 1.42% 91.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 616095 0.53% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2274849 1.96% 94.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 467300 0.40% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6414504 5.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 106717875 87.44% 87.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 829211 0.68% 88.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1015415 0.83% 88.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2063306 1.69% 90.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1641471 1.34% 91.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 615009 0.50% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2274741 1.86% 94.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 467540 0.38% 94.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6423639 5.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 115781579 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.027725 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.202550 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23776389 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 74601447 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13781615 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 561009 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3061119 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1241407 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102665 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 81190791 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 341149 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3061119 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 25333003 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33967991 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 36116187 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12703540 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4599739 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 74711209 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 20422 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 719883 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3284162 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33659 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 79078972 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 344223554 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 344164086 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59468 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50180386 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28898586 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 486916 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 421354 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8389500 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14026564 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8607423 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1068694 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1518812 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 67421543 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1209489 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 91958955 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 109721 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18898752 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53543776 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 290002 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 115781579 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.794245 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521941 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 122048207 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.023426 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.171240 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23807304 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 80829213 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13786228 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 560401 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3065061 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1241341 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 102643 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 81234919 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 343119 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3065061 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 25364340 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34010393 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 42304537 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12707018 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4596858 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 74746383 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 20429 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 720817 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3279864 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33412 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 79106997 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 344419030 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 344359691 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59339 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50193146 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28913851 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 487769 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 421850 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8399849 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 14034972 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8614706 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1072487 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1529720 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 67446295 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1206628 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 91979521 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 109681 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18910261 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53596675 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 286825 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 122048207 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.753633 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.492572 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83973534 72.53% 72.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9124499 7.88% 80.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4576997 3.95% 84.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4009566 3.46% 87.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10699106 9.24% 97.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1974757 1.71% 98.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1060771 0.92% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 281863 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 80486 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 90230410 73.93% 73.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9124502 7.48% 81.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4577298 3.75% 85.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4017634 3.29% 88.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10703333 8.77% 97.22% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1977632 1.62% 98.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1055737 0.87% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 281681 0.23% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 79980 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 115781579 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 122048207 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29310 0.37% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 993 0.01% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 28913 0.37% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 998 0.01% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available @@ -1255,13 +1255,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7573445 95.84% 96.23% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 298199 3.77% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7574685 95.84% 96.22% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 298874 3.78% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 39470238 42.92% 43.26% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61477 0.07% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 39479578 42.92% 43.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61492 0.07% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.33% # Type of FU issued @@ -1274,378 +1274,382 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.33% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1690 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1697 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.33% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44643108 48.55% 91.88% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7468676 8.12% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44651207 48.54% 91.88% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7471778 8.12% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 91958955 # Type of FU issued -system.cpu1.iq.rate 0.258870 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7901947 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.085929 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 307754751 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 87542996 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 55769663 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14772 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8137 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6817 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 99539441 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7724 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 371642 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 91979521 # Type of FU issued +system.cpu1.iq.rate 0.218796 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7903470 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.085926 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 314063875 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 87576510 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 55784562 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14814 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8109 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 99561488 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7766 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 369403 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4037130 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6814 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 21954 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1589436 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4042367 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6847 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 22042 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1594624 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965709 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1043610 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965742 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1047944 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3061119 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25601852 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 406330 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 68756671 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 131432 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14026564 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8607423 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 899609 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 81519 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 7124 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 21954 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 226065 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 196785 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 422850 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 89098857 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43830249 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2860098 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3065061 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25634357 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 409319 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 68777683 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 134755 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 14034972 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8614706 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 896270 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 80399 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 14951 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 22042 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 226446 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 198201 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 424647 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 89117462 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43838045 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2862059 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 125639 # number of nop insts executed -system.cpu1.iew.exec_refs 51224079 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7396455 # Number of branches executed -system.cpu1.iew.exec_stores 7393830 # Number of stores executed -system.cpu1.iew.exec_rate 0.250818 # Inst execution rate -system.cpu1.iew.wb_sent 87931251 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 55776480 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30792122 # num instructions producing a value -system.cpu1.iew.wb_consumers 54566321 # num instructions consuming a value +system.cpu1.iew.exec_nop 124760 # number of nop insts executed +system.cpu1.iew.exec_refs 51234744 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7395685 # Number of branches executed +system.cpu1.iew.exec_stores 7396699 # Number of stores executed +system.cpu1.iew.exec_rate 0.211988 # Inst execution rate +system.cpu1.iew.wb_sent 87946957 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 55791363 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30796912 # num instructions producing a value +system.cpu1.iew.wb_consumers 54575062 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.157014 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.564306 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.132714 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.564304 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38938347 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 49298719 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 19014978 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 919487 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 376070 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112768879 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.437166 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.403258 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38947564 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 49311547 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 19037243 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 919803 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 377326 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 119031582 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.414273 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.369590 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95484340 84.67% 84.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8537208 7.57% 92.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2210726 1.96% 94.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1312266 1.16% 95.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1283048 1.14% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 588048 0.52% 97.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1003635 0.89% 97.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 487845 0.43% 98.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1861763 1.65% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 101746657 85.48% 85.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8535054 7.17% 92.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2209116 1.86% 94.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1312161 1.10% 95.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1288209 1.08% 96.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 590684 0.50% 97.19% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 998098 0.84% 98.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 485890 0.41% 98.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1865713 1.57% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112768879 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38938347 # Number of instructions committed -system.cpu1.commit.committedOps 49298719 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 119031582 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38947564 # Number of instructions committed +system.cpu1.commit.committedOps 49311547 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17007421 # Number of memory references committed -system.cpu1.commit.loads 9989434 # Number of loads committed -system.cpu1.commit.membars 202281 # Number of memory barriers committed -system.cpu1.commit.branches 6220621 # Number of branches committed +system.cpu1.commit.refs 17012687 # Number of memory references committed +system.cpu1.commit.loads 9992605 # Number of loads committed +system.cpu1.commit.membars 202357 # Number of memory barriers committed +system.cpu1.commit.branches 6222202 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43690243 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556165 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1861763 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43701968 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556417 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1865713 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 178106600 # The number of ROB reads -system.cpu1.rob.rob_writes 139781050 # The number of ROB writes -system.cpu1.timesIdled 1519184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 239450845 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4808685831 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38868708 # Number of Instructions Simulated -system.cpu1.committedOps 49229080 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38868708 # Number of Instructions Simulated -system.cpu1.cpi 9.139291 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 9.139291 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.109418 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.109418 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 398713179 # number of integer regfile reads -system.cpu1.int_regfile_writes 58485097 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4918 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2338 # number of floating regfile writes -system.cpu1.misc_regfile_reads 91819776 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429481 # number of misc regfile writes -system.cpu1.icache.replacements 621812 # number of replacements -system.cpu1.icache.tagsinuse 498.762593 # Cycle average of tags in use -system.cpu1.icache.total_refs 8548797 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 622324 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.736891 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74633258000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.762593 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974146 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974146 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8548797 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8548797 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8548797 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8548797 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8548797 # number of overall hits -system.cpu1.icache.overall_hits::total 8548797 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 672174 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 672174 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 672174 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 672174 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 672174 # number of overall misses -system.cpu1.icache.overall_misses::total 672174 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10613540997 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10613540997 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10613540997 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10613540997 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10613540997 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10613540997 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9220971 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9220971 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9220971 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9220971 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9220971 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9220971 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072896 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.072896 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072896 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.072896 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072896 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.072896 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15789.871368 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15789.871368 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15789.871368 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15789.871368 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15789.871368 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15789.871368 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1180997 # number of cycles access was blocked +system.cpu1.rob.rob_reads 184400014 # The number of ROB reads +system.cpu1.rob.rob_writes 139856425 # The number of ROB writes +system.cpu1.timesIdled 1519588 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 298341063 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4812976632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38877925 # Number of Instructions Simulated +system.cpu1.committedOps 49241908 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38877925 # Number of Instructions Simulated +system.cpu1.cpi 10.813058 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.813058 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092481 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092481 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 398800057 # number of integer regfile reads +system.cpu1.int_regfile_writes 58498146 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4943 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2344 # number of floating regfile writes +system.cpu1.misc_regfile_reads 91875872 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429758 # number of misc regfile writes +system.cpu1.icache.replacements 623101 # number of replacements +system.cpu1.icache.tagsinuse 498.730815 # Cycle average of tags in use +system.cpu1.icache.total_refs 8556871 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 623613 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.721444 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 75785780000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.730815 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974084 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974084 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8556871 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8556871 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8556871 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8556871 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8556871 # number of overall hits +system.cpu1.icache.overall_hits::total 8556871 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 673686 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 673686 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 673686 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 673686 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 673686 # number of overall misses +system.cpu1.icache.overall_misses::total 673686 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10642693998 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10642693998 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10642693998 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10642693998 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10642693998 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10642693998 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 9230557 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 9230557 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 9230557 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 9230557 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 9230557 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 9230557 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072984 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.072984 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072984 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.072984 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072984 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.072984 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15797.706941 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15797.706941 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15797.706941 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15797.706941 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1133998 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 198 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 174 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 5964.631313 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6517.229885 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49820 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 49820 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 49820 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 49820 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 49820 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 49820 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622354 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 622354 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 622354 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 622354 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 622354 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 622354 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8128418498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8128418498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8128418498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8128418498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8128418498 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8128418498 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3154000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3154000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3154000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3154000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067493 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.067493 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.067493 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13060.763646 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13060.763646 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13060.763646 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50044 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 50044 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 50044 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 50044 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 50044 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 50044 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623642 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 623642 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 623642 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 623642 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 623642 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 623642 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8149352498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8149352498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8149352498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8149352498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8149352498 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8149352498 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3211500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3211500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3211500 # 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average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 362958 # number of replacements -system.cpu1.dcache.tagsinuse 487.094495 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13107479 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 363304 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.078543 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70482639000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.094495 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951356 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951356 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8608268 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8608268 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4252418 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4252418 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 106100 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 106100 # 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number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10905 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 2006234 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 2006234 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 2006234 # number of overall misses -system.cpu1.dcache.overall_misses::total 2006234 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8133768000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8133768000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66485489237 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 66485489237 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 165213500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 165213500 # 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miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118199 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118199 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097698 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097698 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134946 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.134946 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134946 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134946 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19808.745418 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19808.745418 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41667.521656 # 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number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5620000 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6671 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 172 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4418.530205 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 32674.418605 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 363581 # number of replacements +system.cpu1.dcache.tagsinuse 487.223522 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13117187 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 363929 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.043258 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 71474573000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.223522 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951608 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951608 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8616147 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8616147 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4254446 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4254446 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105790 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 105790 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100736 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 100736 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12870593 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12870593 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12870593 # number of overall hits +system.cpu1.dcache.overall_hits::total 12870593 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 410065 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 410065 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1595508 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1595508 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10912 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10912 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2005573 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2005573 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2005573 # number of overall misses +system.cpu1.dcache.overall_misses::total 2005573 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8126055000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8126055000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66044305227 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 66044305227 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166791500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 166791500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 95304000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 95304000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 74170360227 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 74170360227 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 74170360227 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 74170360227 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9026212 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9026212 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5849954 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5849954 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120068 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 120068 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111648 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 111648 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14876166 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14876166 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14876166 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14876166 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045430 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045430 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272739 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.272739 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118916 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118916 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097736 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097736 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134818 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134818 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134818 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134818 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19816.504700 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19816.504700 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41393.904153 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41393.904153 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11681.713125 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11681.713125 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8733.870968 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8733.870968 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 36982.129410 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 36982.129410 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29670016 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5568500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6658 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 173 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4456.295584 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 32187.861272 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327729 # number of writebacks -system.cpu1.dcache.writebacks::total 327729 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179332 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 179332 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432824 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1432824 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1612156 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1612156 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1612156 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1612156 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231283 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231283 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162795 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162795 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10900 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10900 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394078 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394078 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394078 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394078 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3556387454 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3556387454 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5557887685 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5557887685 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 103446504 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 103446504 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60421505 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60421505 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9114275139 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9114275139 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9114275139 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9114275139 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004022500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004022500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40580989302 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40580989302 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177585011802 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177585011802 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025644 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025644 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027838 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027838 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106173 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106173 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097654 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097654 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026507 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026507 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15376.778466 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15376.778466 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34140.407783 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34140.407783 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8097.573699 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8097.573699 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5543.257339 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5543.257339 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23128.099359 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23128.099359 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23128.099359 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23128.099359 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 328251 # number of writebacks +system.cpu1.dcache.writebacks::total 328251 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178277 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 178277 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432587 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1432587 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1464 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1464 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1610864 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1610864 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1610864 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1610864 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231788 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231788 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162921 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162921 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12814 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12814 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394709 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394709 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394709 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394709 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3566201462 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3566201462 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5537603585 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5537603585 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104573506 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104573506 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61265506 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61265506 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9103805047 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9103805047 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9103805047 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9103805047 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169309741500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169309741500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40933880282 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40933880282 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210243621782 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210243621782 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025679 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025679 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027850 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027850 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106723 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106723 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097709 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097709 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026533 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026533 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15385.617297 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15385.617297 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33989.501568 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33989.501568 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8160.879195 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8160.879195 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5616.051517 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5616.051517 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1667,18 +1671,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305599683923 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1305599683923 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305599683923 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1305599683923 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323189312111 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323189312111 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43782 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43824 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53899 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b903804f3..bc845639a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,209 +1,209 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503329 # Number of seconds simulated -sim_ticks 2503329223500 # Number of ticks simulated -final_tick 2503329223500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.538055 # Number of seconds simulated +sim_ticks 2538055224500 # Number of ticks simulated +final_tick 2538055224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62297 # Simulator instruction rate (inst/s) -host_op_rate 80132 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2573650165 # Simulator tick rate (ticks/s) -host_mem_usage 394796 # Number of bytes of host memory used -host_seconds 972.68 # Real time elapsed on the host -sim_insts 60594713 # Number of instructions simulated -sim_ops 77942287 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory +host_inst_rate 88262 # Simulator instruction rate (inst/s) +host_op_rate 113532 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3696075323 # Simulator tick rate (ticks/s) +host_mem_usage 390228 # Number of bytes of host memory used +host_seconds 686.69 # Real time elapsed on the host +sim_insts 60608338 # Number of instructions simulated +sim_ops 77960937 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory -system.physmem.bytes_read::total 129435024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9090192 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3781888 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6797960 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12493 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096888 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12492 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142068 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293438 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59092 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47751475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 319395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3632775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51705154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 319395 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319395 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1512073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1204824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2716897 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1512073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47751475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 319395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4837599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54422052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813110 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47717846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3581558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51615968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1490073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188340 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2678413 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1490073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47717846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4769898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54294380 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 26 # 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average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40966.138456 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40966.138456 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41080.219877 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40930.159396 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40941.772131 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41080.219877 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40930.159396 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40941.772131 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,27 +332,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51771178 # DTB read hits -system.cpu.dtb.read_misses 82022 # DTB read misses -system.cpu.dtb.write_hits 11879780 # DTB write hits -system.cpu.dtb.write_misses 18404 # DTB write misses +system.cpu.dtb.read_hits 51779226 # DTB read hits +system.cpu.dtb.read_misses 81574 # DTB read misses +system.cpu.dtb.write_hits 11882622 # DTB write hits +system.cpu.dtb.write_misses 18093 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4476 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2874 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 631 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4488 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3293 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 606 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1260 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51853200 # DTB read accesses -system.cpu.dtb.write_accesses 11898184 # DTB write accesses +system.cpu.dtb.perms_faults 1237 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51860800 # DTB read accesses +system.cpu.dtb.write_accesses 11900715 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63650958 # DTB hits -system.cpu.dtb.misses 100426 # DTB misses -system.cpu.dtb.accesses 63751384 # DTB accesses -system.cpu.itb.inst_hits 13147400 # ITB inst hits -system.cpu.itb.inst_misses 12275 # ITB inst misses +system.cpu.dtb.hits 63661848 # DTB hits +system.cpu.dtb.misses 99667 # DTB misses +system.cpu.dtb.accesses 63761515 # DTB accesses +system.cpu.itb.inst_hits 13144692 # ITB inst hits +system.cpu.itb.inst_misses 11967 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -361,121 +361,121 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2641 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2632 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3416 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13159675 # ITB inst accesses -system.cpu.itb.hits 13147400 # DTB hits -system.cpu.itb.misses 12275 # DTB misses -system.cpu.itb.accesses 13159675 # DTB accesses -system.cpu.numCycles 415310668 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13156659 # ITB inst accesses +system.cpu.itb.hits 13144692 # DTB hits +system.cpu.itb.misses 11967 # DTB misses +system.cpu.itb.accesses 13156659 # DTB accesses +system.cpu.numCycles 487285069 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15527738 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12466555 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753811 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10646284 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8367014 # Number of BTB hits +system.cpu.BPredUnit.lookups 15533008 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12472748 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 753945 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10621013 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8369898 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1449693 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80905 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33357472 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101736318 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15527738 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9816707 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22310929 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6078281 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 161634 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94635812 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2484 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 132549 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208778 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 375 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13143214 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1025665 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6564 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154991090 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.809239 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.178893 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1450891 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 81082 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33390116 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101781554 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15533008 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9820789 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22319812 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6080499 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 158808 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102222011 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133571 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 207903 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13140422 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1021772 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6316 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162617823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.771724 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.134680 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132697054 85.62% 85.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1371702 0.89% 86.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1758298 1.13% 87.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2653739 1.71% 89.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2357523 1.52% 90.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1143564 0.74% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2918516 1.88% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 809258 0.52% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9281436 5.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140314971 86.29% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1367844 0.84% 87.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1761669 1.08% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2653320 1.63% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2361626 1.45% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1142802 0.70% 92.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2916048 1.79% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 808288 0.50% 94.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9291255 5.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154991090 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.037388 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.244964 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35540110 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94304374 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20024957 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1112327 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4009322 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100739 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174603 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118268322 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 570412 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4009322 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37657945 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39869078 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47822984 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18880557 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6751204 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110681454 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22988 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1160036 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4497834 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31020 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115504222 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 506609726 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506516210 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93516 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727449 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36776772 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 900485 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 799637 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13564830 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21065339 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13879000 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1961867 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2663971 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101316574 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2057711 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126458108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 199553 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24657438 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65563204 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 513311 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154991090 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.815906 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.514046 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162617823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031877 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208875 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35567426 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101892214 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20037549 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1109983 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4010651 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2100654 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174914 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118316762 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572114 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4010651 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37681511 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40491658 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54797467 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18895098 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6741438 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110776004 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22866 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1160313 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4487001 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30716 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115615239 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 507028919 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506935731 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 93188 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78747197 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36868041 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898954 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797959 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13563069 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21067127 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13877132 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1956196 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2590406 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101357427 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059773 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126494913 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 198538 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24680718 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65543860 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514575 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162617823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.777866 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488052 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108868078 70.24% 70.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14887887 9.61% 79.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7383585 4.76% 84.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6313472 4.07% 88.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12622401 8.14% 96.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2812506 1.81% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1537255 0.99% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 440277 0.28% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125629 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116473756 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14895850 9.16% 80.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7383355 4.54% 85.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6325930 3.89% 89.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12628751 7.77% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2810327 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536412 0.94% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438084 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125358 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154991090 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162617823 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 54148 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53829 0.61% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available @@ -504,397 +504,397 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8364176 94.75% 95.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 409089 4.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366722 94.73% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411335 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60068751 47.50% 47.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95236 0.08% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53417106 42.24% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12511205 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60100692 47.51% 47.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95407 0.08% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53419362 42.23% 90.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12513627 9.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126458108 # Type of FU issued -system.cpu.iq.rate 0.304490 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8827417 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069805 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417011386 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128052835 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87416470 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22950 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12920 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10331 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134909754 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12105 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 645788 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126494913 # Type of FU issued +system.cpu.iq.rate 0.259591 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8831890 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069820 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 424714403 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128119104 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87467949 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22973 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12866 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10326 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134951003 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12134 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 645792 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5350138 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11136 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35101 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2080838 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5347388 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11096 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35111 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2076739 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107263 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1048290 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107215 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052024 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4009322 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29478613 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 536036 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103628902 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 217385 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21065339 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13879000 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1466402 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126510 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 31155 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35101 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376939 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332400 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709339 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123236608 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52461044 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3221500 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4010651 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30083339 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540488 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103672693 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 219471 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21067127 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13877132 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1468075 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126042 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 41068 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35111 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 376458 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332668 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 709126 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123289616 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52469824 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3205297 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 254617 # number of nop insts executed -system.cpu.iew.exec_refs 64851969 # number of memory reference insts executed -system.cpu.iew.exec_branches 11926568 # Number of branches executed -system.cpu.iew.exec_stores 12390925 # Number of stores executed -system.cpu.iew.exec_rate 0.296734 # Inst execution rate -system.cpu.iew.wb_sent 121860265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87426801 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47494075 # num instructions producing a value -system.cpu.iew.wb_consumers 86379183 # num instructions consuming a value +system.cpu.iew.exec_nop 255493 # number of nop insts executed +system.cpu.iew.exec_refs 64863659 # number of memory reference insts executed +system.cpu.iew.exec_branches 11931891 # Number of branches executed +system.cpu.iew.exec_stores 12393835 # Number of stores executed +system.cpu.iew.exec_rate 0.253013 # Inst execution rate +system.cpu.iew.wb_sent 121912605 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87478275 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47524907 # num instructions producing a value +system.cpu.iew.wb_consumers 86445005 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.210509 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549832 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179522 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549770 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 60745094 # The number of committed instructions -system.cpu.commit.commitCommittedOps 78092668 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24728606 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544400 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625654 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151064180 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.516950 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.491641 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 60758719 # The number of committed instructions +system.cpu.commit.commitCommittedOps 78111318 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24740610 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545198 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625619 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158689613 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492227 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459221 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122872114 81.34% 81.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13991345 9.26% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3943128 2.61% 93.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2231050 1.48% 94.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2009345 1.33% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1063949 0.70% 96.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402638 0.93% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 655924 0.43% 98.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2894687 1.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130476861 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14004142 8.82% 91.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3942589 2.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2238161 1.41% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2017118 1.27% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1061710 0.67% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402075 0.88% 97.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657613 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889344 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151064180 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60745094 # Number of instructions committed -system.cpu.commit.committedOps 78092668 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158689613 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60758719 # Number of instructions committed +system.cpu.commit.committedOps 78111318 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513363 # Number of memory references committed -system.cpu.commit.loads 15715201 # Number of loads committed -system.cpu.commit.membars 413054 # Number of memory barriers committed -system.cpu.commit.branches 10161447 # Number of branches committed +system.cpu.commit.refs 27520132 # Number of memory references committed +system.cpu.commit.loads 15719739 # Number of loads committed +system.cpu.commit.membars 413350 # Number of memory barriers committed +system.cpu.commit.branches 10163894 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69131310 # Number of committed integer instructions. -system.cpu.commit.function_calls 995952 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2894687 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69148099 # Number of committed integer instructions. +system.cpu.commit.function_calls 996264 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889344 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 249075594 # The number of ROB reads -system.cpu.rob.rob_writes 209750294 # The number of ROB writes -system.cpu.timesIdled 1905944 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260319578 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591259733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60594713 # Number of Instructions Simulated -system.cpu.committedOps 77942287 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60594713 # Number of Instructions Simulated -system.cpu.cpi 6.853909 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.853909 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145902 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.145902 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 557815348 # number of integer regfile reads -system.cpu.int_regfile_writes 90098492 # number of integer regfile writes -system.cpu.fp_regfile_reads 8218 # number of floating regfile reads -system.cpu.fp_regfile_writes 2870 # number of floating regfile writes -system.cpu.misc_regfile_reads 134021846 # number of misc regfile reads -system.cpu.misc_regfile_writes 912706 # number of misc regfile writes -system.cpu.icache.replacements 989908 # number of replacements -system.cpu.icache.tagsinuse 511.610984 # Cycle average of tags in use -system.cpu.icache.total_refs 12068184 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990420 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.184915 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6426400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.610984 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999240 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999240 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12068184 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12068184 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12068184 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12068184 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12068184 # number of overall hits -system.cpu.icache.overall_hits::total 12068184 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1074896 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1074896 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1074896 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1074896 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1074896 # number of overall misses -system.cpu.icache.overall_misses::total 1074896 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16638687991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16638687991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16638687991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16638687991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16638687991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16638687991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13143080 # 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Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60608338 # Number of Instructions Simulated +system.cpu.committedOps 77960937 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60608338 # Number of Instructions Simulated +system.cpu.cpi 8.039902 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.039902 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124380 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124380 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 558055785 # number of integer regfile reads +system.cpu.int_regfile_writes 90157820 # number of integer regfile writes +system.cpu.fp_regfile_reads 8288 # number of floating regfile reads +system.cpu.fp_regfile_writes 2908 # number of floating regfile writes +system.cpu.misc_regfile_reads 134082325 # number of misc regfile reads +system.cpu.misc_regfile_writes 913357 # number of misc regfile writes +system.cpu.icache.replacements 991945 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12623481992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12623481992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84824 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84824 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84824 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84824 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84824 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84824 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992495 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 992495 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 992495 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 992495 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 992495 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 992495 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12649346990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12649346990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12649346990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12649346990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12649346990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12649346990 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075360 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075360 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075360 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.082827 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.082827 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.082827 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.082827 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.082827 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.082827 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075531 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075531 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075531 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12744.998202 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12744.998202 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643258 # number of replacements -system.cpu.dcache.tagsinuse 511.991338 # Cycle average of tags in use -system.cpu.dcache.total_refs 21734239 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643770 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.760876 # Average number of references to valid blocks. +system.cpu.dcache.replacements 644089 # number of replacements +system.cpu.dcache.tagsinuse 511.991456 # Cycle average of tags in use +system.cpu.dcache.total_refs 21738846 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644601 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.724499 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991338 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.991456 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13902749 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13902749 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7257426 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7257426 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 285261 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 285261 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285646 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285646 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21160175 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21160175 # 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miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150874 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19418.259614 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19418.259614 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43172.529355 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43172.529355 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16206.184820 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16206.184820 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21157.894737 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21157.894737 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38328.596755 # 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number of writebacks -system.cpu.dcache.writebacks::total 607519 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379422 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 379422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744177 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744177 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1481 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1481 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3123599 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3123599 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3123599 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3123599 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385632 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224322480914 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224322480914 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041603 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041603 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # 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average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17789.473684 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17789.473684 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24416.536543 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24416.536543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24416.536543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24416.536543 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -916,16 +916,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305424568773 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1305424568773 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305424568773 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1305424568773 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323890643510 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88047 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88043 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |