diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
| commit | 6489598fb449531c34bfb25a52189196ee2b1086 (patch) | |
| tree | 5f8bb88862ffd187cb7b182f4a0d20599b4409bf /tests/long/fs/10.linux-boot/ref/arm | |
| parent | 966c3f4bc5581347a411c25db1440afb97f12dab (diff) | |
| download | gem5-6489598fb449531c34bfb25a52189196ee2b1086.tar.xz | |
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
16 files changed, 27072 insertions, 26361 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 405fa6e98..9cf124dc2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,157 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.843655 # Number of seconds simulated -sim_ticks 2843654861000 # Number of ticks simulated -final_tick 2843654861000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.844427 # Number of seconds simulated +sim_ticks 2844427140500 # Number of ticks simulated +final_tick 2844427140500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157498 # Simulator instruction rate (inst/s) -host_op_rate 190690 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3581426538 # Simulator tick rate (ticks/s) -host_mem_usage 613612 # Number of bytes of host memory used -host_seconds 794.00 # Real time elapsed on the host -sim_insts 125053138 # Number of instructions simulated -sim_ops 151407658 # Number of ops (including micro ops) simulated +host_inst_rate 150296 # Simulator instruction rate (inst/s) +host_op_rate 181972 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3416553864 # Simulator tick rate (ticks/s) +host_mem_usage 612172 # Number of bytes of host memory used +host_seconds 832.54 # Real time elapsed on the host +sim_insts 125127935 # Number of instructions simulated +sim_ops 151499394 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 10304 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1363068 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10771008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 534304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1165248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1349820 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10836800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 503456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1120064 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 13845276 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 418688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 26560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 445248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7176128 # Number of bytes written to this memory +system.physmem.bytes_read::total 13821980 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 416640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 27264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 443904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9404288 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 9512208 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 9422032 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 161 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 21823 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 168297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 8372 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 18207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 21616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 169325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7890 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 17501 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 216881 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 112127 # Number of write requests responded to by this memory +system.physmem.num_reads::total 216517 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 146942 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 152787 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3398 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 151378 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3623 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 479337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3787734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 187893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 409771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 474549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3809836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 176997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 393775 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4868831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 147236 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 9340 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2523558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4859319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 146476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 9585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3306215 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 6224 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 815266 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3345064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2523558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3312453 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3306215 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 485562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3787734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 187907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 409771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 815604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8213896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 216881 # Number of read requests accepted -system.physmem.writeReqs 152787 # Number of write requests accepted -system.physmem.readBursts 216881 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 152787 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13864960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 15424 # Total number of bytes read from write queue -system.physmem.bytesWritten 9526912 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 13845276 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9512208 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 241 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13516 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 13445 # Per bank write bursts -system.physmem.perBankRdBursts::1 13090 # Per bank write bursts -system.physmem.perBankRdBursts::2 14400 # Per bank write bursts -system.physmem.perBankRdBursts::3 13760 # Per bank write bursts -system.physmem.perBankRdBursts::4 15799 # Per bank write bursts -system.physmem.perBankRdBursts::5 12812 # Per bank write bursts -system.physmem.perBankRdBursts::6 13576 # Per bank write bursts -system.physmem.perBankRdBursts::7 13750 # Per bank write bursts -system.physmem.perBankRdBursts::8 13572 # Per bank write bursts -system.physmem.perBankRdBursts::9 13600 # Per bank write bursts -system.physmem.perBankRdBursts::10 13300 # Per bank write bursts -system.physmem.perBankRdBursts::11 11904 # Per bank write bursts -system.physmem.perBankRdBursts::12 13370 # Per bank write bursts -system.physmem.perBankRdBursts::13 13720 # Per bank write bursts -system.physmem.perBankRdBursts::14 13497 # Per bank write bursts -system.physmem.perBankRdBursts::15 13045 # Per bank write bursts -system.physmem.perBankWrBursts::0 9322 # Per bank write bursts -system.physmem.perBankWrBursts::1 9428 # Per bank write bursts -system.physmem.perBankWrBursts::2 10143 # Per bank write bursts -system.physmem.perBankWrBursts::3 9576 # Per bank write bursts -system.physmem.perBankWrBursts::4 8974 # Per bank write bursts -system.physmem.perBankWrBursts::5 8900 # Per bank write bursts -system.physmem.perBankWrBursts::6 9376 # Per bank write bursts -system.physmem.perBankWrBursts::7 9386 # Per bank write bursts -system.physmem.perBankWrBursts::8 9384 # Per bank write bursts -system.physmem.perBankWrBursts::9 9431 # Per bank write bursts -system.physmem.perBankWrBursts::10 9355 # Per bank write bursts -system.physmem.perBankWrBursts::11 8834 # Per bank write bursts -system.physmem.perBankWrBursts::12 9379 # Per bank write bursts -system.physmem.perBankWrBursts::13 9206 # Per bank write bursts -system.physmem.perBankWrBursts::14 9289 # Per bank write bursts -system.physmem.perBankWrBursts::15 8875 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 480773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3809836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 177011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 393775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8171773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 216517 # Number of read requests accepted +system.physmem.writeReqs 187602 # Number of write requests accepted +system.physmem.readBursts 216517 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 187602 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13846784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue +system.physmem.bytesWritten 11642944 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 13821980 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11740368 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5664 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13644 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 13513 # Per bank write bursts +system.physmem.perBankRdBursts::1 13311 # Per bank write bursts +system.physmem.perBankRdBursts::2 14548 # Per bank write bursts +system.physmem.perBankRdBursts::3 14027 # Per bank write bursts +system.physmem.perBankRdBursts::4 15548 # Per bank write bursts +system.physmem.perBankRdBursts::5 13123 # Per bank write bursts +system.physmem.perBankRdBursts::6 13508 # Per bank write bursts +system.physmem.perBankRdBursts::7 14039 # Per bank write bursts +system.physmem.perBankRdBursts::8 13183 # Per bank write bursts +system.physmem.perBankRdBursts::9 13181 # Per bank write bursts +system.physmem.perBankRdBursts::10 13142 # Per bank write bursts +system.physmem.perBankRdBursts::11 11743 # Per bank write bursts +system.physmem.perBankRdBursts::12 13238 # Per bank write bursts +system.physmem.perBankRdBursts::13 14181 # Per bank write bursts +system.physmem.perBankRdBursts::14 13272 # Per bank write bursts +system.physmem.perBankRdBursts::15 12799 # Per bank write bursts +system.physmem.perBankWrBursts::0 11429 # Per bank write bursts +system.physmem.perBankWrBursts::1 11725 # Per bank write bursts +system.physmem.perBankWrBursts::2 12190 # Per bank write bursts +system.physmem.perBankWrBursts::3 11854 # Per bank write bursts +system.physmem.perBankWrBursts::4 10909 # Per bank write bursts +system.physmem.perBankWrBursts::5 11199 # Per bank write bursts +system.physmem.perBankWrBursts::6 11528 # Per bank write bursts +system.physmem.perBankWrBursts::7 11643 # Per bank write bursts +system.physmem.perBankWrBursts::8 11026 # Per bank write bursts +system.physmem.perBankWrBursts::9 11436 # Per bank write bursts +system.physmem.perBankWrBursts::10 11468 # Per bank write bursts +system.physmem.perBankWrBursts::11 11022 # Per bank write bursts +system.physmem.perBankWrBursts::12 11525 # Per bank write bursts +system.physmem.perBankWrBursts::13 11398 # Per bank write bursts +system.physmem.perBankWrBursts::14 10974 # Per bank write bursts +system.physmem.perBankWrBursts::15 10595 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2843652584000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2844424796500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 216294 # Read request sizes (log2) +system.physmem.readPktSize::6 215930 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148351 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 79253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 7490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 425 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 183166 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 7427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6415 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -179,156 +176,173 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12070 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92618 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 252.562223 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.207145 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.469960 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46921 50.66% 50.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18876 20.38% 71.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6855 7.40% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3600 3.89% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3008 3.25% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2120 2.29% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1341 1.45% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1115 1.20% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8782 9.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92618 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7463 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.028407 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 529.473600 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7462 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 93322 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 273.137395 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 151.655882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.256113 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45588 48.85% 48.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18736 20.08% 68.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6915 7.41% 76.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3558 3.81% 80.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3108 3.33% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2062 2.21% 85.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1352 1.45% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1057 1.13% 88.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10946 11.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 93322 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7762 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.873744 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 521.384620 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7761 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7463 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7463 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.946134 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.603737 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.129560 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6171 82.69% 82.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 489 6.55% 89.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 84 1.13% 90.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 205 2.75% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 200 2.68% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.23% 96.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.23% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.16% 96.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 25 0.33% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.08% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.08% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.04% 96.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 165 2.21% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.09% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.08% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 18 0.24% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 7 0.09% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.11% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7463 # Writes before turning the bus around for reads -system.physmem.totQLat 7683149500 # Total ticks spent queuing -system.physmem.totMemAccLat 11745149500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1083200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35465.05 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7762 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7762 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.437387 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.920909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.626862 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6141 79.12% 79.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 490 6.31% 85.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 77 0.99% 86.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 208 2.68% 89.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 144 1.86% 90.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 54 0.70% 91.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 53 0.68% 92.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 34 0.44% 92.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 115 1.48% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.19% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 16 0.21% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 14 0.18% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 31 0.40% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 17 0.22% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.12% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.31% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 61 0.79% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 9 0.12% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.05% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 7 0.09% 96.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 74 0.95% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.15% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 8 0.10% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 21 0.27% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 7 0.09% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 12 0.15% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 7 0.09% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 28 0.36% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 9 0.12% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.04% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.12% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 8 0.10% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 7 0.09% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.04% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.06% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 3 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 3 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7762 # Writes before turning the bus around for reads +system.physmem.totQLat 7644398000 # Total ticks spent queuing +system.physmem.totMemAccLat 11701073000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1081780000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35332.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54215.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54082.50 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.86 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.13 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.48 # Average write queue length when enqueuing -system.physmem.readRowHits 183194 # Number of row buffer hits during reads -system.physmem.writeRowHits 89685 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.24 # Row buffer hit rate for writes -system.physmem.avgGap 7692449.94 # Average gap between requests -system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2709796310750 # Time in different power states -system.physmem.memoryStateTime::REF 94955640000 # Time in different power states +system.physmem.avgRdQLen 1.94 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.48 # Average write queue length when enqueuing +system.physmem.readRowHits 183280 # Number of row buffer hits during reads +system.physmem.writeRowHits 121675 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.88 # Row buffer hit rate for writes +system.physmem.avgGap 7038582.19 # Average gap between requests +system.physmem.pageHitRate 76.57 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2710525028500 # Time in different power states +system.physmem.memoryStateTime::REF 94981640000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 38900516750 # Time in different power states +system.physmem.memoryStateTime::ACT 38919724000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 358956360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 341235720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 195859125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 186190125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 862929600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 826854600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 486680400 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 477919440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 185733231840 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 185733231840 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 81937929780 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81435296655 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1634313275250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1634754181500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1903888862355 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1903754909880 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.523453 # Core power per rank (mW) -system.physmem.averagePower::1 669.476347 # Core power per rank (mW) +system.physmem.actEnergy::0 365533560 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 339980760 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 199447875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 185505375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 870612600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 816964200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 599250960 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 579597120 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 185784087840 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 185784087840 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 82151193285 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 81119552850 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1634593377000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1635498324750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1904563503120 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1904324012895 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.577359 # Core power per rank (mW) +system.physmem.averagePower::1 669.493163 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory @@ -353,15 +367,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 34892527 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17126488 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1674515 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20008950 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14462185 # Number of BTB hits +system.cpu0.branchPred.lookups 35736686 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17706973 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1707657 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20554340 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 14845557 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.278580 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 10813099 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 822816 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.225900 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 10924417 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 815226 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -386,25 +400,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23969265 # DTB read hits -system.cpu0.dtb.read_misses 62663 # DTB read misses -system.cpu0.dtb.write_hits 17948332 # DTB write hits -system.cpu0.dtb.write_misses 6711 # DTB write misses +system.cpu0.dtb.read_hits 24607000 # DTB read hits +system.cpu0.dtb.read_misses 66402 # DTB read misses +system.cpu0.dtb.write_hits 18455953 # DTB write hits +system.cpu0.dtb.write_misses 6655 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3475 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1396 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1982 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3808 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1234 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2108 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 568 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24031928 # DTB read accesses -system.cpu0.dtb.write_accesses 17955043 # DTB write accesses +system.cpu0.dtb.perms_faults 615 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24673402 # DTB read accesses +system.cpu0.dtb.write_accesses 18462608 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41917597 # DTB hits -system.cpu0.dtb.misses 69374 # DTB misses -system.cpu0.dtb.accesses 41986971 # DTB accesses +system.cpu0.dtb.hits 43062953 # DTB hits +system.cpu0.dtb.misses 73057 # DTB misses +system.cpu0.dtb.accesses 43136010 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -426,8 +440,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 70358748 # ITB inst hits -system.cpu0.itb.inst_misses 3854 # ITB inst misses +system.cpu0.itb.inst_hits 71661808 # ITB inst hits +system.cpu0.itb.inst_misses 4142 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -436,123 +450,123 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2220 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2456 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7388 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 8241 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 70362602 # ITB inst accesses -system.cpu0.itb.hits 70358748 # DTB hits -system.cpu0.itb.misses 3854 # DTB misses -system.cpu0.itb.accesses 70362602 # DTB accesses -system.cpu0.numCycles 229119066 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 71665950 # ITB inst accesses +system.cpu0.itb.hits 71661808 # DTB hits +system.cpu0.itb.misses 4142 # DTB misses +system.cpu0.itb.accesses 71665950 # DTB accesses +system.cpu0.numCycles 235973632 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 109189984 # Number of instructions committed -system.cpu0.committedOps 132016369 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8791665 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1828 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5458204948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.098352 # CPI: cycles per instruction -system.cpu0.ipc 0.476564 # IPC: instructions per cycle +system.cpu0.committedInsts 111703770 # Number of instructions committed +system.cpu0.committedOps 135097839 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8562554 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1855 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5452894525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.112495 # CPI: cycles per instruction +system.cpu0.ipc 0.473374 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1830 # number of quiesce instructions executed -system.cpu0.tickCycles 193229301 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 35889765 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 714801 # number of replacements -system.cpu0.dcache.tags.tagsinuse 493.827802 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 40473769 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 715313 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.581901 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 493.827802 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.964507 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.964507 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1855 # number of quiesce instructions executed +system.cpu0.tickCycles 199544848 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 36428784 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 751860 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.262864 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 41566353 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 752372 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.247076 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 306713000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.262864 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965357 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.965357 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 83782876 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 83782876 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 22802755 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22802755 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862558 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16862558 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381551 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 381551 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362630 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362630 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 39665313 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 39665313 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 39665313 # number of overall hits -system.cpu0.dcache.overall_hits::total 39665313 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 537301 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 537301 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 532764 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 532764 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6412 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6412 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20204 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20204 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 1070065 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1070065 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 1070065 # number of overall misses -system.cpu0.dcache.overall_misses::total 1070065 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6609674711 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6609674711 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8019150247 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8019150247 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 105707749 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 105707749 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 437634051 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 437634051 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 129000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 14628824958 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 14628824958 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 14628824958 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 14628824958 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23340056 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23340056 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395322 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17395322 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387963 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387963 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382834 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382834 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 40735378 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 40735378 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 40735378 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40735378 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023021 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.023021 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030627 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030627 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016527 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016527 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.052775 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052775 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026269 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026269 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026269 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026269 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12301.623691 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12301.623691 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15051.974696 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15051.974696 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16485.924672 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16485.924672 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21660.762770 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21660.762770 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 86104149 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 86104149 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 23403701 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23403701 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 17336391 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17336391 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 390425 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 390425 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 371566 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 371566 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 40740092 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 40740092 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 40740092 # number of overall hits +system.cpu0.dcache.overall_hits::total 40740092 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 564897 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 564897 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 554409 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 554409 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6644 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6644 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20340 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20340 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 1119306 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1119306 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 1119306 # number of overall misses +system.cpu0.dcache.overall_misses::total 1119306 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6887885459 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6887885459 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8219762503 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8219762503 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 108110000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 108110000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 440070983 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 440070983 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 121000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 15107647962 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15107647962 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 15107647962 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15107647962 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23968598 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23968598 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17890800 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17890800 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 397069 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 397069 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 391906 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 391906 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 41859398 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 41859398 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 41859398 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 41859398 # 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number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,76 +575,74 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 517954 # number of writebacks -system.cpu0.dcache.writebacks::total 517954 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42678 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 42678 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230706 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 230706 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 1 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1 # 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mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016525 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052775 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052775 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.019557 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019557 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10346.327282 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10346.327282 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14139.092161 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14139.092161 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14480.229293 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14480.229293 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19638.880865 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19638.880865 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 541643 # number of writebacks +system.cpu0.dcache.writebacks::total 541643 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 45094 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 45094 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 240822 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 240822 # 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number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 398879017 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 398879017 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 115000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 115000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9690655600 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9690655600 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9690655600 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9690655600 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6196262496 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6196262496 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4811489492 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4811489492 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11007751988 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11007751988 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021687 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021687 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017528 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017528 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.051900 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051900 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.019909 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.019909 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10241.794353 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10241.794353 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13925.769149 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13925.769149 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14269.416014 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14269.416014 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19610.571141 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19610.571141 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -638,58 +650,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1983566 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.796833 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 68366923 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1984078 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.457780 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796833 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999603 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 2070442 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.797171 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 69582233 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 2070954 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 33.599121 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6297775000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.797171 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999604 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 142686127 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 142686127 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 68366923 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 68366923 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 68366923 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 68366923 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 68366923 # number of overall hits -system.cpu0.icache.overall_hits::total 68366923 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1984094 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1984094 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1984094 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1984094 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1984094 # number of overall misses -system.cpu0.icache.overall_misses::total 1984094 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16546799645 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 16546799645 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 16546799645 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 16546799645 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 16546799645 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 16546799645 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 70351017 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 70351017 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 70351017 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 70351017 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 70351017 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 70351017 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028203 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028203 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028203 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028203 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028203 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028203 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.725661 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.725661 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8339.725661 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8339.725661 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 145377375 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 145377375 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 69582233 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 69582233 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 69582233 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 69582233 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 69582233 # number of overall hits +system.cpu0.icache.overall_hits::total 69582233 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 2070970 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2070970 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 2070970 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2070970 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 2070970 # number of overall misses +system.cpu0.icache.overall_misses::total 2070970 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17258012980 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 17258012980 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 17258012980 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 17258012980 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 17258012980 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 17258012980 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 71653203 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 71653203 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 71653203 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 71653203 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 71653203 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 71653203 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028903 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.028903 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028903 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.028903 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028903 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.028903 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8333.299362 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8333.299362 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8333.299362 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8333.299362 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -698,326 +710,313 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1984094 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1984094 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1984094 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1984094 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1984094 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1984094 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13568682853 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13568682853 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13568682853 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13568682853 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13568682853 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13568682853 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276787500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276787500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276787500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 276787500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028203 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028203 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028203 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.729845 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2070970 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 2070970 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 2070970 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 2070970 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 2070970 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 2070970 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 14149699520 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 14149699520 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 14149699520 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 14149699520 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 14149699520 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 14149699520 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276493750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276493750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276493750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 276493750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028903 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028903 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028903 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6832.401976 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17337039 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425762 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16383461 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9078 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 18115074 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 431506 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 17132776 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9283 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6456 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512279 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329409 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6596 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 534910 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1383846 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 409357 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16202.462840 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3013500 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 425611 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.080409 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4205.324174 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 51.364575 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062072 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2198.474976 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.237044 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.256673 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003135 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.replacements 428439 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16212.256950 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3152645 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 444682 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 7.089662 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2824980212500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4226.197620 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.775812 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065487 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2187.555983 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.662049 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.257947 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003099 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134184 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594924 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988920 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8963 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7281 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 54 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2805 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5150 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 820 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # 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mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.160439 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046153 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856775 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856775 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.881465 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.881465 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.154795 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154795 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.044889 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226671 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24503.941556 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24499.196485 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41646.576259 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17039.541033 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17039.541033 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13222.799254 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13222.799254 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 44500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 44500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27509.077572 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27509.077572 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25492.815284 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38357.472316 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225125 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24365.159010 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24387.417709 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40472.031944 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17220.066452 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17220.066452 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13307.710748 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13307.710748 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27564.673910 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27564.673910 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25424.656953 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37471.664733 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1025,67 +1024,67 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2765429 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2670282 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 517951 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 696439 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 70465 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42615 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 93717 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 291656 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 282057 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3974309 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393187 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11845 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 168040 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6547381 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127177856 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86874167 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17764 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 315068 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 214384855 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1083965 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4385734 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.219720 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.414057 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2861093 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2792980 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28855 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28855 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 541643 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 731101 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 68486 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42622 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 93982 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 302729 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 293421 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 4148051 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2491359 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12339 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 183942 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6835691 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 132737600 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 90757533 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17524 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 340220 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 223852877 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1093341 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4548807 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.213001 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.409428 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 3422100 78.03% 78.03% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 963634 21.97% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 3579907 78.70% 78.70% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 968900 21.30% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4385734 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2275890990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4548807 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2378574445 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 119346000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 119537998 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2982392646 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 3112636730 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1235371968 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1291088389 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7407493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7963988 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 89292476 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 98908477 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4040174 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2339682 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 248924 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2652147 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1629183 # Number of BTB hits +system.cpu1.branchPred.lookups 3448752 # Number of BP lookups +system.cpu1.branchPred.condPredicted 1941981 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 196391 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2221819 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1396869 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 61.428835 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 794888 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 55483 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 62.870513 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 715789 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 52420 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1109,25 +1108,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4061400 # DTB read hits -system.cpu1.dtb.read_misses 20326 # DTB read misses -system.cpu1.dtb.write_hits 3327397 # DTB write hits -system.cpu1.dtb.write_misses 1493 # DTB write misses +system.cpu1.dtb.read_hits 3432223 # DTB read hits +system.cpu1.dtb.read_misses 19764 # DTB read misses +system.cpu1.dtb.write_hits 2826731 # DTB write hits +system.cpu1.dtb.write_misses 1392 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 130 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1674 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 275 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4081726 # DTB read accesses -system.cpu1.dtb.write_accesses 3328890 # DTB write accesses +system.cpu1.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3451987 # DTB read accesses +system.cpu1.dtb.write_accesses 2828123 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7388797 # DTB hits -system.cpu1.dtb.misses 21819 # DTB misses -system.cpu1.dtb.accesses 7410616 # DTB accesses +system.cpu1.dtb.hits 6258954 # DTB hits +system.cpu1.dtb.misses 21156 # DTB misses +system.cpu1.dtb.accesses 6280110 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1149,8 +1148,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7665717 # ITB inst hits -system.cpu1.itb.inst_misses 2240 # ITB inst misses +system.cpu1.itb.inst_hits 6653879 # ITB inst hits +system.cpu1.itb.inst_misses 1856 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1159,122 +1158,122 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1155 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 882 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1128 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7667957 # ITB inst accesses -system.cpu1.itb.hits 7665717 # DTB hits -system.cpu1.itb.misses 2240 # DTB misses -system.cpu1.itb.accesses 7667957 # DTB accesses -system.cpu1.numCycles 40520229 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6655735 # ITB inst accesses +system.cpu1.itb.hits 6653879 # DTB hits +system.cpu1.itb.misses 1856 # DTB misses +system.cpu1.itb.accesses 6655735 # DTB accesses +system.cpu1.numCycles 36145472 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15863154 # Number of instructions committed -system.cpu1.committedOps 19391289 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1555006 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2808 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5646190749 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.554361 # CPI: cycles per instruction -system.cpu1.ipc 0.391487 # IPC: instructions per cycle +system.cpu1.committedInsts 13424165 # Number of instructions committed +system.cpu1.committedOps 16401555 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1287407 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5652095397 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.692568 # CPI: cycles per instruction +system.cpu1.ipc 0.371393 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2810 # number of quiesce instructions executed -system.cpu1.tickCycles 29462484 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 11057745 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 188500 # number of replacements -system.cpu1.dcache.tags.tagsinuse 474.724355 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6998456 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 188865 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.055336 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 474.724355 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927196 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.927196 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14854828 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14854828 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 3752021 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3752021 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051608 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3051608 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88860 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88860 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69213 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 69213 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 6803629 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6803629 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 6803629 # number of overall hits -system.cpu1.dcache.overall_hits::total 6803629 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 182037 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 182037 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 139457 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 139457 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5164 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5164 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23160 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23160 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 321494 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 321494 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 321494 # number of overall misses -system.cpu1.dcache.overall_misses::total 321494 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2747896424 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2747896424 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3339347493 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3339347493 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93721501 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 93721501 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540094758 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 540094758 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 317500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 317500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 6087243917 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6087243917 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 6087243917 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6087243917 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3934058 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3934058 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3191065 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3191065 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94024 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 94024 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92373 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92373 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 7125123 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7125123 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 7125123 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7125123 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046272 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.046272 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043702 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.043702 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054922 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054922 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250723 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250723 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045121 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.045121 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045121 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.045121 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15095.263183 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15095.263183 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23945.355866 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 23945.355866 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18149.012587 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18149.012587 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23320.153627 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23320.153627 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed +system.cpu1.tickCycles 26236459 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 9909013 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 149765 # number of replacements +system.cpu1.dcache.tags.tagsinuse 476.829408 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 5935391 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 150124 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.536590 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 107725830000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 476.829408 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.931307 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.931307 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12574886 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12574886 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.inst 3167382 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3167382 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.inst 2587127 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2587127 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 79870 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79870 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 60510 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 60510 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.inst 5754509 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5754509 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 5754509 # number of overall hits +system.cpu1.dcache.overall_hits::total 5754509 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 151161 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 151161 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 116953 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 116953 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5079 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5079 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 22818 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22818 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.inst 268114 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 268114 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.inst 268114 # number of overall misses +system.cpu1.dcache.overall_misses::total 268114 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2359046468 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2359046468 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3063915205 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3063915205 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93260000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 93260000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 534664798 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 534664798 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 106500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 106500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 5422961673 # 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number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 6022623 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6022623 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 6022623 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6022623 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.045550 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045550 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043251 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.043251 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.059789 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.059789 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.273834 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273834 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044518 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044518 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044518 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044518 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15606.184585 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.184585 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26197.833360 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26197.833360 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18361.882260 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18361.882260 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23431.711719 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.711719 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18934.238017 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18934.238017 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20226.327879 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20226.327879 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1283,74 +1282,74 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 115754 # number of writebacks -system.cpu1.dcache.writebacks::total 115754 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15456 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 15456 # 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average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22187.199720 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22187.199720 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16147.463013 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.463013 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21267.195250 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21267.195250 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 93707 # number of writebacks +system.cpu1.dcache.writebacks::total 93707 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 11593 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 11593 # 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average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # 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Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 469 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 16220792 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 16220792 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6770083 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6770083 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6770083 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6770083 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6770083 # 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miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124412 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.124412 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124412 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.124412 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8109.785471 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8109.785471 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8109.785471 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8109.785471 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1417,310 +1417,310 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893542 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 893542 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 893542 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 893542 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 893542 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 893542 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923954530 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923954530 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923954530 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5923954530 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923954530 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5923954530 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10589750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10589750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10589750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10589750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116595 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.743795 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 827664 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 827664 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 827664 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 827664 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 827664 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 827664 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5467532518 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5467532518 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5467532518 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5467532518 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5467532518 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5467532518 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10038000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10038000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10038000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10038000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124412 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.124412 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.124412 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6605.980830 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7064659 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 40510 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6914419 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1409 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6453687 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 29592 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6340817 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 898 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2627 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 105694 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 724613 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2376 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 80004 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 668025 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 80002 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15534.005683 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1138706 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 95380 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.938624 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 52740 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15520.178150 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1029232 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 68128 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 15.107327 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6881.050205 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.485106 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.098583 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2338.762949 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6287.608842 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.419986 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001617 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142747 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.383765 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.948120 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10071 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6676 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3263 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 237 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1869 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.614685 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.321838 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21370209 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21370209 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 22701 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2439 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993088 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1018228 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 115754 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 115754 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1810 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1810 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 740 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 740 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 27796 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27796 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 22701 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2439 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1020884 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1046024 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 22701 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2439 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1020884 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1046024 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 604 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 243 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 72199 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 73046 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28140 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28140 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22420 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22420 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32240 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32240 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 604 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 243 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 104439 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 105286 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 604 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 243 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 104439 # number of overall misses -system.cpu1.l2cache.overall_misses::total 105286 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13239000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4899500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1623706138 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1641844638 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 531483393 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 531483393 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440502566 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440502566 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 296000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 296000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1126750383 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1126750383 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13239000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4899500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2750456521 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 2768595021 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13239000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4899500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2750456521 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 2768595021 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23305 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2682 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1065287 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 1091274 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 115754 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 115754 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29950 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29950 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23160 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23160 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60036 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 60036 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23305 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2682 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1125323 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1151310 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23305 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2682 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1125323 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1151310 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090604 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067774 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.066936 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.939566 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.939566 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.968048 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.968048 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.537011 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.537011 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090604 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092808 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.091449 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090604 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092808 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.091449 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20162.551440 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22489.316168 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22476.858938 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18887.114179 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18887.114179 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19647.750491 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19647.750491 # average SCUpgradeReq miss latency +system.cpu1.l2cache.tags.occ_blocks::writebacks 6901.586978 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.255538 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 87 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6442 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 153 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1624 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 7082 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 51 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 256 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1161 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5025 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.540710 # 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number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4930797243 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316625253 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316625253 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 186937501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 186937501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 503562754 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 503562754 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.066269 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.065467 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 30368 # number of writebacks +system.cpu1.l2cache.writebacks::total 30368 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 950 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 950 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 295 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 295 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1245 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 1245 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1245 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 1245 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 704 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 245 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 65524 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 66473 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 80004 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 80004 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 27781 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27781 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22285 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22285 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 29842 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 29842 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 704 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 245 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 95366 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 96315 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 704 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 245 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 95366 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 80004 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 176319 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3095998 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 981688737 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 994327236 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2522312930 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2522312930 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 396174942 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 396174942 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 306073762 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306073762 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 76500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 76500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 831450098 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 831450098 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3095998 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1813138835 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 1825777334 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3095998 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1813138835 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2522312930 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4348090264 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 313994504 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 313994504 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 182561501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 182561501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 496556005 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 496556005 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.067390 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.066598 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.939566 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.939566 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.968048 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.968048 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.531648 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.531648 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.089776 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.947187 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947187 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.976641 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.976641 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.616112 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.616112 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.092031 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181579 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15556.048375 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15542.478332 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27988.792401 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14371.563433 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14371.563433 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13747.490054 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13747.490054 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168476 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14982.124672 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14958.362583 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31527.335258 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14260.643677 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14260.643677 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13734.519273 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13734.519273 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27011.845416 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27011.845416 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19084.266825 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23586.237254 # average overall mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27861.741773 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27861.741773 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18956.313492 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24660.361413 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1728,64 +1728,64 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1582615 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1137834 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2120 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2120 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 115754 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 151048 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84372 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41116 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85179 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 76804 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 64396 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787314 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 769072 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6988 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51360 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2614734 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57194048 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24925415 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10728 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93220 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 82223411 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 838592 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2085067 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.363773 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.481085 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1502965 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1041469 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2098 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2098 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 93707 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 114724 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 83933 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40744 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84523 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 65298 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 52790 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1655558 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 667978 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6105 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48641 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2378282 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 52977856 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 21039827 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10136 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93092 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 74120911 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 816365 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1934720 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.382054 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.485890 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1326575 63.62% 63.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 758492 36.38% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1195552 61.79% 61.79% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 739168 38.21% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2085067 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 782771935 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1934720 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 695166718 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 78513000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 78719500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1341710719 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1243267482 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 381436893 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 322631890 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4307996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3571998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 28057498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 25370995 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31012 # Transaction distribution -system.iobus.trans_dist::ReadResp 31012 # Transaction distribution -system.iobus.trans_dist::WriteReq 59407 # Transaction distribution -system.iobus.trans_dist::WriteResp 59440 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31020 # Transaction distribution +system.iobus.trans_dist::ReadResp 31020 # Transaction distribution +system.iobus.trans_dist::WriteReq 59447 # Transaction distribution +system.iobus.trans_dist::WriteResp 23223 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56686 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1806,11 +1806,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 108000 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71630 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1831,11 +1831,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162880 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40158000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1875,508 +1875,517 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326658321 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347075142 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84777000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36824131 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36822606 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36417 # number of replacements -system.iocache.tags.tagsinuse 0.992159 # Cycle average of tags in use +system.iocache.tags.replacements 36433 # number of replacements +system.iocache.tags.tagsinuse 0.995239 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 268855800000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.992159 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062010 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062010 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 269184120000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.995239 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062202 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062202 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328467 # Number of tag accesses -system.iocache.tags.data_accesses 328467 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses system.iocache.ReadReq_misses::total 243 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses system.iocache.demand_misses::total 243 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 243 # number of overall misses system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31254127 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31254127 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31254127 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31254127 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31254127 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31254127 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 30315377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 30315377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9644186159 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9644186159 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 30315377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 30315377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 30315377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 30315377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128617.806584 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128617.806584 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128617.806584 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128617.806584 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124754.637860 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124754.637860 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266237.471262 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 266237.471262 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124754.637860 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124754.637860 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 57278 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7269 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.879763 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18617627 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18617627 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2261621825 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2261621825 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18617627 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18617627 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18617627 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18617627 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17678377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17678377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7760326371 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7760326371 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17678377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17678377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17678377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17678377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76615.748971 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76615.748971 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72750.522634 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72750.522634 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214231.624641 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214231.624641 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 151810 # number of replacements -system.l2c.tags.tagsinuse 64480.586594 # Cycle average of tags in use -system.l2c.tags.total_refs 529933 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 216565 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.446993 # Average number of references to valid blocks. +system.l2c.tags.replacements 150396 # number of replacements +system.l2c.tags.tagsinuse 64479.883220 # Cycle average of tags in use +system.l2c.tags.total_refs 522727 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 215317 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.427709 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12374.174406 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.831156 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030524 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3874.361594 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42727.383721 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.891665 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 757.615436 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4654.298093 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.188815 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001249 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059118 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.651968 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011560 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071019 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983896 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 46322 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 18386 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6596 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39440 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2604 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 15495 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.706818 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.280548 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6644341 # Number of tag accesses -system.l2c.tags.data_accesses 6644341 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 563 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 116 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 36701 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 207577 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 56 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11433 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 45418 # number of ReadReq hits -system.l2c.ReadReq_hits::total 301993 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 252536 # number of Writeback hits -system.l2c.Writeback_hits::total 252536 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 11942 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 830 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12772 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 205 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 179 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 3525 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 1107 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4632 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 563 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 116 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 40226 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 207577 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 129 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 56 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 12540 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 45418 # number of demand (read+write) hits -system.l2c.demand_hits::total 306625 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 563 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 116 # number of overall hits -system.l2c.overall_hits::cpu0.inst 40226 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 207577 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 129 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 56 # number of overall hits -system.l2c.overall_hits::cpu1.inst 12540 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 45418 # number of overall hits -system.l2c.overall_hits::total 306625 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses +system.l2c.tags.occ_blocks::writebacks 12469.492368 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 93.733463 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3818.005633 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42810.602787 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.718540 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 732.215158 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4549.115372 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.190269 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001430 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.058258 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.653238 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.011173 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.069414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983885 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 47457 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 17396 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 475 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6086 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 40896 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 67 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 270 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2310 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 14797 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.724136 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.265442 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6561930 # Number of tag accesses +system.l2c.tags.data_accesses 6561930 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 576 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 131 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 39519 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 221242 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 94 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 19 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 6900 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 25945 # number of ReadReq hits +system.l2c.ReadReq_hits::total 294426 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 250431 # number of Writeback hits +system.l2c.Writeback_hits::total 250431 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 11782 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 481 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 12263 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 184 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 192 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 3646 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 908 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4554 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 576 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 131 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 43165 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 221242 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 94 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 19 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7808 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 25945 # number of demand (read+write) hits +system.l2c.demand_hits::total 298980 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 576 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 131 # number of overall hits +system.l2c.overall_hits::cpu0.inst 43165 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 221242 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 94 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 19 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7808 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 25945 # number of overall hits +system.l2c.overall_hits::total 298980 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 161 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 11286 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168297 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1852 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 18208 # number of ReadReq misses -system.l2c.ReadReq_misses::total 199810 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 9028 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 2665 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11693 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 461 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 1254 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1715 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 7011 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 6410 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 13421 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 11256 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 169617 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1341 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 17501 # number of ReadReq misses +system.l2c.ReadReq_misses::total 199885 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 9580 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 2241 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11821 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 527 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 1214 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1741 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 6969 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 6429 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 13398 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 161 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 18297 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 168297 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 8262 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 18208 # number of demand (read+write) misses -system.l2c.demand_misses::total 213231 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses +system.l2c.demand_misses::cpu0.inst 18225 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 169617 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7770 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 17501 # number of demand (read+write) misses +system.l2c.demand_misses::total 213283 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 161 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.398182 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.430520 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.762518 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.477948 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.692192 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.875087 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.817056 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.665433 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.852734 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.743422 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.410171 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.410171 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 1324667340 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 500000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 493247005 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 19704446766 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5522428749 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 260648000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5783076749 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4102579499 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 146450000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4249029499 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9625008248 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 407098000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10032106248 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.221684 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.162723 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.404369 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.448460 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.823292 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.490824 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.741210 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.863442 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.822390 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.656524 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.876244 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.746324 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.296872 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.498780 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.416353 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.296872 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.498780 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.416353 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72255.493355 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69508.098272 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 94172.624146 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10101.567678 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10067.034522 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.697084 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10119.212581 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10053.625997 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.255977 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72038.558979 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61619.191732 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67062.167946 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72653.539979 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71955.443699 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 94058.618584 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.646555 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10096.708166 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10189.046358 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10290.366224 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10019.530478 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10101.512349 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72733.404219 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61713.292114 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67445.428348 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2387,57 +2396,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 238091 # Transaction distribution -system.membus.trans_dist::ReadResp 238091 # Transaction distribution -system.membus.trans_dist::WriteReq 30933 # Transaction distribution -system.membus.trans_dist::WriteResp 30933 # Transaction distribution -system.membus.trans_dist::Writeback 112127 # Transaction distribution +system.membus.trans_dist::ReadReq 238185 # Transaction distribution +system.membus.trans_dist::ReadResp 238185 # Transaction distribution +system.membus.trans_dist::WriteReq 30953 # Transaction distribution +system.membus.trans_dist::WriteResp 30953 # Transaction distribution +system.membus.trans_dist::Writeback 146942 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 79652 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39985 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13516 # Transaction distribution -system.membus.trans_dist::ReadExReq 30363 # Transaction distribution -system.membus.trans_dist::ReadExResp 13313 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 78292 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39832 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13662 # Transaction distribution +system.membus.trans_dist::ReadExReq 30241 # Transaction distribution +system.membus.trans_dist::ReadExResp 13298 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 108000 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 826518 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 899224 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13634 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 701758 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 823430 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 932326 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162880 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21038188 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21229406 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23548702 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123399 # Total snoops (count) -system.membus.snoop_fanout::samples 498406 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27268 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 20926892 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21118256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25753712 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 122070 # Total snoops (count) +system.membus.snoop_fanout::samples 531658 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 498406 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 531658 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 498406 # Request fanout histogram -system.membus.reqLayer0.occupancy 87864494 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 531658 # Request fanout histogram +system.membus.reqLayer0.occupancy 88755994 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11666999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11894500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1620379248 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1935574499 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2120601580 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2123782192 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38542869 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38517394 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2470,44 +2479,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 668340 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 668325 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30933 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30933 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 252536 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 92316 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40369 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 132685 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 38932 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 38932 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370044 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368770 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1738814 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41959415 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7901735 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 49861150 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 291964 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1090717 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.033437 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.179774 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 658320 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 658305 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30953 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30953 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 250431 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 90455 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40208 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 130663 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 38633 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 38633 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1411505 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 304961 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1716466 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 43486557 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5753747 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 49240304 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 287552 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1076220 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.033884 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.180932 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1054247 96.66% 96.66% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36470 3.34% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1039753 96.61% 96.61% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36467 3.39% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1090717 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1589301055 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1076220 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1573537018 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2361799867 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2438104006 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 804005619 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 680349684 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 8921a3479..1c98029fc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,119 +1,116 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852237 # Number of seconds simulated -sim_ticks 2852237227000 # Number of ticks simulated -final_tick 2852237227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852850 # Number of seconds simulated +sim_ticks 2852849954000 # Number of ticks simulated +final_tick 2852849954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157725 # Simulator instruction rate (inst/s) -host_op_rate 190692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4039440180 # Simulator tick rate (ticks/s) -host_mem_usage 566224 # Number of bytes of host memory used -host_seconds 706.10 # Real time elapsed on the host -sim_insts 111368950 # Number of instructions simulated -sim_ops 134647110 # Number of ops (including micro ops) simulated +host_inst_rate 160685 # Simulator instruction rate (inst/s) +host_op_rate 194286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4092855045 # Simulator tick rate (ticks/s) +host_mem_usage 562916 # Number of bytes of host memory used +host_seconds 697.03 # Real time elapsed on the host +sim_insts 112002684 # Number of instructions simulated +sim_ops 135423332 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 6208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10897572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10823844 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10904868 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1667392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1667392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5682816 # Number of bytes written to this memory +system.physmem.bytes_read::total 10832740 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1658560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1658560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7967296 # Number of bytes written to this memory system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8018676 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 97 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 170794 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7984820 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 169642 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 88794 # Number of write requests responded to by this memory +system.physmem.num_reads::total 169781 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124489 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129399 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3820710 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128870 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2759 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3794046 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3823268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 584591 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 584591 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1992407 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 6144 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 812813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2811364 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1992407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3826854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 813150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6634632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170908 # Number of read requests accepted -system.physmem.writeReqs 129399 # Number of write requests accepted -system.physmem.readBursts 170908 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129399 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10927552 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10560 # Total number of bytes read from write queue -system.physmem.bytesWritten 8032256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10904868 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8018676 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3869 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4597 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10514 # Per bank write bursts -system.physmem.perBankRdBursts::1 10246 # Per bank write bursts -system.physmem.perBankRdBursts::2 10769 # Per bank write bursts -system.physmem.perBankRdBursts::3 10552 # Per bank write bursts -system.physmem.perBankRdBursts::4 13499 # Per bank write bursts -system.physmem.perBankRdBursts::5 10126 # Per bank write bursts -system.physmem.perBankRdBursts::6 11178 # Per bank write bursts -system.physmem.perBankRdBursts::7 10889 # Per bank write bursts -system.physmem.perBankRdBursts::8 10228 # Per bank write bursts -system.physmem.perBankRdBursts::9 10887 # Per bank write bursts -system.physmem.perBankRdBursts::10 10100 # Per bank write bursts -system.physmem.perBankRdBursts::11 9610 # Per bank write bursts -system.physmem.perBankRdBursts::12 10315 # Per bank write bursts -system.physmem.perBankRdBursts::13 11222 # Per bank write bursts -system.physmem.perBankRdBursts::14 10292 # Per bank write bursts -system.physmem.perBankRdBursts::15 10316 # Per bank write bursts -system.physmem.perBankWrBursts::0 7730 # Per bank write bursts -system.physmem.perBankWrBursts::1 7667 # Per bank write bursts -system.physmem.perBankWrBursts::2 8410 # Per bank write bursts -system.physmem.perBankWrBursts::3 8128 # Per bank write bursts -system.physmem.perBankWrBursts::4 7856 # Per bank write bursts -system.physmem.perBankWrBursts::5 7340 # Per bank write bursts -system.physmem.perBankWrBursts::6 8209 # Per bank write bursts -system.physmem.perBankWrBursts::7 8042 # Per bank write bursts -system.physmem.perBankWrBursts::8 7786 # Per bank write bursts -system.physmem.perBankWrBursts::9 8073 # Per bank write bursts -system.physmem.perBankWrBursts::10 7525 # Per bank write bursts -system.physmem.perBankWrBursts::11 7421 # Per bank write bursts -system.physmem.perBankWrBursts::12 7760 # Per bank write bursts -system.physmem.perBankWrBursts::13 8405 # Per bank write bursts -system.physmem.perBankWrBursts::14 7549 # Per bank write bursts -system.physmem.perBankWrBursts::15 7603 # Per bank write bursts +system.physmem.bw_read::total 3797164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 581370 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 581370 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2792750 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.inst 6143 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2798892 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2792750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3800189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6596057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 169781 # Number of read requests accepted +system.physmem.writeReqs 165094 # Number of write requests accepted +system.physmem.readBursts 169781 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 165094 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10858880 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 10194112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10832740 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10303156 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5787 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4592 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10675 # Per bank write bursts +system.physmem.perBankRdBursts::1 10570 # Per bank write bursts +system.physmem.perBankRdBursts::2 10940 # Per bank write bursts +system.physmem.perBankRdBursts::3 10884 # Per bank write bursts +system.physmem.perBankRdBursts::4 12996 # Per bank write bursts +system.physmem.perBankRdBursts::5 10666 # Per bank write bursts +system.physmem.perBankRdBursts::6 11098 # Per bank write bursts +system.physmem.perBankRdBursts::7 10877 # Per bank write bursts +system.physmem.perBankRdBursts::8 10287 # Per bank write bursts +system.physmem.perBankRdBursts::9 10457 # Per bank write bursts +system.physmem.perBankRdBursts::10 10268 # Per bank write bursts +system.physmem.perBankRdBursts::11 9318 # Per bank write bursts +system.physmem.perBankRdBursts::12 10425 # Per bank write bursts +system.physmem.perBankRdBursts::13 10908 # Per bank write bursts +system.physmem.perBankRdBursts::14 9678 # Per bank write bursts +system.physmem.perBankRdBursts::15 9623 # Per bank write bursts +system.physmem.perBankWrBursts::0 10097 # Per bank write bursts +system.physmem.perBankWrBursts::1 10006 # Per bank write bursts +system.physmem.perBankWrBursts::2 10747 # Per bank write bursts +system.physmem.perBankWrBursts::3 10511 # Per bank write bursts +system.physmem.perBankWrBursts::4 9282 # Per bank write bursts +system.physmem.perBankWrBursts::5 9914 # Per bank write bursts +system.physmem.perBankWrBursts::6 10247 # Per bank write bursts +system.physmem.perBankWrBursts::7 10166 # Per bank write bursts +system.physmem.perBankWrBursts::8 10178 # Per bank write bursts +system.physmem.perBankWrBursts::9 10302 # Per bank write bursts +system.physmem.perBankWrBursts::10 10037 # Per bank write bursts +system.physmem.perBankWrBursts::11 9553 # Per bank write bursts +system.physmem.perBankWrBursts::12 10068 # Per bank write bursts +system.physmem.perBankWrBursts::13 10279 # Per bank write bursts +system.physmem.perBankWrBursts::14 8984 # Per bank write bursts +system.physmem.perBankWrBursts::15 8912 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2852236741500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2852849531000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 170353 # Read request sizes (log2) +system.physmem.readPktSize::6 169226 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 125018 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160713 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 162999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -158,154 +155,173 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60829 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.689227 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.313026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.369125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22276 36.62% 36.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14416 23.70% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6737 11.08% 71.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3572 5.87% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2597 4.27% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1607 2.64% 84.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1084 1.78% 85.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1076 1.77% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7464 12.27% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60829 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6321 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.008859 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 576.510415 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6319 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6321 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6321 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.855086 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.377929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.560499 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5522 87.36% 87.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 41 0.65% 88.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 34 0.54% 88.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 217 3.43% 91.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 214 3.39% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 10 0.16% 95.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 16 0.25% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 20 0.32% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 24 0.38% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.06% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.03% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.03% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 162 2.56% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.08% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.19% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 7 0.11% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.08% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.11% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6321 # Writes before turning the bus around for reads -system.physmem.totQLat 1722371500 # Total ticks spent queuing -system.physmem.totMemAccLat 4923802750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 853715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10087.51 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62892 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 334.747313 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.220308 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.895470 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22415 35.64% 35.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14531 23.10% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6612 10.51% 69.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3482 5.54% 74.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2506 3.98% 78.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1581 2.51% 81.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1054 1.68% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1133 1.80% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9578 15.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62892 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6668 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.444061 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 561.318574 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6666 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6668 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6668 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.887672 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.937507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.272912 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5557 83.34% 83.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 39 0.58% 83.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.36% 84.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 223 3.34% 87.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 119 1.78% 89.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 51 0.76% 90.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 29 0.43% 90.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 45 0.67% 91.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 120 1.80% 93.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 12 0.18% 93.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 15 0.22% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 14 0.21% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 30 0.45% 94.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 19 0.28% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.12% 94.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 35 0.52% 95.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 60 0.90% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 9 0.13% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.09% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 14 0.21% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 100 1.50% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 13 0.19% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 8 0.12% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 22 0.33% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 10 0.15% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.04% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 27 0.40% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 9 0.13% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.12% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.07% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.04% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6668 # Writes before turning the bus around for reads +system.physmem.totQLat 1702635750 # Total ticks spent queuing +system.physmem.totMemAccLat 4883948250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 848350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10034.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28837.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28784.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.39 # Average write queue length when enqueuing -system.physmem.readRowHits 140948 # Number of row buffer hits during reads -system.physmem.writeRowHits 94469 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.26 # Row buffer hit rate for writes -system.physmem.avgGap 9497736.45 # Average gap between requests -system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2712717626000 # Time in different power states -system.physmem.memoryStateTime::REF 95242420000 # Time in different power states +system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing +system.physmem.readRowHits 139924 # Number of row buffer hits during reads +system.physmem.writeRowHits 126136 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.18 # Row buffer hit rate for writes +system.physmem.avgGap 8519147.54 # Average gap between requests +system.physmem.pageHitRate 80.87 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2713515031250 # Time in different power states +system.physmem.memoryStateTime::REF 95262700000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 44277091000 # Time in different power states +system.physmem.memoryStateTime::ACT 44072132750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 234707760 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 225159480 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 128064750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122854875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 684629400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 647158200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 410715360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 402550560 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 186294173520 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 186294173520 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 83068916085 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 82611072135 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1638474130500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1638875748000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1909295337375 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1909178716770 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.403001 # Core power per rank (mW) -system.physmem.averagePower::1 669.362113 # Core power per rank (mW) +system.physmem.actEnergy::0 246765960 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 228697560 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134644125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 124785375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 691906800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 631511400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 524685600 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 507468240 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 186333841200 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 186333841200 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 83199782385 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 82045768365 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1638723732000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1639736025000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1909855358070 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1909608097140 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.456797 # Core power per rank (mW) +system.physmem.averagePower::1 669.370126 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory @@ -324,15 +340,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 30773662 # Number of BP lookups -system.cpu.branchPred.condPredicted 16735793 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2481146 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18414792 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13204104 # Number of BTB hits +system.cpu.branchPred.lookups 31051775 # Number of BP lookups +system.cpu.branchPred.condPredicted 16857996 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2519060 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18534749 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13337392 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.703791 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7765871 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1476448 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.958849 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7856975 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1512712 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -357,25 +373,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24574985 # DTB read hits -system.cpu.dtb.read_misses 58557 # DTB read misses -system.cpu.dtb.write_hits 19368965 # DTB write hits -system.cpu.dtb.write_misses 5915 # DTB write misses +system.cpu.dtb.read_hits 24746159 # DTB read hits +system.cpu.dtb.read_misses 60199 # DTB read misses +system.cpu.dtb.write_hits 19443156 # DTB write hits +system.cpu.dtb.write_misses 6950 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4353 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1231 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1821 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4352 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1306 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1783 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24633542 # DTB read accesses -system.cpu.dtb.write_accesses 19374880 # DTB write accesses +system.cpu.dtb.perms_faults 751 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24806358 # DTB read accesses +system.cpu.dtb.write_accesses 19450106 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 43943950 # DTB hits -system.cpu.dtb.misses 64472 # DTB misses -system.cpu.dtb.accesses 44008422 # DTB accesses +system.cpu.dtb.hits 44189315 # DTB hits +system.cpu.dtb.misses 67149 # DTB misses +system.cpu.dtb.accesses 44256464 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -397,8 +413,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 57039019 # ITB inst hits -system.cpu.itb.inst_misses 5418 # ITB inst misses +system.cpu.itb.inst_hits 57672689 # ITB inst hits +system.cpu.itb.inst_misses 5411 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -407,119 +423,119 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2981 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2970 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8633 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8383 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57044437 # ITB inst accesses -system.cpu.itb.hits 57039019 # DTB hits -system.cpu.itb.misses 5418 # DTB misses -system.cpu.itb.accesses 57044437 # DTB accesses -system.cpu.numCycles 313379229 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57678100 # ITB inst accesses +system.cpu.itb.hits 57672689 # DTB hits +system.cpu.itb.misses 5411 # DTB misses +system.cpu.itb.accesses 57678100 # DTB accesses +system.cpu.numCycles 314966932 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 111368950 # Number of instructions committed -system.cpu.committedOps 134647110 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7900477 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5391141904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.813883 # CPI: cycles per instruction -system.cpu.ipc 0.355381 # IPC: instructions per cycle +system.cpu.committedInsts 112002684 # Number of instructions committed +system.cpu.committedOps 135423332 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7762811 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3036 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5390780993 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.812137 # CPI: cycles per instruction +system.cpu.ipc 0.355601 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 224160135 # Number of cycles that the object actually ticked -system.cpu.idleCycles 89219094 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 841413 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.953450 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42452187 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 841925 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.422766 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 279721250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953450 # Average occupied blocks per requestor +system.cpu.kern.inst.quiesce 3036 # number of quiesce instructions executed +system.cpu.tickCycles 228185661 # Number of cycles that the object actually ticked +system.cpu.idleCycles 86781271 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 843230 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.953176 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42691062 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 843742 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.597294 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 281436250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953176 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 175172385 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 175172385 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 23318882 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23318882 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 18212211 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18212211 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457846 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457846 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 460333 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460333 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 41531093 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41531093 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 41531093 # number of overall hits -system.cpu.dcache.overall_hits::total 41531093 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 583694 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 583694 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 541327 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 541327 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8314 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8314 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176134397 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176134397 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 23488260 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23488260 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 18281937 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18281937 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457712 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457712 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 460238 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460238 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 41770197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41770197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 41770197 # number of overall hits +system.cpu.dcache.overall_hits::total 41770197 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 584617 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 584617 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 541532 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 541532 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8359 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8359 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.inst 1125021 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1125021 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1125021 # number of overall misses -system.cpu.dcache.overall_misses::total 1125021 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8654598086 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8654598086 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21588798306 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21588798306 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117927750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 117927750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 52502 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 52502 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 30243396392 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30243396392 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 30243396392 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30243396392 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 23902576 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23902576 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 18753538 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18753538 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466160 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466160 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460335 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460335 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42656114 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42656114 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42656114 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42656114 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024420 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024420 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028865 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028865 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017835 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017835 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.inst 1126149 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1126149 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1126149 # number of overall misses +system.cpu.dcache.overall_misses::total 1126149 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8658802092 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8658802092 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21460434801 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21460434801 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117977250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 117977250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 152000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 152000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 30119236893 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30119236893 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 30119236893 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30119236893 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 24072877 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24072877 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 18823469 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18823469 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466071 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466071 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460240 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460240 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 42896346 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42896346 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 42896346 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42896346 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024285 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.024285 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028769 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.028769 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017935 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017935 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.026374 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026374 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.026374 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026374 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14827.286362 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14827.286362 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39881.251639 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39881.251639 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14184.237431 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.237431 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26251 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26251 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26882.517208 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26882.517208 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26882.517208 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26882.517208 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.026253 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026253 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.026253 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026253 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14811.067916 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14811.067916 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39629.116656 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39629.116656 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14113.799498 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14113.799498 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 76000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 76000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26745.339110 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26745.339110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26745.339110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26745.339110 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,70 +544,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 697938 # number of writebacks -system.cpu.dcache.writebacks::total 697938 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45858 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45858 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242707 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 242707 # 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number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45143 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45143 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242778 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 242778 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 287921 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 287921 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 287921 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 287921 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 539474 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 539474 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298754 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298754 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8359 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8359 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 836456 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 836456 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 836456 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 836456 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6884995145 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6884995145 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11268709155 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11268709155 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101270250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101270250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18153704300 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18153704300 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18153704300 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18153704300 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5790985000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790985000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439182000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439182000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230167000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230167000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022501 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022501 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015923 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015923 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017835 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017835 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 838228 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 838228 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 838228 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 838228 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6896325139 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6896325139 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11211804160 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11211804160 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101230750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101230750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 148000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 148000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18108129299 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18108129299 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18108129299 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18108129299 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5790997000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790997000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439577500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439577500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230574500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230574500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022410 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022410 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015871 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015871 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017935 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017935 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019609 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.019609 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019609 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019609 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12801.290998 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12801.290998 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37735.949216 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37735.949216 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12180.689199 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12180.689199 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24249 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24249 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21703.119232 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21703.119232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21703.119232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21703.119232 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019541 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.019541 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019541 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019541 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12783.424482 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12783.424482 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37528.549107 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37528.549107 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12110.389999 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12110.389999 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 74000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 74000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21602.868550 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21602.868550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21602.868550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21602.868550 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -599,58 +615,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2897611 # number of replacements -system.cpu.icache.tags.tagsinuse 511.427780 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54131846 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2898123 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.678243 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 15213015250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.427780 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998882 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998882 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2898546 # number of replacements +system.cpu.icache.tags.tagsinuse 511.424366 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54764882 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2899058 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.890578 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15302672250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.424366 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998876 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998876 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59928115 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59928115 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54131846 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54131846 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54131846 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54131846 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54131846 # number of overall hits -system.cpu.icache.overall_hits::total 54131846 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2898135 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2898135 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2898135 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2898135 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2898135 # number of overall misses -system.cpu.icache.overall_misses::total 2898135 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39145708027 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39145708027 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39145708027 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39145708027 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39145708027 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39145708027 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57029981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57029981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57029981 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57029981 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57029981 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57029981 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050818 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050818 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050818 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050818 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050818 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050818 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13507.206540 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545306500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545306500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4107046000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107046000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652352500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652352500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010758 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010560 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.982612 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982612 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.445227 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.445227 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001403 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000418 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045204 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044354 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001403 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000418 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045204 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044354 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.443071 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443071 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044077 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044077 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61571.082564 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61580.497277 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10012.707493 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10012.707493 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57572.475847 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57572.475847 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61532.254585 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61543.946887 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10066.727700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10066.727700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 61000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 61000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57558.304584 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57558.304584 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58456.206601 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58460.114557 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58434.353561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58439.219923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58456.206601 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58460.114557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58434.353561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58439.219923 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -930,59 +946,60 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3576313 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3576217 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3581708 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3581608 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 697938 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2821 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 699279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295804 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295804 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5802238 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2505111 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15298 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 156293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8478940 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185670592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98744797 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19124 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276596 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284711109 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 60360 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4574965 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.007969 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.088914 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2820 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295941 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295941 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5804102 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2510082 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14997 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161563 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8490744 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185730048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98946845 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 286516 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284981381 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 60946 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4581834 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.007957 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.088847 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4538506 99.20% 99.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36459 0.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 4545376 99.20% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36458 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4574965 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3011909666 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4581834 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3016682672 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4357140777 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4358543218 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1340495452 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1342977701 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10517000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10504000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 87146500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 89938750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30195 # Transaction distribution system.iobus.trans_dist::ReadResp 30195 # Transaction distribution system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1073,42 +1090,44 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347024164 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804753 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804504 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.031563 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.033420 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 269946820000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.031563 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064473 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064473 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270180945000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.033420 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064589 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064589 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 27956377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 27956377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 27956377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 27956377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 27956377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 27956377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 27950377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 27950377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9603131283 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9603131283 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 27950377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 27950377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 27950377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 27950377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1119,104 +1138,114 @@ system.iocache.overall_accesses::realview.ide 234 system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119471.696581 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119471.696581 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119471.696581 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119471.696581 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119471.696581 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119471.696581 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119446.055556 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265104.110065 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265104.110065 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119446.055556 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119446.055556 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56022 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7210 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.770042 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15787377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15787377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2211427725 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2211427725 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15787377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15787377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15787377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15787377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 15781377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 15781377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7719475291 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7719475291 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 15781377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 15781377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 15781377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 15781377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67467.423077 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67467.423077 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67467.423077 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67467.423077 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67467.423077 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67467.423077 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213103.889438 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213103.889438 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71836 # Transaction distribution -system.membus.trans_dist::ReadResp 71836 # Transaction distribution +system.membus.trans_dist::ReadReq 71576 # Transaction distribution +system.membus.trans_dist::ReadResp 71576 # Transaction distribution system.membus.trans_dist::WriteReq 27607 # Transaction distribution system.membus.trans_dist::WriteResp 27607 # Transaction distribution -system.membus.trans_dist::Writeback 88794 # Transaction distribution +system.membus.trans_dist::Writeback 124489 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4595 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4592 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4597 # Transaction distribution -system.membus.trans_dist::ReadExReq 129881 # Transaction distribution -system.membus.trans_dist::ReadExResp 129881 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4594 # Transaction distribution +system.membus.trans_dist::ReadExReq 129300 # Transaction distribution +system.membus.trans_dist::ReadExResp 129300 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448536 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 628865 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446065 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 662584 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16604248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16768029 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19087325 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 219 # Total snoops (count) -system.membus.snoop_fanout::samples 297195 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16500440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16664221 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21299677 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 507 # Total snoops (count) +system.membus.snoop_fanout::samples 332045 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 297195 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 332045 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 297195 # Request fanout histogram -system.membus.reqLayer0.occupancy 87032500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 332045 # Request fanout histogram +system.membus.reqLayer0.occupancy 87455500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1706500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1699000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1386266250 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1718628403 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1675329000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 1688631909 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38334247 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38334496 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 7a2aefe62..d32247ca8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,125 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.826844 # Number of seconds simulated -sim_ticks 2826844351500 # Number of ticks simulated -final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827042 # Number of seconds simulated +sim_ticks 2827042159500 # Number of ticks simulated +final_tick 2827042159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74392 # Simulator instruction rate (inst/s) -host_op_rate 90233 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1857645684 # Simulator tick rate (ticks/s) -host_mem_usage 566256 # Number of bytes of host memory used -host_seconds 1521.74 # Real time elapsed on the host -sim_insts 113204796 # Number of instructions simulated -sim_ops 137311416 # Number of ops (including micro ops) simulated +host_inst_rate 73670 # Simulator instruction rate (inst/s) +host_op_rate 89358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1840258315 # Simulator tick rate (ticks/s) +host_mem_usage 564112 # Number of bytes of host memory used +host_seconds 1536.22 # Real time elapsed on the host +sim_insts 113173742 # Number of instructions simulated +sim_ops 137273263 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9496932 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory +system.physmem.bytes_read::total 10823604 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8116352 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory +system.physmem.bytes_written::total 8133876 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 148909 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory +system.physmem.num_reads::total 171883 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126818 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory +system.physmem.num_writes::total 131199 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3359317 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3828597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2870970 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2877168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2870970 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 172165 # Number of read requests accepted -system.physmem.writeReqs 131231 # Number of write requests accepted -system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11009408 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue -system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10989 # Per bank write bursts -system.physmem.perBankRdBursts::1 10130 # Per bank write bursts -system.physmem.perBankRdBursts::2 11201 # Per bank write bursts -system.physmem.perBankRdBursts::3 11419 # Per bank write bursts -system.physmem.perBankRdBursts::4 13122 # Per bank write bursts -system.physmem.perBankRdBursts::5 10546 # Per bank write bursts -system.physmem.perBankRdBursts::6 11171 # Per bank write bursts -system.physmem.perBankRdBursts::7 11539 # Per bank write bursts -system.physmem.perBankRdBursts::8 10356 # Per bank write bursts -system.physmem.perBankRdBursts::9 11056 # Per bank write bursts -system.physmem.perBankRdBursts::10 10496 # Per bank write bursts -system.physmem.perBankRdBursts::11 9259 # Per bank write bursts -system.physmem.perBankRdBursts::12 10183 # Per bank write bursts -system.physmem.perBankRdBursts::13 10761 # Per bank write bursts -system.physmem.perBankRdBursts::14 10049 # Per bank write bursts -system.physmem.perBankRdBursts::15 9745 # Per bank write bursts -system.physmem.perBankWrBursts::0 8312 # Per bank write bursts -system.physmem.perBankWrBursts::1 7765 # Per bank write bursts -system.physmem.perBankWrBursts::2 8704 # Per bank write bursts -system.physmem.perBankWrBursts::3 8604 # Per bank write bursts -system.physmem.perBankWrBursts::4 7611 # Per bank write bursts -system.physmem.perBankWrBursts::5 7949 # Per bank write bursts -system.physmem.perBankWrBursts::6 8258 # Per bank write bursts -system.physmem.perBankWrBursts::7 8579 # Per bank write bursts -system.physmem.perBankWrBursts::8 7843 # Per bank write bursts -system.physmem.perBankWrBursts::9 8531 # Per bank write bursts -system.physmem.perBankWrBursts::10 7842 # Per bank write bursts -system.physmem.perBankWrBursts::11 6872 # Per bank write bursts -system.physmem.perBankWrBursts::12 7611 # Per bank write bursts -system.physmem.perBankWrBursts::13 8198 # Per bank write bursts -system.physmem.perBankWrBursts::14 7543 # Per bank write bursts -system.physmem.perBankWrBursts::15 7118 # Per bank write bursts +system.physmem.bw_total::cpu.inst 468351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3365516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6705765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 171884 # Number of read requests accepted +system.physmem.writeReqs 167423 # Number of write requests accepted +system.physmem.readBursts 171884 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 167423 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10992576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue +system.physmem.bytesWritten 10315392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10823668 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10452212 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6228 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4543 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10965 # Per bank write bursts +system.physmem.perBankRdBursts::1 10116 # Per bank write bursts +system.physmem.perBankRdBursts::2 11197 # Per bank write bursts +system.physmem.perBankRdBursts::3 11389 # Per bank write bursts +system.physmem.perBankRdBursts::4 13120 # Per bank write bursts +system.physmem.perBankRdBursts::5 10535 # Per bank write bursts +system.physmem.perBankRdBursts::6 11120 # Per bank write bursts +system.physmem.perBankRdBursts::7 11540 # Per bank write bursts +system.physmem.perBankRdBursts::8 10348 # Per bank write bursts +system.physmem.perBankRdBursts::9 11053 # Per bank write bursts +system.physmem.perBankRdBursts::10 10478 # Per bank write bursts +system.physmem.perBankRdBursts::11 9244 # Per bank write bursts +system.physmem.perBankRdBursts::12 10124 # Per bank write bursts +system.physmem.perBankRdBursts::13 10758 # Per bank write bursts +system.physmem.perBankRdBursts::14 10029 # Per bank write bursts +system.physmem.perBankRdBursts::15 9743 # Per bank write bursts +system.physmem.perBankWrBursts::0 10407 # Per bank write bursts +system.physmem.perBankWrBursts::1 9909 # Per bank write bursts +system.physmem.perBankWrBursts::2 10642 # Per bank write bursts +system.physmem.perBankWrBursts::3 10446 # Per bank write bursts +system.physmem.perBankWrBursts::4 9703 # Per bank write bursts +system.physmem.perBankWrBursts::5 10218 # Per bank write bursts +system.physmem.perBankWrBursts::6 10399 # Per bank write bursts +system.physmem.perBankWrBursts::7 10626 # Per bank write bursts +system.physmem.perBankWrBursts::8 10202 # Per bank write bursts +system.physmem.perBankWrBursts::9 10761 # Per bank write bursts +system.physmem.perBankWrBursts::10 9802 # Per bank write bursts +system.physmem.perBankWrBursts::11 9030 # Per bank write bursts +system.physmem.perBankWrBursts::12 9755 # Per bank write bursts +system.physmem.perBankWrBursts::13 10443 # Per bank write bursts +system.physmem.perBankWrBursts::14 9720 # Per bank write bursts +system.physmem.perBankWrBursts::15 9115 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 2826844140500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2827041948500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2993 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168617 # Read request sizes (log2) +system.physmem.readPktSize::6 168336 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126850 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 163042 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -162,156 +159,174 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.286868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.931959 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.707872 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23391 37.64% 37.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14782 23.79% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3679 5.92% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2602 4.19% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1126 1.81% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1130 1.82% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7555 12.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62147 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6420 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.793614 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.638433 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6418 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6420 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6420 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.834891 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.369444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.492928 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5612 87.41% 87.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 54 0.84% 88.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.20% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.23% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.26% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.06% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.05% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 167 2.60% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.16% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.08% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6420 # Writes before turning the bus around for reads -system.physmem.totQLat 2072280000 # Total ticks spent queuing -system.physmem.totMemAccLat 5297692500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 860110000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12046.60 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64399 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.873212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 190.977516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.816153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23539 36.55% 36.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14785 22.96% 59.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6319 9.81% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3687 5.73% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2636 4.09% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1562 2.43% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1140 1.77% 83.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1107 1.72% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9624 14.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64399 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6814 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.206340 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 540.339482 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6812 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6814 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6814 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.653948 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.805353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.459775 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5702 83.68% 83.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 39 0.57% 84.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.38% 84.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 231 3.39% 88.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 131 1.92% 89.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 61 0.90% 90.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 35 0.51% 91.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 27 0.40% 91.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 123 1.81% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 13 0.19% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 19 0.28% 94.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.16% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 31 0.45% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 13 0.19% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 13 0.19% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.38% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 61 0.90% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 10 0.15% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 9 0.13% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 11 0.16% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 89 1.31% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 7 0.10% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 18 0.26% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.06% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 5 0.07% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.06% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 26 0.38% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 4 0.06% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.06% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.07% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 11 0.16% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 11 0.16% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.04% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.04% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6814 # Writes before turning the bus around for reads +system.physmem.totQLat 2084525750 # Total ticks spent queuing +system.physmem.totMemAccLat 5305007000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 858795000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12136.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30796.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30886.34 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 3.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing -system.physmem.readRowHits 142002 # Number of row buffer hits during reads -system.physmem.writeRowHits 95212 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes -system.physmem.avgGap 9317341.50 # Average gap between requests -system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2694665773000 # Time in different power states -system.physmem.memoryStateTime::REF 94394300000 # Time in different power states +system.physmem.avgWrQLen 25.50 # Average write queue length when enqueuing +system.physmem.readRowHits 141721 # Number of row buffer hits during reads +system.physmem.writeRowHits 126816 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.67 # Row buffer hit rate for writes +system.physmem.avgGap 8331811.45 # Average gap between requests +system.physmem.pageHitRate 80.65 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2694668588500 # Time in different power states +system.physmem.memoryStateTime::REF 94401060000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37784264500 # Time in different power states +system.physmem.memoryStateTime::ACT 37972497000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 245987280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 223844040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134219250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122137125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 638851200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 80264555415 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79079779350 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625694839250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1626734116500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1892104031955 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1891832874855 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.336036 # Core power per rank (mW) -system.physmem.averagePower::1 669.240113 # Core power per rank (mW) +system.physmem.actEnergy::0 254499840 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 232356600 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 138864000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 126781875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 701859600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 637852800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 533628000 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 510805440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184648473360 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184648473360 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 80377758270 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 79142156730 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625717004000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1626800865000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1892372087070 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1892099291805 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.382923 # Core power per rank (mW) +system.physmem.averagePower::1 669.286428 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory @@ -330,15 +345,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46964274 # Number of BP lookups -system.cpu.branchPred.condPredicted 24050124 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232745 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29560624 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21375180 # Number of BTB hits +system.cpu.branchPred.lookups 46933448 # Number of BP lookups +system.cpu.branchPred.condPredicted 24039449 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232882 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29542848 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21360620 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.309637 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11765118 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.303862 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11754095 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33720 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -363,25 +378,25 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24601402 # DTB read hits -system.cpu.checker.dtb.read_misses 8241 # DTB read misses -system.cpu.checker.dtb.write_hits 19645330 # DTB write hits +system.cpu.checker.dtb.read_hits 24594187 # DTB read hits +system.cpu.checker.dtb.read_misses 8246 # DTB read misses +system.cpu.checker.dtb.write_hits 19641862 # DTB write hits system.cpu.checker.dtb.write_misses 1441 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 4295 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 4296 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1773 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1766 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24609643 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19646771 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24602433 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19643303 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44246732 # DTB hits -system.cpu.checker.dtb.misses 9682 # DTB misses -system.cpu.checker.dtb.accesses 44256414 # DTB accesses +system.cpu.checker.dtb.hits 44236049 # DTB hits +system.cpu.checker.dtb.misses 9687 # DTB misses +system.cpu.checker.dtb.accesses 44245736 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -403,7 +418,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 115909165 # ITB inst hits +system.cpu.checker.itb.inst_hits 115876249 # ITB inst hits system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -420,11 +435,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115913991 # ITB inst accesses -system.cpu.checker.itb.hits 115909165 # DTB hits +system.cpu.checker.itb.inst_accesses 115881075 # ITB inst accesses +system.cpu.checker.itb.hits 115876249 # DTB hits system.cpu.checker.itb.misses 4826 # DTB misses -system.cpu.checker.itb.accesses 115913991 # DTB accesses -system.cpu.checker.numCycles 139167829 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115881075 # DTB accesses +system.cpu.checker.numCycles 139127814 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -450,25 +465,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25471879 # DTB read hits -system.cpu.dtb.read_misses 60408 # DTB read misses -system.cpu.dtb.write_hits 19919747 # DTB write hits -system.cpu.dtb.write_misses 9388 # DTB write misses +system.cpu.dtb.read_hits 25465003 # DTB read hits +system.cpu.dtb.read_misses 60438 # DTB read misses +system.cpu.dtb.write_hits 19916425 # DTB write hits +system.cpu.dtb.write_misses 9382 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 344 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2309 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25532287 # DTB read accesses -system.cpu.dtb.write_accesses 19929135 # DTB write accesses +system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25525441 # DTB read accesses +system.cpu.dtb.write_accesses 19925807 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45391626 # DTB hits -system.cpu.dtb.misses 69796 # DTB misses -system.cpu.dtb.accesses 45461422 # DTB accesses +system.cpu.dtb.hits 45381428 # DTB hits +system.cpu.dtb.misses 69820 # DTB misses +system.cpu.dtb.accesses 45451248 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -490,8 +505,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 66240582 # ITB inst hits -system.cpu.itb.inst_misses 11936 # ITB inst misses +system.cpu.itb.inst_hits 66294026 # ITB inst hits +system.cpu.itb.inst_misses 11939 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -500,98 +515,98 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66252518 # ITB inst accesses -system.cpu.itb.hits 66240582 # DTB hits -system.cpu.itb.misses 11936 # DTB misses -system.cpu.itb.accesses 66252518 # DTB accesses -system.cpu.numCycles 260548868 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66305965 # ITB inst accesses +system.cpu.itb.hits 66294026 # DTB hits +system.cpu.itb.misses 11939 # DTB misses +system.cpu.itb.accesses 66305965 # DTB accesses +system.cpu.numCycles 260580731 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104909639 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184558460 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46964274 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33140298 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145575332 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6162234 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66240894 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254585351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104873538 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184739295 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46933448 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33114715 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145635789 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6158762 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 168952 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8750 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 338958 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 503648 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66294321 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1128854 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4994 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 254609122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.884999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.237560 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155338707 61.02% 61.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29243843 11.49% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14083345 5.53% 78.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55919456 21.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155317216 61.00% 61.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29235163 11.48% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14076452 5.53% 78.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55980291 21.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254585351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180251 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708345 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78108823 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105363724 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64680632 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3828797 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2603375 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485996 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157495015 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3691306 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2603375 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83949795 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10013130 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74489960 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62673363 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20855728 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146845952 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 950144 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 437842 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18093439 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150530803 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678954009 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164472740 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141875467 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8655333 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2847772 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2651529 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13851116 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26418132 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21304063 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1686589 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2099460 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143580575 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143376028 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 269119 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6250781 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14651223 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254585351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 254609122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180111 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.708952 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78085586 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105431733 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64660886 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3829260 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2601657 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422216 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 485978 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157447803 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3691485 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2601657 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83925210 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10033565 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74541150 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62655394 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20852146 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146807646 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 950357 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 437123 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62766 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16447 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18089237 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150492315 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678770164 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164434086 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141835122 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8657190 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2845976 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2649716 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13845319 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26411369 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21300781 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1686386 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2189128 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143541895 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2120957 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143337283 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269192 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6251828 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14653372 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125306 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 254609122 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.562970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.882443 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166207835 65.29% 65.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45306594 17.80% 83.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31956972 12.55% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10300343 4.05% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813574 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166344309 65.33% 65.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45117660 17.72% 83.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32035421 12.58% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10298180 4.04% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813519 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -599,9 +614,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254585351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254609122 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7371879 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7370311 32.63% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available @@ -630,13 +645,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632028 24.93% 57.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9586948 42.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5632420 24.93% 57.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9586874 42.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96038086 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113978 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96009315 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113982 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -660,100 +675,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26200986 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21012051 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26194290 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21008765 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143376028 # Type of FU issued -system.cpu.iq.rate 0.550285 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22590887 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157564 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564161758 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151957264 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140260479 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 143337283 # Type of FU issued +system.cpu.iq.rate 0.550069 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22589637 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157598 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564106761 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151919680 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140223084 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35756 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165941227 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 324401 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 165901147 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23436 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 324147 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1490308 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18271 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701002 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18251 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701176 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88081 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6304 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2603375 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 948323 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 290944 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145902361 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2601657 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 950737 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 291154 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145863821 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26418132 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21304063 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 256072 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18271 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317509 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471618 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789127 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142433599 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25799978 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872737 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26411369 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21300781 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096076 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17895 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 256263 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18251 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317548 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471732 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789280 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142394540 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25793108 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 873030 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200927 # number of nop insts executed -system.cpu.iew.exec_refs 46682549 # number of memory reference insts executed -system.cpu.iew.exec_branches 26544085 # Number of branches executed -system.cpu.iew.exec_stores 20882571 # Number of stores executed -system.cpu.iew.exec_rate 0.546668 # Inst execution rate -system.cpu.iew.wb_sent 142046516 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140271910 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63301578 # num instructions producing a value -system.cpu.iew.wb_consumers 95887209 # num instructions consuming a value +system.cpu.iew.exec_nop 200969 # number of nop insts executed +system.cpu.iew.exec_refs 46672402 # number of memory reference insts executed +system.cpu.iew.exec_branches 26533167 # Number of branches executed +system.cpu.iew.exec_stores 20879294 # Number of stores executed +system.cpu.iew.exec_rate 0.546451 # Inst execution rate +system.cpu.iew.wb_sent 142007306 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140234515 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63283849 # num instructions producing a value +system.cpu.iew.wb_consumers 95860591 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back +system.cpu.iew.wb_rate 0.538161 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7591975 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755003 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251649065 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.145555 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7591533 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995651 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755158 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251674404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.546055 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.146686 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178084267 70.77% 70.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43398054 17.25% 88.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15481884 6.15% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4357721 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1589357 0.63% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777637 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414343 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1083780 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178222235 70.81% 70.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43294364 17.20% 88.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15476639 6.15% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4357303 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6369018 2.53% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1679088 0.67% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777340 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414271 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1084146 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251649065 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113359701 # Number of instructions committed -system.cpu.commit.committedOps 137466321 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251674404 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113328647 # Number of instructions committed +system.cpu.commit.committedOps 137428168 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45531319 # Number of memory references committed -system.cpu.commit.loads 24928258 # Number of loads committed -system.cpu.commit.membars 814674 # Number of memory barriers committed -system.cpu.commit.branches 26060472 # Number of branches committed +system.cpu.commit.refs 45520666 # Number of memory references committed +system.cpu.commit.loads 24921061 # Number of loads committed +system.cpu.commit.membars 814701 # Number of memory barriers committed +system.cpu.commit.branches 26049415 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120282111 # Number of committed integer instructions. -system.cpu.commit.function_calls 4896381 # Number of function calls committed. +system.cpu.commit.int_insts 120247607 # Number of committed integer instructions. +system.cpu.commit.function_calls 4892692 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91813423 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91785919 66.79% 66.79% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction @@ -778,43 +793,43 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24928258 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20603061 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24921061 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20599605 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137466321 # Class of committed instruction -system.cpu.commit.bw_lim_events 1083780 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137428168 # Class of committed instruction +system.cpu.commit.bw_lim_events 1084146 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373370450 # The number of ROB reads -system.cpu.rob.rob_writes 293050441 # The number of ROB writes -system.cpu.timesIdled 892831 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5963517 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393139836 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113204796 # Number of Instructions Simulated -system.cpu.committedOps 137311416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.301571 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.301571 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155870535 # number of integer regfile reads -system.cpu.int_regfile_writes 88662744 # number of integer regfile writes -system.cpu.fp_regfile_reads 9591 # number of floating regfile reads +system.cpu.rob.rob_reads 373381031 # The number of ROB reads +system.cpu.rob.rob_writes 292971684 # The number of ROB writes +system.cpu.timesIdled 892930 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5971609 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393503589 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113173742 # Number of Instructions Simulated +system.cpu.committedOps 137273263 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.302484 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.302484 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434314 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434314 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155831391 # number of integer regfile reads +system.cpu.int_regfile_writes 88636025 # number of integer regfile writes +system.cpu.fp_regfile_reads 9607 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503158962 # number of cc regfile reads -system.cpu.cc_regfile_writes 53196475 # number of cc regfile writes -system.cpu.misc_regfile_reads 444136009 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes -system.cpu.dcache.tags.replacements 837744 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40170152 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838256 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.921103 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 503020698 # number of cc regfile reads +system.cpu.cc_regfile_writes 53185327 # number of cc regfile writes +system.cpu.misc_regfile_reads 444130548 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521619 # number of misc regfile writes +system.cpu.dcache.tags.replacements 837995 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958491 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40159583 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838507 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.894154 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958491 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -822,170 +837,170 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179419983 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179419983 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23329792 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23329792 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15588565 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15588565 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38918357 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38918357 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39265000 # number of overall hits -system.cpu.dcache.overall_hits::total 39265000 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700458 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700458 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3573865 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3573865 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179379502 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179379502 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23322864 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23322864 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15584894 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15584894 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346636 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346636 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 442009 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 442009 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460310 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460310 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38907758 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38907758 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39254394 # number of overall hits +system.cpu.dcache.overall_hits::total 39254394 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 700618 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 700618 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3574058 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3574058 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177109 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177109 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26740 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26740 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4274323 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4274323 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4451395 # number of overall misses -system.cpu.dcache.overall_misses::total 4451395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897569146 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9897569146 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 135184782788 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 135184782788 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357043749 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 357043749 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145082351934 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145082351934 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145082351934 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145082351934 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24030250 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24030250 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19162430 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19162430 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43192680 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43192680 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43716395 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43716395 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 4274676 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4274676 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4451785 # number of overall misses +system.cpu.dcache.overall_misses::total 4451785 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9939142148 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9939142148 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 135148977049 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 135148977049 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356483749 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 356483749 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 189500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 189500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145088119197 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145088119197 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145088119197 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145088119197 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24023482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24023482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19158952 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19158952 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523745 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523745 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468749 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468749 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460315 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460315 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43182434 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43182434 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43706179 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43706179 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029164 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029164 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186548 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186548 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338159 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.338159 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057045 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057045 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.139346 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.139346 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.934328 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.934328 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.918609 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.918609 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33942.767529 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33942.767529 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.558498 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32592.558498 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 504099 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.098991 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.098991 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.101857 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.101857 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14186.250065 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14186.250065 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37813.873488 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37813.873488 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13331.479020 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13331.479020 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 37900 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 37900 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.313727 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33941.313727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32590.998711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32590.998711 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 505021 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6926 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.762558 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.916691 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695413 # number of writebacks -system.cpu.dcache.writebacks::total 695413 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286304 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 286304 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274603 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3274603 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3560907 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3560907 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3560907 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3560907 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414154 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414154 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 695574 # number of writebacks +system.cpu.dcache.writebacks::total 695574 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286297 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 286297 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3274736 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18417 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18417 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3561033 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3561033 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3561033 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3561033 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414321 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414321 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299322 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299322 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119334 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119334 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8323 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8323 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 713416 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 713416 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 832722 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 832722 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5341815166 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5341815166 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883724205 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883724205 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479869001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479869001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225539371 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17225539371 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18705408372 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18705408372 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792724250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792724250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440459453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440459453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233183703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233183703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 713643 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713643 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 832977 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 832977 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5358688665 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5358688665 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11888843709 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11888843709 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1476460251 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1476460251 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110246000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110246000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 179500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 179500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17247532374 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17247532374 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18723992625 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18723992625 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792718250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792718250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233175703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233175703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017247 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017247 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015623 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227848 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227848 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017756 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017756 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.137326 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.137326 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39710.100865 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39710.100865 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.978015 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.978015 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.154259 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.154259 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.968880 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.968880 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016526 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016526 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019059 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019059 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12933.664152 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12933.664152 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39719.244523 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39719.244523 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12372.502816 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12372.502816 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.944972 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.944972 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 35900 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 35900 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24168.291953 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24168.291953 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22478.402915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22478.402915 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -993,13 +1008,13 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1894031 # number of replacements -system.cpu.icache.tags.tagsinuse 511.373814 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64256441 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1894543 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.916591 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1894210 # number of replacements +system.cpu.icache.tags.tagsinuse 511.373832 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64309690 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1894722 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.941491 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.373814 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.373832 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1008,250 +1023,250 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 170 system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68132454 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68132454 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64256441 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64256441 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64256441 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64256441 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64256441 # number of overall hits -system.cpu.icache.overall_hits::total 64256441 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1981452 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1981452 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1981452 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1981452 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1981452 # number of overall misses -system.cpu.icache.overall_misses::total 1981452 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26762198879 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26762198879 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26762198879 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26762198879 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26762198879 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26762198879 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66237893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66237893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66237893 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66237893 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66237893 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66237893 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.357398 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13506.357398 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13506.357398 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13506.357398 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1929 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68186062 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68186062 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64309690 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64309690 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64309690 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64309690 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64309690 # number of overall hits +system.cpu.icache.overall_hits::total 64309690 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1981630 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1981630 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1981630 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1981630 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1981630 # number of overall misses +system.cpu.icache.overall_misses::total 1981630 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26770075875 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26770075875 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26770075875 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26770075875 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26770075875 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26770075875 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66291320 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66291320 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66291320 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66291320 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66291320 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66291320 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029893 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029893 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029893 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029893 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029893 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029893 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13509.119197 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13509.119197 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13509.119197 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13509.119197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13509.119197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13509.119197 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1592 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 105 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 104 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.371429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.307692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86889 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 86889 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 86889 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 86889 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 86889 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 86889 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894563 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1894563 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1894563 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1894563 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1894563 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1894563 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22159944091 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22159944091 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22159944091 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22159944091 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22159944091 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22159944091 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86886 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 86886 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 86886 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 86886 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 86886 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 86886 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894744 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1894744 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1894744 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1894744 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1894744 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1894744 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22166113097 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22166113097 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22166113097 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22166113097 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22166113097 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22166113097 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.599211 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.599211 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028582 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.737717 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98619 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65077.788294 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3020947 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163832 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.439298 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 98615 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65077.693225 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3021592 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163828 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.443685 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540884 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798460 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612666 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617940 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.756264 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 49562.273815 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798544 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10309.775657 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5192.626837 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.756260 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157327 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.079218 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.993008 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157315 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.079233 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.993007 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65200 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2968 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7006 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55046 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2969 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7003 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55048 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 28437271 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 28437271 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53838 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11660 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1874564 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 528034 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2468096 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 695413 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 695413 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 34 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 34 # number of UpgradeReq hits +system.cpu.l2cache.tags.tag_accesses 28442992 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 28442992 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53902 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11707 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1874744 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 528230 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2468583 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 695574 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 695574 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179407 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060884 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000352 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000598 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179469 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060898 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179407 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060884 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62575.460107 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66847.886438 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64300.918596 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.417490 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.417490 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # 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average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59987.377561 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59987.377561 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1372,31 +1387,31 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2564949 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2565344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2565278 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695574 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2770 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795093 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495164 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128717 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6450154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121297808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349473 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215428 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219909377 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65488 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3561849 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9.010233 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296684 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296684 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795456 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495832 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128794 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6451318 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121309456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98375777 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215684 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219947773 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65392 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3562462 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9.010230 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100625 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram @@ -1407,28 +1422,29 @@ system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 3525400 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 36449 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 3526018 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 36444 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3561849 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2502926529 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3562462 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2503396529 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849434655 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2849706150 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334430859 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1334755109 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19527240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74882707 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74897454 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30181 # Transaction distribution system.iobus.trans_dist::ReadResp 30181 # Transaction distribution system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1519,42 +1535,44 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347066130 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36776516 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.000725 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.999676 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 251942535000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000725 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062545 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062545 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327996 # Number of tag accesses system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses system.iocache.demand_misses::total 220 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 220 # number of overall misses system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26406377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26406377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26406377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26406377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26406377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26406377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 26411377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 26411377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9622478237 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9622478237 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 26411377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 26411377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 26411377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 26411377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1565,104 +1583,114 @@ system.iocache.overall_accesses::realview.ide 220 system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120028.986364 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120028.986364 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120028.986364 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120028.986364 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 120051.713636 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120051.713636 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265638.202214 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265638.202214 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120051.713636 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120051.713636 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56749 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7275 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.800550 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14965377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14965377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2230292235 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2230292235 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14965377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14965377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14965377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14965377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 14970377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14970377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7738798269 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7738798269 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 14970377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14970377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 14970377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14970377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68024.440909 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68024.440909 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68047.168182 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68047.168182 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213637.319705 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213637.319705 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 67834 # Transaction distribution -system.membus.trans_dist::ReadResp 67833 # Transaction distribution +system.membus.trans_dist::ReadReq 67832 # Transaction distribution +system.membus.trans_dist::ReadResp 67831 # Transaction distribution system.membus.trans_dist::WriteReq 27608 # Transaction distribution system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 90626 # Transaction distribution +system.membus.trans_dist::Writeback 126818 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution -system.membus.trans_dist::ReadExReq 135127 # Transaction distribution -system.membus.trans_dist::ReadExResp 135127 # Transaction distribution +system.membus.trans_dist::ReadExReq 135125 # Transaction distribution +system.membus.trans_dist::ReadExResp 135125 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452492 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 669001 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 205 # Total snoops (count) -system.membus.snoop_fanout::samples 300222 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16640360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16803825 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21439281 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 484 # Total snoops (count) +system.membus.snoop_fanout::samples 336405 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 336405 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 300222 # Request fanout histogram -system.membus.reqLayer0.occupancy 94200000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 336405 # Request fanout histogram +system.membus.reqLayer0.occupancy 94190000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1697000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1357984749 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1678025205 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1683660499 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 1677935457 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38220484 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1696,6 +1724,6 @@ system.realview.ethernet.coalescedTotal nan # av system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index b13980f34..8bea05f5e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,169 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.824366 # Number of seconds simulated -sim_ticks 2824365837500 # Number of ticks simulated -final_tick 2824365837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.824570 # Number of seconds simulated +sim_ticks 2824570221000 # Number of ticks simulated +final_tick 2824570221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93434 # Simulator instruction rate (inst/s) -host_op_rate 113356 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2196532158 # Simulator tick rate (ticks/s) -host_mem_usage 669668 # Number of bytes of host memory used -host_seconds 1285.83 # Real time elapsed on the host -sim_insts 120140086 # Number of instructions simulated -sim_ops 145755972 # Number of ops (including micro ops) simulated +host_inst_rate 42227 # Simulator instruction rate (inst/s) +host_op_rate 51230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 992732164 # Simulator tick rate (ticks/s) +host_mem_usage 776620 # Number of bytes of host memory used +host_seconds 2845.25 # Real time elapsed on the host +sim_insts 120145307 # Number of instructions simulated +sim_ops 145762315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 286496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1047804 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10514048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 286752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1037180 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10498560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 32208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 549728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1343808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 549024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1342912 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 13778252 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 286496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 32208 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 13750604 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 286752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31952 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 318704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7259968 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 9574272 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 9596048 # Number of bytes written to this memory +system.physmem.bytes_written::total 9592016 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6722 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 16897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 164282 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6726 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 16731 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 164040 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 570 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 20997 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 566 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8602 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 20983 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 218146 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 113437 # Number of write requests responded to by this memory +system.physmem.num_reads::total 217714 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149598 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 154097 # Number of write requests responded to by this memory +system.physmem.num_writes::total 154034 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 101437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 370987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3722623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 101521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 367199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3716870 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 11404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 194638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 475791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 11312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 194374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 475439 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4878352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 101437 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11404 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 112841 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2570477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4868211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 101521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112833 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3389639 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 820834 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3397594 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2570477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3395921 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3389639 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 101437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 377256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3722623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 101521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 373467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3716870 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 11404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 194652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 475791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 821174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8275946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 218146 # Number of read requests accepted -system.physmem.writeReqs 154097 # Number of write requests accepted -system.physmem.readBursts 218146 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 154097 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13946112 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 15232 # Total number of bytes read from write queue -system.physmem.bytesWritten 9610368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 13778252 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9596048 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 238 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13753 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 13737 # Per bank write bursts -system.physmem.perBankRdBursts::1 13637 # Per bank write bursts -system.physmem.perBankRdBursts::2 14389 # Per bank write bursts -system.physmem.perBankRdBursts::3 14286 # Per bank write bursts -system.physmem.perBankRdBursts::4 15951 # Per bank write bursts -system.physmem.perBankRdBursts::5 13008 # Per bank write bursts -system.physmem.perBankRdBursts::6 13922 # Per bank write bursts -system.physmem.perBankRdBursts::7 13905 # Per bank write bursts -system.physmem.perBankRdBursts::8 13614 # Per bank write bursts -system.physmem.perBankRdBursts::9 13369 # Per bank write bursts -system.physmem.perBankRdBursts::10 12796 # Per bank write bursts -system.physmem.perBankRdBursts::11 11719 # Per bank write bursts -system.physmem.perBankRdBursts::12 13344 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 11312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 194389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 475439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8264132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 217714 # Number of read requests accepted +system.physmem.writeReqs 190258 # Number of write requests accepted +system.physmem.readBursts 217714 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 190258 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13924352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 11782272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 13750604 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11910352 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6131 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13778 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 13720 # Per bank write bursts +system.physmem.perBankRdBursts::1 13621 # Per bank write bursts +system.physmem.perBankRdBursts::2 14360 # Per bank write bursts +system.physmem.perBankRdBursts::3 14230 # Per bank write bursts +system.physmem.perBankRdBursts::4 15917 # Per bank write bursts +system.physmem.perBankRdBursts::5 12969 # Per bank write bursts +system.physmem.perBankRdBursts::6 13917 # Per bank write bursts +system.physmem.perBankRdBursts::7 13922 # Per bank write bursts +system.physmem.perBankRdBursts::8 13602 # Per bank write bursts +system.physmem.perBankRdBursts::9 13356 # Per bank write bursts +system.physmem.perBankRdBursts::10 12792 # Per bank write bursts +system.physmem.perBankRdBursts::11 11688 # Per bank write bursts +system.physmem.perBankRdBursts::12 13275 # Per bank write bursts system.physmem.perBankRdBursts::13 14168 # Per bank write bursts -system.physmem.perBankRdBursts::14 13355 # Per bank write bursts -system.physmem.perBankRdBursts::15 12708 # Per bank write bursts -system.physmem.perBankWrBursts::0 9678 # Per bank write bursts -system.physmem.perBankWrBursts::1 9778 # Per bank write bursts -system.physmem.perBankWrBursts::2 10288 # Per bank write bursts -system.physmem.perBankWrBursts::3 9945 # Per bank write bursts -system.physmem.perBankWrBursts::4 9066 # Per bank write bursts -system.physmem.perBankWrBursts::5 9050 # Per bank write bursts -system.physmem.perBankWrBursts::6 9464 # Per bank write bursts -system.physmem.perBankWrBursts::7 9420 # Per bank write bursts -system.physmem.perBankWrBursts::8 9418 # Per bank write bursts -system.physmem.perBankWrBursts::9 9295 # Per bank write bursts -system.physmem.perBankWrBursts::10 9149 # Per bank write bursts -system.physmem.perBankWrBursts::11 8660 # Per bank write bursts -system.physmem.perBankWrBursts::12 9452 # Per bank write bursts -system.physmem.perBankWrBursts::13 9588 # Per bank write bursts -system.physmem.perBankWrBursts::14 9180 # Per bank write bursts -system.physmem.perBankWrBursts::15 8731 # Per bank write bursts +system.physmem.perBankRdBursts::14 13342 # Per bank write bursts +system.physmem.perBankRdBursts::15 12689 # Per bank write bursts +system.physmem.perBankWrBursts::0 11837 # Per bank write bursts +system.physmem.perBankWrBursts::1 11937 # Per bank write bursts +system.physmem.perBankWrBursts::2 12245 # Per bank write bursts +system.physmem.perBankWrBursts::3 12130 # Per bank write bursts +system.physmem.perBankWrBursts::4 11220 # Per bank write bursts +system.physmem.perBankWrBursts::5 11075 # Per bank write bursts +system.physmem.perBankWrBursts::6 11642 # Per bank write bursts +system.physmem.perBankWrBursts::7 11554 # Per bank write bursts +system.physmem.perBankWrBursts::8 11490 # Per bank write bursts +system.physmem.perBankWrBursts::9 11375 # Per bank write bursts +system.physmem.perBankWrBursts::10 11404 # Per bank write bursts +system.physmem.perBankWrBursts::11 11050 # Per bank write bursts +system.physmem.perBankWrBursts::12 11716 # Per bank write bursts +system.physmem.perBankWrBursts::13 11527 # Per bank write bursts +system.physmem.perBankWrBursts::14 11100 # Per bank write bursts +system.physmem.perBankWrBursts::15 10796 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 2824364779500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2824568625000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3083 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 214476 # Read request sizes (log2) +system.physmem.readPktSize::6 214044 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149661 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 53531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 76693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20729 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2475 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1095 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 185822 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 53286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 76786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 636 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -191,152 +188,172 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9241 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 13286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 12907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 12909 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 253.712882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.703009 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 308.429657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46968 50.59% 50.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18903 20.36% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6762 7.28% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3669 3.95% 82.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3165 3.41% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2101 2.26% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1261 1.36% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1081 1.16% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8937 9.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92847 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7530 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.938645 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 528.498472 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7529 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 95193 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 270.047419 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 149.647814 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.885603 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47290 49.68% 49.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18811 19.76% 69.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6810 7.15% 76.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3608 3.79% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3189 3.35% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2125 2.23% 85.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1286 1.35% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1091 1.15% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10983 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 95193 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7956 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.345777 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 514.192665 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7955 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7530 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7530 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.941833 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.646034 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.689402 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6119 81.26% 81.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 568 7.54% 88.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 91 1.21% 90.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 218 2.90% 92.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 217 2.88% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 12 0.16% 95.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 20 0.27% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 25 0.33% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 26 0.35% 96.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.11% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.08% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.07% 97.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 157 2.08% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.09% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.11% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.05% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.17% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 6 0.08% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.09% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7530 # Writes before turning the bus around for reads -system.physmem.totQLat 8946488000 # Total ticks spent queuing -system.physmem.totMemAccLat 13032263000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1089540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 41056.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7956 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7956 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.139517 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.869319 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.452539 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6216 78.13% 78.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 561 7.05% 85.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 92 1.16% 86.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 246 3.09% 89.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 152 1.91% 91.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 55 0.69% 92.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 34 0.43% 92.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 37 0.47% 92.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 126 1.58% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.23% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 19 0.24% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.11% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 35 0.44% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 15 0.19% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.11% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 35 0.44% 96.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 47 0.59% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 11 0.14% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 5 0.06% 97.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 9 0.11% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 88 1.11% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 8 0.10% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 17 0.21% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 6 0.08% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 8 0.10% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.04% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 29 0.36% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 10 0.13% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.05% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.09% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 7 0.09% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 5 0.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 6 0.08% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.01% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7956 # Writes before turning the bus around for reads +system.physmem.totQLat 8935367250 # Total ticks spent queuing +system.physmem.totMemAccLat 13014767250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1087840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 41069.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 59806.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.40 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 59819.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.93 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.08 # Average write queue length when enqueuing -system.physmem.readRowHits 185273 # Number of row buffer hits during reads -system.physmem.writeRowHits 89950 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.89 # Row buffer hit rate for writes -system.physmem.avgGap 7587422.14 # Average gap between requests -system.physmem.pageHitRate 74.77 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2697372741500 # Time in different power states -system.physmem.memoryStateTime::REF 94311620000 # Time in different power states +system.physmem.avgRdQLen 2.29 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.31 # Average write queue length when enqueuing +system.physmem.readRowHits 184937 # Number of row buffer hits during reads +system.physmem.writeRowHits 121536 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.01 # Row buffer hit rate for writes +system.physmem.avgGap 6923437.45 # Average gap between requests +system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2697464747500 # Time in different power states +system.physmem.memoryStateTime::REF 94318380000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 32676864750 # Time in different power states +system.physmem.memoryStateTime::ACT 32780541250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 364906080 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 337017240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 199105500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 183888375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 880113000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 819569400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 496944720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 476105040 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184473528720 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184473528720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 78935898240 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 78466357035 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625374711500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1625786589750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1890725207760 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1890543055560 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.434632 # Core power per rank (mW) -system.physmem.averagePower::1 669.370138 # Core power per rank (mW) +system.physmem.actEnergy::0 374477040 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 345182040 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 204327750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 188343375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 878716800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 818313600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 606787200 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 586167840 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184486751280 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184486751280 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 79037968995 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 78368155155 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625406641250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1625994197250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1890995670315 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1890787110540 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.482406 # Core power per rank (mW) +system.physmem.averagePower::1 669.408568 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory @@ -361,15 +378,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 24027931 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15718166 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 977317 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 14657289 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10772949 # Number of BTB hits +system.cpu0.branchPred.lookups 24032454 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15719473 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 977282 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 14661590 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 10774814 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.498919 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3877670 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32392 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.490078 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3879582 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32449 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -394,25 +411,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17722563 # DTB read hits -system.cpu0.dtb.read_misses 56347 # DTB read misses -system.cpu0.dtb.write_hits 14648246 # DTB write hits -system.cpu0.dtb.write_misses 8736 # DTB write misses +system.cpu0.dtb.read_hits 17723797 # DTB read hits +system.cpu0.dtb.read_misses 56461 # DTB read misses +system.cpu0.dtb.write_hits 14648555 # DTB write hits +system.cpu0.dtb.write_misses 8741 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3529 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 316 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2360 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3527 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 309 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2355 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 858 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17778910 # DTB read accesses -system.cpu0.dtb.write_accesses 14656982 # DTB write accesses +system.cpu0.dtb.perms_faults 868 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17780258 # DTB read accesses +system.cpu0.dtb.write_accesses 14657296 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32370809 # DTB hits -system.cpu0.dtb.misses 65083 # DTB misses -system.cpu0.dtb.accesses 32435892 # DTB accesses +system.cpu0.dtb.hits 32372352 # DTB hits +system.cpu0.dtb.misses 65202 # DTB misses +system.cpu0.dtb.accesses 32437554 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -434,8 +451,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 37749898 # ITB inst hits -system.cpu0.itb.inst_misses 10270 # ITB inst misses +system.cpu0.itb.inst_hits 37754755 # ITB inst hits +system.cpu0.itb.inst_misses 10287 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -444,108 +461,108 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2361 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2369 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1943 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1949 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37760168 # ITB inst accesses -system.cpu0.itb.hits 37749898 # DTB hits -system.cpu0.itb.misses 10270 # DTB misses -system.cpu0.itb.accesses 37760168 # DTB accesses -system.cpu0.numCycles 126937172 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 37765042 # ITB inst accesses +system.cpu0.itb.hits 37754755 # DTB hits +system.cpu0.itb.misses 10287 # DTB misses +system.cpu0.itb.accesses 37765042 # DTB accesses +system.cpu0.numCycles 126967483 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 18140410 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 112713647 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 24027931 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 14650619 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 104775763 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2822832 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 131776 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 38634 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 364177 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 430173 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 37568 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 37750515 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 265085 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3932 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 125329917 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.084963 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.263075 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 18140354 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 112726031 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 24032454 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 14654396 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 104803073 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2823208 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 134368 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 38414 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 364228 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 430065 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 37874 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 37755386 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 265155 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3922 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 125359980 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.084816 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.263057 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 62773644 50.09% 50.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 21461872 17.12% 67.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8766803 6.99% 74.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 32327598 25.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 62797458 50.09% 50.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 21463892 17.12% 67.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8767294 6.99% 74.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 32331336 25.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 125329917 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.189290 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.887948 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19211260 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58677383 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 41416135 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4957927 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1067212 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3055574 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 348409 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 110727822 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3998029 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1067212 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24961632 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12004838 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 36556596 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 40485229 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10254410 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 105647594 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1060765 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1435224 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 161199 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 61281 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6055537 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 109729609 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 482383818 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 120922156 # Number of integer rename lookups +system.cpu0.fetch.rateDist::total 125359980 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.189280 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.887834 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19213877 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58702572 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 41417912 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4958150 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1067469 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3055480 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 348347 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 110732586 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3998245 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1067469 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24964892 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12028946 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 36555738 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 40486723 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10256212 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 105650222 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1060720 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1433198 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 161272 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 61252 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6057790 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 109732658 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 482396625 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 120923658 # Number of integer rename lookups system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 98138163 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11591443 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1228785 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1087461 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12318010 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 18735902 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 16202980 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1699572 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2289990 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 102687216 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1694558 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 100671408 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 483936 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9020941 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22487287 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 122833 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 125329917 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.803251 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.034851 # Number of insts issued each cycle +system.cpu0.rename.CommittedMaps 98143798 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11588857 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1229050 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1087734 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12319550 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18736791 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 16202841 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1700720 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2277601 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 102690318 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1694621 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 100676052 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 483863 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9017764 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22481770 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 122874 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 125359980 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.803096 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.034807 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 69186063 55.20% 55.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 23179586 18.49% 73.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 22515563 17.97% 91.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 9334163 7.45% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1114503 0.89% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 39 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 69212985 55.21% 55.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 23181797 18.49% 73.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 22515986 17.96% 91.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 9334603 7.45% 99.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1114571 0.89% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 38 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 125329917 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 125359980 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 9379139 40.75% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 9379077 40.75% 40.75% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 80 0.00% 40.75% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available @@ -574,15 +591,15 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5583986 24.26% 65.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8051096 34.98% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5582793 24.26% 65.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8054863 35.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 66410061 65.97% 65.97% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 93146 0.09% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 66413118 65.97% 65.97% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 93141 0.09% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued @@ -604,101 +621,101 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8111 0.01% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8113 0.01% 66.07% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 18430824 18.31% 84.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 15726990 15.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18432239 18.31% 84.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 15727166 15.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 100671408 # Type of FU issued -system.cpu0.iq.rate 0.793081 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 23014301 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228608 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 350139117 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 113410576 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 98583429 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 31853 # Number of floating instruction queue reads +system.cpu0.iq.FU_type_0::total 100676052 # Type of FU issued +system.cpu0.iq.rate 0.792928 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 23016813 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228623 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 350180984 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 113410550 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 98587478 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 31776 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9723 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 123662855 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 20581 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 365420 # Number of loads that had data forwarded from stores +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9721 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 123670062 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 20530 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 365459 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2006460 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2583 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19225 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1022371 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2006136 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2602 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19208 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1021760 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 106487 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 336614 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 106419 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 336961 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1067212 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1617559 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 190582 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 104556500 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1067469 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1620814 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 189225 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 104559654 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 18735902 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 16202980 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 876211 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27258 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 139659 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19225 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 291750 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 400567 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 692317 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 99574081 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 17974103 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1032379 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 18736791 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 16202841 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 876235 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27148 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 138418 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19208 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 291783 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 400552 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 692335 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 99578675 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 17975392 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1032310 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 174726 # number of nop insts executed -system.cpu0.iew.exec_refs 33509859 # number of memory reference insts executed -system.cpu0.iew.exec_branches 16843488 # Number of branches executed -system.cpu0.iew.exec_stores 15535756 # Number of stores executed -system.cpu0.iew.exec_rate 0.784436 # Inst execution rate -system.cpu0.iew.wb_sent 99043344 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 98593152 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 51321674 # num instructions producing a value -system.cpu0.iew.wb_consumers 84801576 # num instructions consuming a value +system.cpu0.iew.exec_nop 174715 # number of nop insts executed +system.cpu0.iew.exec_refs 33511345 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16844732 # Number of branches executed +system.cpu0.iew.exec_stores 15535953 # Number of stores executed +system.cpu0.iew.exec_rate 0.784285 # Inst execution rate +system.cpu0.iew.wb_sent 99047596 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 98597199 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 51323656 # num instructions producing a value +system.cpu0.iew.wb_consumers 84802398 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.776708 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.605197 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.776555 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.605215 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 8525747 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1571725 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 633113 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 123576047 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.768210 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.481297 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 8524425 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1571747 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 633147 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 123606126 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.768066 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.480848 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 79251877 64.13% 64.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 24711108 20.00% 84.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 8248464 6.67% 90.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3214478 2.60% 93.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3439388 2.78% 96.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1513562 1.22% 97.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1143910 0.93% 98.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 534023 0.43% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1519237 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 79269760 64.13% 64.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 24721020 20.00% 84.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 8248963 6.67% 90.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3214548 2.60% 93.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3440916 2.78% 96.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1523839 1.23% 97.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1135185 0.92% 98.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 534039 0.43% 98.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1517856 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 123576047 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 78902307 # Number of instructions committed -system.cpu0.commit.committedOps 94932349 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 123606126 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 78906627 # Number of instructions committed +system.cpu0.commit.committedOps 94937680 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 31910051 # Number of memory references committed -system.cpu0.commit.loads 16729442 # Number of loads committed -system.cpu0.commit.membars 647161 # Number of memory barriers committed -system.cpu0.commit.branches 16205593 # Number of branches committed +system.cpu0.commit.refs 31911736 # Number of memory references committed +system.cpu0.commit.loads 16730655 # Number of loads committed +system.cpu0.commit.membars 647181 # Number of memory barriers committed +system.cpu0.commit.branches 16206992 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 81881586 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1929479 # Number of function calls committed. +system.cpu0.commit.int_insts 81886422 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1929931 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 62923469 66.28% 66.28% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 90718 0.10% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 62927104 66.28% 66.28% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 90727 0.10% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction @@ -722,222 +739,222 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8111 0.01% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8113 0.01% 66.39% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 16729442 17.62% 84.01% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 15180609 15.99% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 16730655 17.62% 84.01% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 15181081 15.99% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 94932349 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1519237 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 94937680 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1517856 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 221333052 # The number of ROB reads -system.cpu0.rob.rob_writes 208669303 # The number of ROB writes -system.cpu0.timesIdled 109478 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 1607255 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5521794529 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 78780256 # Number of Instructions Simulated -system.cpu0.committedOps 94810298 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.611282 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.611282 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.620624 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.620624 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 110616528 # number of integer regfile reads -system.cpu0.int_regfile_writes 59738270 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8164 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes -system.cpu0.cc_regfile_reads 350776322 # number of cc regfile reads -system.cpu0.cc_regfile_writes 41073406 # number of cc regfile writes -system.cpu0.misc_regfile_reads 245816614 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1224552 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 712837 # number of replacements -system.cpu0.dcache.tags.tagsinuse 493.082878 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28842463 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 713349 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.432471 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 221365586 # The number of ROB reads +system.cpu0.rob.rob_writes 208677314 # The number of ROB writes +system.cpu0.timesIdled 109557 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1607503 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5522172985 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 78784576 # Number of Instructions Simulated +system.cpu0.committedOps 94815629 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.611578 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.611578 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.620510 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.620510 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 110621221 # number of integer regfile reads +system.cpu0.int_regfile_writes 59741549 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8143 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes +system.cpu0.cc_regfile_reads 350793071 # number of cc regfile reads +system.cpu0.cc_regfile_writes 41074475 # number of cc regfile writes +system.cpu0.misc_regfile_reads 246484638 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1224545 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 712867 # number of replacements +system.cpu0.dcache.tags.tagsinuse 493.083932 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28844186 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 713379 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.433186 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.082878 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.083932 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963055 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.963055 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63484078 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63484078 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15589241 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15589241 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 12071944 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 12071944 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 310964 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 310964 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363200 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363200 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360654 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 360654 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27661185 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27661185 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 27972149 # number of overall hits -system.cpu0.dcache.overall_hits::total 27972149 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 638343 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 638343 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1832165 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1832165 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146120 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 146120 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20612 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20612 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2470508 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2470508 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2616628 # number of overall misses -system.cpu0.dcache.overall_misses::total 2616628 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8099233830 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8099233830 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24956974532 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24956974532 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395327755 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 395327755 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453888287 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 453888287 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 344500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 344500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 33056208362 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 33056208362 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 33056208362 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 33056208362 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16227584 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16227584 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904109 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13904109 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457084 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 457084 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388176 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388176 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381266 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381266 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30131693 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30131693 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30588777 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30588777 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039337 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039337 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131771 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.131771 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319679 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319679 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064342 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064342 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054062 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054062 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081990 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.081990 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085542 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.085542 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12687.902632 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12687.902632 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13621.575858 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 13621.575858 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15828.305373 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15828.305373 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22020.584465 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22020.584465 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63487140 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63487140 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15590249 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15590249 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 12072536 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 12072536 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311110 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 311110 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363193 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363193 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360660 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 360660 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27662785 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27662785 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 27973895 # number of overall hits +system.cpu0.dcache.overall_hits::total 27973895 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 638253 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 638253 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1832121 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1832121 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146008 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 146008 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25001 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25001 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20609 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20609 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2470374 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2470374 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2616382 # number of overall misses +system.cpu0.dcache.overall_misses::total 2616382 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8112547038 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8112547038 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24972133492 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24972133492 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 394969003 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 394969003 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454279790 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 454279790 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 381000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 381000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 33084680530 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 33084680530 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 33084680530 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 33084680530 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16228502 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16228502 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904657 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13904657 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457118 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 457118 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388194 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388194 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381269 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381269 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30133159 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30133159 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30590277 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30590277 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039329 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.039329 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131763 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.131763 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319410 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319410 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064403 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064403 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054054 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054054 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081982 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.081982 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085530 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.085530 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.550578 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.550578 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13630.176987 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 13630.176987 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15798.128195 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15798.128195 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22042.786647 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22042.786647 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13380.328403 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13380.328403 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12633.132552 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12633.132552 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1355 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3366874 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 70 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 191323 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.357143 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 17.597853 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13392.579638 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13392.579638 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12645.202623 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12645.202623 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1345 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3372122 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 71 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 191319 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.943662 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 17.625651 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 513073 # number of writebacks -system.cpu0.dcache.writebacks::total 513073 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248142 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 248142 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519584 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1519584 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18421 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18421 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767726 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1767726 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767726 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1767726 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390201 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 390201 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312581 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 312581 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101511 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 101511 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6555 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6555 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20612 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20612 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 702782 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 702782 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 804293 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 804293 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4170777489 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4170777489 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4999843092 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4999843092 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1415062493 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1415062493 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97847997 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97847997 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411963713 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 411963713 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 324500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 324500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9170620581 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9170620581 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10585683074 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10585683074 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4217063246 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4217063246 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187063995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187063995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7404127241 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7404127241 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024046 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024046 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022481 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022481 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222084 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222084 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016887 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016887 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054062 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054062 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023324 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023324 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026294 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026294 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10688.792415 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10688.792415 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15995.351899 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15995.351899 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13939.991656 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13939.991656 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14927.230664 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14927.230664 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19986.595818 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19986.595818 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 512814 # number of writebacks +system.cpu0.dcache.writebacks::total 512814 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248043 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 248043 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519569 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1519569 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18426 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18426 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767612 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1767612 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767612 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1767612 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390210 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 390210 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312552 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312552 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101508 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 101508 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6575 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6575 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20609 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20609 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 702762 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 702762 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 804270 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 804270 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4184101504 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4184101504 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5001279356 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5001279356 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1410085492 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1410085492 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97668747 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97668747 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 412365210 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 412365210 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 359000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 359000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9185380860 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9185380860 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10595466352 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10595466352 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4216928747 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4216928747 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3186876498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3186876498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7403805245 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7403805245 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024045 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024045 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022478 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022478 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222061 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222061 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016937 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016937 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054054 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054054 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023322 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023322 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026292 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026292 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10722.691638 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10722.691638 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16001.431301 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16001.431301 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13891.373015 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13891.373015 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14854.562281 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14854.562281 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20008.986850 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20008.986850 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13049.025987 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13049.025987 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13161.476072 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13161.476072 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13070.400591 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13070.400591 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13174.016626 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13174.016626 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -945,427 +962,420 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1263629 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.774279 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36446507 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1264141 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.831046 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1263628 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.774293 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36451354 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1264140 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.834903 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774279 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774293 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 76758780 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 76758780 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 36446507 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36446507 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36446507 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36446507 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36446507 # number of overall hits -system.cpu0.icache.overall_hits::total 36446507 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1300794 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1300794 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1300794 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1300794 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1300794 # number of overall misses -system.cpu0.icache.overall_misses::total 1300794 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11016728605 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11016728605 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11016728605 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11016728605 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11016728605 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11016728605 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 37747301 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 37747301 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 37747301 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 37747301 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 37747301 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 37747301 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034461 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034461 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034461 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034461 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034461 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034461 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8469.233872 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8469.233872 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8469.233872 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8469.233872 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8469.233872 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8469.233872 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 724171 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 76768570 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 76768570 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36451354 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36451354 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36451354 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36451354 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36451354 # number of overall hits +system.cpu0.icache.overall_hits::total 36451354 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1300843 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1300843 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1300843 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1300843 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1300843 # number of overall misses +system.cpu0.icache.overall_misses::total 1300843 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11016228057 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11016228057 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11016228057 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11016228057 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11016228057 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11016228057 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37752197 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37752197 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37752197 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37752197 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37752197 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37752197 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034457 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.034457 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034457 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.034457 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034457 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.034457 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8468.530066 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8468.530066 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8468.530066 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8468.530066 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8468.530066 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8468.530066 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 721640 # 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number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8918143809 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8918143809 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8918143809 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8918143809 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36666 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 36666 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 36666 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 36666 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 36666 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 36666 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264177 # 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number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244130748 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 244130748 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033491 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033491 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033491 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.494505 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.494505 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.494505 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033486 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033486 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033486 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033486 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033486 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033486 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.281981 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.281981 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.281981 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.281981 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.281981 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.281981 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11567606 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525705 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10416149 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118627 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11568415 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525589 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10417206 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118474 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25546 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 481574 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 882370 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25510 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 481631 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881553 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 396542 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16205.769061 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2244815 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 412792 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.438126 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2809084521500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4618.987809 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 8.979975 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 2.443926 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 942.112111 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1410.719068 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9222.526172 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.281921 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000548 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000149 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.057502 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086103 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.562898 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989122 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8075 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8170 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 46 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 189 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3306 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4046 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 488 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 491 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3813 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3549 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 254 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.492859 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.498657 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 43582688 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 43582688 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54105 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12184 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242379 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 407374 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1716042 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 513072 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 513072 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15340 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 15340 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2133 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2133 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216716 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 216716 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54105 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12184 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1242379 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 624090 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1932758 # 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mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016704 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7093849178 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312562928 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009922 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015945 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.175860 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057167 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.175694 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057105 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.645711 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.645711 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.896517 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.896517 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163093 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163093 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009683 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016704 # mshr miss rate for demand accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.645932 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.645932 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.897521 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.897521 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163160 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163160 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009922 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015945 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171378 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070767 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009683 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016704 # mshr miss rate for overall accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171294 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070716 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009922 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015945 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171378 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171294 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.300217 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36181.618810 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22931.145641 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24957.897062 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45602.758858 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45602.758858 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17233.989091 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17233.989091 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13486.538395 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13486.538395 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.300100 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36232.893385 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23035.645199 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25055.367788 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45584.105017 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.482661 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.482661 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13495.796237 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13495.796237 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29984.001024 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29984.001024 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36181.618810 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25287.315617 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26445.116511 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36181.618810 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25287.315617 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45602.758858 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41086.910300 # average overall mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 30024.896989 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 30024.896989 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36232.893385 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25372.553683 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26526.881263 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36232.893385 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25372.553683 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41093.419955 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1375,67 +1385,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2021884 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1920690 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19107 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19107 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 513073 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 646583 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 80962 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43193 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 104964 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 2021847 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1920670 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19105 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19105 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 512814 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 646384 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 80933 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43154 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 104914 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 291894 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 281156 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2534332 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360691 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28712 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120464 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5044199 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80953568 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86204446 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 49568 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 218536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 167426118 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1040274 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3610797 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.254659 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.435670 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 291875 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 281146 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2534329 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360353 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29069 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120916 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5044667 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80953504 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86188042 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50924 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 220524 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 167412994 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1039110 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3610193 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.254626 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.435651 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2691274 74.53% 74.53% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 919523 25.47% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2690945 74.54% 74.54% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 919248 25.46% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3610797 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1890423984 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3610193 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1889992000 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 117333499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 117303500 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1901305348 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1901297082 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1220101128 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1220075844 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 16329482 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 16351973 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 65866183 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 65816442 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 33911271 # Number of BP lookups -system.cpu1.branchPred.condPredicted 11563003 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 305102 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 18755199 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 14959397 # Number of BTB hits +system.cpu1.branchPred.lookups 33910806 # Number of BP lookups +system.cpu1.branchPred.condPredicted 11562772 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 305112 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 18755942 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 14959399 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.761334 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12490268 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7230 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 79.758185 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12490105 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7221 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1459,25 +1469,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10163694 # DTB read hits -system.cpu1.dtb.read_misses 18763 # DTB read misses -system.cpu1.dtb.write_hits 6542250 # DTB write hits -system.cpu1.dtb.write_misses 2833 # DTB write misses +system.cpu1.dtb.read_hits 10163643 # DTB read hits +system.cpu1.dtb.read_misses 18794 # DTB read misses +system.cpu1.dtb.write_hits 6541990 # DTB write hits +system.cpu1.dtb.write_misses 2867 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 53 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 58 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 411 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10182457 # DTB read accesses -system.cpu1.dtb.write_accesses 6545083 # DTB write accesses +system.cpu1.dtb.perms_faults 409 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10182437 # DTB read accesses +system.cpu1.dtb.write_accesses 6544857 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16705944 # DTB hits -system.cpu1.dtb.misses 21596 # DTB misses -system.cpu1.dtb.accesses 16727540 # DTB accesses +system.cpu1.dtb.hits 16705633 # DTB hits +system.cpu1.dtb.misses 21661 # DTB misses +system.cpu1.dtb.accesses 16727294 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1499,8 +1509,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 43642438 # ITB inst hits -system.cpu1.itb.inst_misses 7000 # ITB inst misses +system.cpu1.itb.inst_hits 43641889 # ITB inst hits +system.cpu1.itb.inst_misses 7003 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1513,94 +1523,94 @@ system.cpu1.itb.flush_entries 1205 # Nu system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 538 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 544 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43649438 # ITB inst accesses -system.cpu1.itb.hits 43642438 # DTB hits -system.cpu1.itb.misses 7000 # DTB misses -system.cpu1.itb.accesses 43649438 # DTB accesses -system.cpu1.numCycles 104622324 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 43648892 # ITB inst accesses +system.cpu1.itb.hits 43641889 # DTB hits +system.cpu1.itb.misses 7003 # DTB misses +system.cpu1.itb.accesses 43648892 # DTB accesses +system.cpu1.numCycles 104622935 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9983715 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 109168018 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 33911271 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 27449665 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 91793931 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3775602 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 78298 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 31640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 200637 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 294928 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 7575 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 43641835 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 116209 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2258 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104278525 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.296897 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.339782 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9986788 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 109166158 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 33910806 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 27449504 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 91794015 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3775656 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 78908 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 31556 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 200392 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 294710 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 7499 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 43641278 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 116202 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2270 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104281696 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.296833 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.339781 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 47329971 45.39% 45.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 14035379 13.46% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7536372 7.23% 66.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 35376803 33.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 47334317 45.39% 45.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 14034977 13.46% 58.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7536210 7.23% 66.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 35376192 33.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104278525 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.324130 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.043449 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 13017622 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 61671390 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 26724772 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1111637 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1753104 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 754173 # Number of times decode resolved a branch +system.cpu1.fetch.rateDist::total 104281696 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.324124 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.043425 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 13018026 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 61674095 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 26725105 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1111367 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1753103 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 754241 # Number of times decode resolved a branch system.cpu1.decode.BranchMispred 137598 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 68061604 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1168958 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1753104 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17450100 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2254257 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 56981217 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 23380222 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2459625 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 55156752 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 230613 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 263389 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 35416 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18082 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1432431 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 55002738 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 260522478 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 58680214 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 52222609 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2780129 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1878054 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1805384 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13101359 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10457131 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6914141 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 629237 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 831086 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 54264809 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 589071 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 53908897 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 111732 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2292977 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 5809537 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 48790 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104278525 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.516970 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.852578 # Number of insts issued each cycle +system.cpu1.decode.DecodedInsts 68060945 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1169140 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1753103 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17450583 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2252903 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 56981552 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 23380155 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2463400 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 55156301 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 230486 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 263427 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 35391 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18241 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1436172 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 55002320 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 260520543 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 58679791 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1657 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 52223668 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2778652 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1878098 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1805410 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13101415 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10456972 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6914054 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 629493 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 831483 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 54264321 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 589116 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 53908666 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 111755 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2291961 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 5808692 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 48780 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104281696 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.516952 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.852554 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 71027306 68.11% 68.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16528003 15.85% 83.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 13076309 12.54% 96.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3359364 3.22% 99.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 287531 0.28% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 71029795 68.11% 68.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16529290 15.85% 83.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 13075763 12.54% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3359554 3.22% 99.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 287282 0.28% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -1608,9 +1618,9 @@ system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104278525 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104281696 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2925381 45.12% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2925282 45.12% 45.12% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 677 0.01% 45.13% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.13% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.13% # attempts to use FU when none available @@ -1639,131 +1649,131 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.13% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.13% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.13% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1673591 25.81% 70.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1884116 29.06% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1673331 25.81% 70.93% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1884639 29.07% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36727260 68.13% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46535 0.09% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36727327 68.13% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46544 0.09% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10380151 19.25% 87.48% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6751543 12.52% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 10380092 19.25% 87.48% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6751298 12.52% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 53908897 # Type of FU issued -system.cpu1.iq.rate 0.515271 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6483765 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.120273 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 218686026 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57154966 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 51920427 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 5790 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2052 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 60388895 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 3701 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 91393 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 53908666 # Type of FU issued +system.cpu1.iq.rate 0.515266 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6483929 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.120276 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 218688932 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57153517 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 51920276 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5780 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 60388837 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3692 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 91402 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 490676 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 687 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10193 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 356081 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 490292 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 689 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10197 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 355874 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 51970 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 70495 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 52006 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 70534 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1753104 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 548003 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 114295 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 54906042 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1753103 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 547921 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 114364 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 54905583 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10457131 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6914141 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 301584 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9824 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 96972 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10193 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 54960 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 127313 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 182273 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 53638837 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10278190 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 248481 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 10456972 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6914054 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 301613 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 9861 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 97001 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10197 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 54939 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 127326 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 182265 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 53638641 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10278143 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 248381 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 52162 # number of nop insts executed -system.cpu1.iew.exec_refs 16965416 # number of memory reference insts executed -system.cpu1.iew.exec_branches 11807917 # Number of branches executed -system.cpu1.iew.exec_stores 6687226 # Number of stores executed -system.cpu1.iew.exec_rate 0.512690 # Inst execution rate -system.cpu1.iew.wb_sent 53497875 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 51922213 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25229776 # num instructions producing a value -system.cpu1.iew.wb_consumers 38490454 # num instructions consuming a value +system.cpu1.iew.exec_nop 52146 # number of nop insts executed +system.cpu1.iew.exec_refs 16965109 # number of memory reference insts executed +system.cpu1.iew.exec_branches 11808008 # Number of branches executed +system.cpu1.iew.exec_stores 6686966 # Number of stores executed +system.cpu1.iew.exec_rate 0.512685 # Inst execution rate +system.cpu1.iew.wb_sent 53497702 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 51922060 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25229975 # num instructions producing a value +system.cpu1.iew.wb_consumers 38490431 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.496282 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.655481 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.496278 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.655487 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3658692 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 540281 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 170405 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 102346479 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.498098 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.159114 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3657476 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 540336 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 170387 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 102349842 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.498091 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.159102 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 76767559 75.01% 75.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 14288132 13.96% 88.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6080244 5.94% 94.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 703970 0.69% 95.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1980102 1.93% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1566998 1.53% 99.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 444730 0.43% 99.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 123732 0.12% 99.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 391012 0.38% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 76769313 75.01% 75.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 14290135 13.96% 88.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6080073 5.94% 94.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 704006 0.69% 95.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1980080 1.93% 97.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1566587 1.53% 99.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 444714 0.43% 99.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 123770 0.12% 99.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 391164 0.38% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 102346479 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 41392684 # Number of instructions committed -system.cpu1.commit.committedOps 50978528 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 102349842 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41393585 # Number of instructions committed +system.cpu1.commit.committedOps 50979540 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16524515 # Number of memory references committed -system.cpu1.commit.loads 9966455 # Number of loads committed -system.cpu1.commit.membars 209698 # Number of memory barriers committed -system.cpu1.commit.branches 11639872 # Number of branches committed +system.cpu1.commit.refs 16524860 # Number of memory references committed +system.cpu1.commit.loads 9966680 # Number of loads committed +system.cpu1.commit.membars 209721 # Number of memory barriers committed +system.cpu1.commit.branches 11640060 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 45828467 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3366626 # Number of function calls committed. +system.cpu1.commit.int_insts 45829312 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3366651 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 34405041 67.49% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 45633 0.09% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 34405704 67.49% 67.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 45637 0.09% 67.58% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction @@ -1791,217 +1801,217 @@ system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 9966455 19.55% 87.14% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6558060 12.86% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9966680 19.55% 87.14% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6558180 12.86% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 50978528 # Class of committed instruction -system.cpu1.commit.bw_lim_events 391012 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 50979540 # Class of committed instruction +system.cpu1.commit.bw_lim_events 391164 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 136555973 # The number of ROB reads -system.cpu1.rob.rob_writes 111202855 # The number of ROB writes -system.cpu1.timesIdled 53415 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 343799 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5543567058 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 41359830 # Number of Instructions Simulated -system.cpu1.committedOps 50945674 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.529564 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.529564 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.395325 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.395325 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 56285102 # number of integer regfile reads -system.cpu1.int_regfile_writes 35740910 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads -system.cpu1.fp_regfile_writes 520 # number of floating regfile writes -system.cpu1.cc_regfile_reads 191162273 # number of cc regfile reads -system.cpu1.cc_regfile_writes 15560809 # number of cc regfile writes -system.cpu1.misc_regfile_reads 205875708 # number of misc regfile reads -system.cpu1.misc_regfile_writes 388862 # number of misc regfile writes +system.cpu1.rob.rob_reads 136558924 # The number of ROB reads +system.cpu1.rob.rob_writes 111202252 # The number of ROB writes +system.cpu1.timesIdled 53311 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 341239 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5543976372 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41360731 # Number of Instructions Simulated +system.cpu1.committedOps 50946686 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.529523 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.529523 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.395331 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.395331 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 56284724 # number of integer regfile reads +system.cpu1.int_regfile_writes 35740870 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads +system.cpu1.fp_regfile_writes 516 # number of floating regfile writes +system.cpu1.cc_regfile_reads 191161936 # number of cc regfile reads +system.cpu1.cc_regfile_writes 15560884 # number of cc regfile writes +system.cpu1.misc_regfile_reads 205876605 # number of misc regfile reads +system.cpu1.misc_regfile_writes 388900 # number of misc regfile writes system.cpu1.dcache.tags.replacements 191071 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.558495 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 15741437 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 472.564441 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 15741519 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 82.245811 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 82.246239 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558495 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.564441 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922977 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922977 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 32983767 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 32983767 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9574609 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9574609 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5910607 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5910607 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49573 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49573 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79145 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79145 # number of LoadLockedReq hits +system.cpu1.dcache.tags.tag_accesses 32983738 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 32983738 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 9574548 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9574548 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5910552 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5910552 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49554 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49554 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79147 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79147 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71001 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 71001 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15485216 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15485216 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15534789 # number of overall hits -system.cpu1.dcache.overall_hits::total 15534789 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 219415 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 219415 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 398307 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 398307 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30093 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30093 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18121 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18121 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23394 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23394 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 617722 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 617722 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 647815 # number of overall misses -system.cpu1.dcache.overall_misses::total 647815 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3455998019 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3455998019 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8728631208 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8728631208 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363006249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 363006249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542688316 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 542688316 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 504500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 504500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12184629227 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12184629227 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12184629227 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12184629227 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9794024 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9794024 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308914 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6308914 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79666 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79666 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97266 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97266 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94395 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94395 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16102938 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16102938 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16182604 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16182604 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022403 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.022403 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063134 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.063134 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377740 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377740 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186304 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186304 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247831 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247831 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038361 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038361 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040032 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040032 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15750.965153 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15750.965153 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21914.330424 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21914.330424 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20032.351912 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20032.351912 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23197.756519 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23197.756519 # average StoreCondReq miss latency +system.cpu1.dcache.demand_hits::cpu1.data 15485100 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15485100 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15534654 # number of overall hits +system.cpu1.dcache.overall_hits::total 15534654 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 219354 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 219354 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 398461 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 398461 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30111 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30111 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18127 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18127 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23403 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23403 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 617815 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 617815 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 647926 # number of overall misses +system.cpu1.dcache.overall_misses::total 647926 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3453063988 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3453063988 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8746670918 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8746670918 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363087750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 363087750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542334299 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 542334299 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 511000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 511000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12199734906 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12199734906 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12199734906 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12199734906 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793902 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9793902 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6309013 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6309013 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79665 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79665 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97274 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97274 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94404 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94404 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16102915 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16102915 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16182580 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16182580 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022397 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.022397 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063157 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.063157 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377970 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377970 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186350 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186350 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247903 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247903 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038367 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038367 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040038 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.040038 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15741.969547 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15741.969547 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21951.134284 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21951.134284 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.217355 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.217355 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.708456 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.708456 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19725.101627 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19725.101627 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18808.809964 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18808.809964 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 357 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1112453 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 37 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 39616 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.648649 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 28.080902 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19746.582563 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19746.582563 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18828.901612 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18828.901612 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1116392 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39638 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.421053 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.164690 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 117473 # number of writebacks -system.cpu1.dcache.writebacks::total 117473 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79558 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 79558 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306502 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 306502 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 386060 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 386060 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 386060 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 386060 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139857 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 139857 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91805 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91805 # number of WriteReq MSHR misses +system.cpu1.dcache.writebacks::writebacks 117580 # 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number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 260290 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 260290 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1829354050 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1829354050 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2195265722 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2195265722 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 493416244 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 493416244 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87143250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87143250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494733684 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494733684 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 482500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 482500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4024619772 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4024619772 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4518036016 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4518036016 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298838492 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298838492 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826630495 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826630495 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125468987 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125468987 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014280 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014280 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014552 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014552 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359350 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359350 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050727 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050727 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247831 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247831 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4939 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4939 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23403 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23403 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 231660 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 231660 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 260288 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 260288 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1827288064 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1827288064 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2196971984 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2196971984 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494563997 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494563997 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87258999 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87258999 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494349701 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494349701 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 489000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 489000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4024260048 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4024260048 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4518824045 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4518824045 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298813494 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298813494 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826635494 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826635494 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125448988 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125448988 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014279 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014279 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014553 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014553 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359355 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359355 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050774 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050774 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247903 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247903 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014386 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.014386 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016085 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.016085 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13080.175107 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13080.175107 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23912.267545 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23912.267545 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17235.442364 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17235.442364 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17661.785570 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17661.785570 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21147.887664 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21147.887664 # average StoreCondReq mshr miss latency +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016084 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.016084 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13066.710983 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13066.710983 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23927.725628 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23927.725628 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17275.534337 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17275.534337 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17667.341365 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17667.341365 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21123.347477 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21123.347477 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17372.809403 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17372.809403 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17357.701087 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17357.701087 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17371.406579 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17371.406579 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17360.861987 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17360.861987 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2009,425 +2019,425 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # 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number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5095487535 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5095487535 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5095487535 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5095487535 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5095487535 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5095487535 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 43641679 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 43641679 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43641679 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43641679 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43641679 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 43641679 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014305 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014305 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014305 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014305 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014305 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014305 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8162.222115 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8162.222115 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8162.222115 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8162.222115 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8162.222115 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8162.222115 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 276500 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 87889967 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 87889967 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 43016771 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 43016771 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 43016771 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 43016771 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 43016771 # number of overall hits +system.cpu1.icache.overall_hits::total 43016771 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 624350 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 624350 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 624350 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 624350 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 624350 # number of overall misses +system.cpu1.icache.overall_misses::total 624350 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5095278041 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5095278041 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5095278041 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5095278041 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5095278041 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5095278041 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43641121 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43641121 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43641121 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43641121 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43641121 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43641121 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014306 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014306 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014306 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014306 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014306 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014306 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8160.932235 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8160.932235 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8160.932235 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8160.932235 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8160.932235 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8160.932235 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 275120 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 36143 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 36110 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.650167 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.618942 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16598 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 16598 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 16598 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 16598 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 16598 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 16598 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607679 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 607679 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 607679 # 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Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4157 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 969 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4190 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 941 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.582336 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # 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number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 601754 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 130149 # number of overall hits +system.cpu1.l2cache.overall_hits::total 755758 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 463 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 277 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5933 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 72130 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 78803 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28401 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28401 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22590 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22590 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # 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mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027491 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.033922 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007627 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.441047 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251740 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15359.971092 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16069.541397 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31767.605426 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14701.156825 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14701.156825 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.313236 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.313236 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 197249.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 197249.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29786.484471 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29786.484471 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19765.843492 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20053.664598 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19765.843492 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25915.436797 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251487 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26901.894714 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.593832 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.546147 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31757.007866 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14699.726879 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14699.726879 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13672.501574 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13672.501574 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 400999 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400999 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29828.575036 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29828.575036 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26901.894714 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19772.603245 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20042.049679 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26901.894714 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19772.603245 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25898.777029 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2437,63 +2447,63 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1294408 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 865128 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 1294463 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 865156 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 11871 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 11871 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 117472 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 157468 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84838 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41861 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 87109 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 117580 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 157134 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 84893 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41888 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 87131 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 79574 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66376 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215557 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825064 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17352 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37871 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2095844 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38892880 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25436874 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30676 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66932 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 64427362 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 834611 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1797339 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.418381 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.493294 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 79541 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66364 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215649 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825187 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17442 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37966 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2096244 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38895824 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25442442 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31012 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67368 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 64436646 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 834109 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1797203 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.418253 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.493272 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1045366 58.16% 58.16% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 751973 41.84% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1045518 58.17% 58.17% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 751685 41.83% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1797339 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 659657903 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1797203 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 659823435 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81258998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 81245999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 912908354 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 912982594 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 403842529 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 403842731 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9825216 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 9829718 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 21209360 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 21193613 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31016 # Transaction distribution system.iobus.trans_dist::ReadResp 31016 # Transaction distribution -system.iobus.trans_dist::WriteReq 59408 # Transaction distribution -system.iobus.trans_dist::WriteResp 59439 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 31 # Transaction distribution +system.iobus.trans_dist::WriteReq 59439 # Transaction distribution +system.iobus.trans_dist::WriteResp 23215 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56654 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2584,416 +2594,424 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326664315 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347117122 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84753000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36832361 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36830633 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36453 # number of replacements -system.iocache.tags.tagsinuse 14.560247 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.560350 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 254140674000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.560247 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 254140746000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.560350 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.910022 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.910022 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328487 # Number of tag accesses -system.iocache.tags.data_accesses 328487 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 328239 # Number of tag accesses +system.iocache.tags.data_accesses 328239 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses system.iocache.ReadReq_misses::total 247 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 31 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 31 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses system.iocache.demand_misses::total 247 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 247 # number of overall misses system.iocache.overall_misses::total 247 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30832377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30832377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 30832377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 30832377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 30832377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 30832377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 30846377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 30846377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9649955112 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9649955112 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 30846377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 30846377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 30846377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 30846377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36255 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36255 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000855 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000855 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124827.437247 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124827.437247 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124827.437247 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124827.437247 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124884.117409 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266396.729019 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 266396.729019 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124884.117409 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124884.117409 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 57106 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7195 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.936901 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17987377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17987377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2253111299 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2253111299 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17987377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17987377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17987377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17987377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18001377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18001377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7766041378 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7766041378 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18001377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18001377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18001377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18001377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72823.388664 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72823.388664 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72880.068826 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214389.393165 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214389.393165 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 153470 # number of replacements -system.l2c.tags.tagsinuse 64454.116988 # Cycle average of tags in use -system.l2c.tags.total_refs 519887 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 218097 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.383742 # Average number of references to valid blocks. +system.l2c.tags.replacements 153362 # number of replacements +system.l2c.tags.tagsinuse 64452.240621 # Cycle average of tags in use +system.l2c.tags.total_refs 520061 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 218026 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.385316 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 14115.348135 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.484821 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.876495 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1418.724430 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2146.622945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39266.214752 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.503287 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002749 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 292.346121 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 885.503464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6306.489787 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.215383 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 14085.588040 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.542715 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 2.877015 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1413.412167 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2156.075780 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39299.191861 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.498933 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000005 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 294.129683 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 883.808465 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6297.115959 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.214929 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000222 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.021648 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.032755 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599155 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.021567 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.032899 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599658 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004461 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013512 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096229 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983492 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 44297 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 20314 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.004488 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096086 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983463 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 44393 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 20252 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 7726 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 36160 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 7759 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 36223 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4599 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 15358 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.675919 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.309967 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6595063 # Number of tag accesses -system.l2c.tags.data_accesses 6595063 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 272 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 12554 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 38932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 181919 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 84 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 48 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 4143 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11543 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44205 # number of ReadReq hits -system.l2c.ReadReq_hits::total 293833 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 252624 # number of Writeback hits -system.l2c.Writeback_hits::total 252624 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 11705 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 720 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12425 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 181 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 174 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 355 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3713 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1233 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4946 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 272 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 12554 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 42645 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 181919 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 84 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 48 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 4143 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12776 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 44205 # number of demand (read+write) hits -system.l2c.demand_hits::total 298779 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 272 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits -system.l2c.overall_hits::cpu0.inst 12554 # number of overall hits -system.l2c.overall_hits::cpu0.data 42645 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 181919 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 84 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 48 # number of overall hits -system.l2c.overall_hits::cpu1.inst 4143 # number of overall hits -system.l2c.overall_hits::cpu1.data 12776 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 44205 # number of overall hits -system.l2c.overall_hits::total 298779 # number of overall hits +system.l2c.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4616 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 15266 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.677383 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.309021 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6595512 # Number of tag accesses +system.l2c.tags.data_accesses 6595512 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 297 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 126 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 12544 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 38879 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182049 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 77 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 46 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 4168 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11674 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44095 # number of ReadReq hits +system.l2c.ReadReq_hits::total 293955 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 252625 # number of Writeback hits +system.l2c.Writeback_hits::total 252625 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 11700 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 714 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 12414 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 188 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 168 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3696 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1226 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4922 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 297 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 126 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 12544 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 42575 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 182049 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 77 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 46 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 4168 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 12900 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 44095 # number of demand (read+write) hits +system.l2c.demand_hits::total 298877 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.278031 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474524 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.106383 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.103978 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.402432 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321941 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.417956 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3455077000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10019651249 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.102719 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229342 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181973 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474314 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.114943 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.102647 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.105852 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.322339 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.404316 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.431183 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.800224 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.485814 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.800213 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.878261 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.846618 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.677064 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854670 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.752427 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.102719 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229342 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.278055 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.114943 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.102647 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.399777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.322339 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.417796 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.102719 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229342 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.278055 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.114943 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.102647 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.399777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.322339 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.417796 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75820.619471 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75815.373563 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 102121.617279 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10123.926487 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10120.690852 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10123.137153 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10261.951936 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.006639 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10135.565507 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79341.104456 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65306.401276 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 72582.405248 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81831.099116 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76970.747485 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 63875 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 305500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 87332.285115 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75969.428365 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 102163.161014 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.617657 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10125.469580 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10150.534828 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10408.637450 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10067.822607 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10198.424936 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79738.846045 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65521.915811 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72886.511866 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77484.934482 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67006.597629 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 100059.867975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81831.099116 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78278.833577 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 305500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 87332.285115 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67202.369995 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 100121.391300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77484.934482 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67006.597629 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 100059.867975 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81831.099116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78278.833577 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 305500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 87332.285115 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67202.369995 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 100121.391300 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3204,57 +3222,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 237839 # Transaction distribution -system.membus.trans_dist::ReadResp 237839 # Transaction distribution -system.membus.trans_dist::WriteReq 30978 # Transaction distribution -system.membus.trans_dist::WriteResp 30978 # Transaction distribution -system.membus.trans_dist::Writeback 113437 # Transaction distribution +system.membus.trans_dist::ReadReq 237783 # Transaction distribution +system.membus.trans_dist::ReadResp 237783 # Transaction distribution +system.membus.trans_dist::WriteReq 30976 # Transaction distribution +system.membus.trans_dist::WriteResp 30976 # Transaction distribution +system.membus.trans_dist::Writeback 149598 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 79519 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40695 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13753 # Transaction distribution -system.membus.trans_dist::ReadExReq 31200 # Transaction distribution -system.membus.trans_dist::ReadExResp 14872 # Transaction distribution +system.membus.trans_dist::UpgradeReq 79558 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40675 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13780 # Transaction distribution +system.membus.trans_dist::ReadExReq 31194 # Transaction distribution +system.membus.trans_dist::ReadExResp 14873 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107968 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708866 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 830616 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 903326 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13732 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 830114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 939030 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162848 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21055004 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21245656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23564952 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123021 # Total snoops (count) -system.membus.snoop_fanout::samples 500917 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21024476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21215108 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25851588 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123388 # Total snoops (count) +system.membus.snoop_fanout::samples 537032 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 500917 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 537032 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 500917 # Request fanout histogram -system.membus.reqLayer0.occupancy 81243492 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 537032 # Request fanout histogram +system.membus.reqLayer0.occupancy 81237991 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11638997 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11614997 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1642210248 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1967612498 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2114152611 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2113693587 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38560639 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38580367 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3287,48 +3305,48 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 659694 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 659679 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30978 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30978 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 252624 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 91840 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41050 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 132890 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 40171 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 40171 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1298541 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426600 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1725141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40737982 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8560538 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 49298520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 291438 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1083643 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.033661 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.180356 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 659684 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 659669 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30976 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30976 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 252625 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 91886 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41031 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 132917 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 40129 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 40129 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1298615 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426559 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1725174 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40738026 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8562330 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 49300356 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 291348 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1083611 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.033657 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.180345 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1047166 96.63% 96.63% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36477 3.37% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1047140 96.63% 96.63% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36471 3.37% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1083643 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1586607093 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1083611 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1586551162 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2272505602 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2272414912 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 846502909 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 846278221 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1853 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b94dfc3eb..b41e9656d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,125 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.826844 # Number of seconds simulated -sim_ticks 2826844351500 # Number of ticks simulated -final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827042 # Number of seconds simulated +sim_ticks 2827042159500 # Number of ticks simulated +final_tick 2827042159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107954 # Simulator instruction rate (inst/s) -host_op_rate 130942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2695726613 # Simulator tick rate (ticks/s) -host_mem_usage 568304 # Number of bytes of host memory used -host_seconds 1048.64 # Real time elapsed on the host -sim_insts 113204796 # Number of instructions simulated -sim_ops 137311416 # Number of ops (including micro ops) simulated +host_inst_rate 100972 # Simulator instruction rate (inst/s) +host_op_rate 122474 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2522254422 # Simulator tick rate (ticks/s) +host_mem_usage 564960 # Number of bytes of host memory used +host_seconds 1120.84 # Real time elapsed on the host +sim_insts 113173742 # Number of instructions simulated +sim_ops 137273263 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9496932 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory +system.physmem.bytes_read::total 10823604 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8116352 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory +system.physmem.bytes_written::total 8133876 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 148909 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory +system.physmem.num_reads::total 171883 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126818 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory +system.physmem.num_writes::total 131199 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3359317 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3828597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2870970 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2877168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2870970 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 172165 # Number of read requests accepted -system.physmem.writeReqs 131231 # Number of write requests accepted -system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11009408 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue -system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10989 # Per bank write bursts -system.physmem.perBankRdBursts::1 10130 # Per bank write bursts -system.physmem.perBankRdBursts::2 11201 # Per bank write bursts -system.physmem.perBankRdBursts::3 11419 # Per bank write bursts -system.physmem.perBankRdBursts::4 13122 # Per bank write bursts -system.physmem.perBankRdBursts::5 10546 # Per bank write bursts -system.physmem.perBankRdBursts::6 11171 # Per bank write bursts -system.physmem.perBankRdBursts::7 11539 # Per bank write bursts -system.physmem.perBankRdBursts::8 10356 # Per bank write bursts -system.physmem.perBankRdBursts::9 11056 # Per bank write bursts -system.physmem.perBankRdBursts::10 10496 # Per bank write bursts -system.physmem.perBankRdBursts::11 9259 # Per bank write bursts -system.physmem.perBankRdBursts::12 10183 # Per bank write bursts -system.physmem.perBankRdBursts::13 10761 # Per bank write bursts -system.physmem.perBankRdBursts::14 10049 # Per bank write bursts -system.physmem.perBankRdBursts::15 9745 # Per bank write bursts -system.physmem.perBankWrBursts::0 8312 # Per bank write bursts -system.physmem.perBankWrBursts::1 7765 # Per bank write bursts -system.physmem.perBankWrBursts::2 8704 # Per bank write bursts -system.physmem.perBankWrBursts::3 8604 # Per bank write bursts -system.physmem.perBankWrBursts::4 7611 # Per bank write bursts -system.physmem.perBankWrBursts::5 7949 # Per bank write bursts -system.physmem.perBankWrBursts::6 8258 # Per bank write bursts -system.physmem.perBankWrBursts::7 8579 # Per bank write bursts -system.physmem.perBankWrBursts::8 7843 # Per bank write bursts -system.physmem.perBankWrBursts::9 8531 # Per bank write bursts -system.physmem.perBankWrBursts::10 7842 # Per bank write bursts -system.physmem.perBankWrBursts::11 6872 # Per bank write bursts -system.physmem.perBankWrBursts::12 7611 # Per bank write bursts -system.physmem.perBankWrBursts::13 8198 # Per bank write bursts -system.physmem.perBankWrBursts::14 7543 # Per bank write bursts -system.physmem.perBankWrBursts::15 7118 # Per bank write bursts +system.physmem.bw_total::cpu.inst 468351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3365516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6705765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 171884 # Number of read requests accepted +system.physmem.writeReqs 167423 # Number of write requests accepted +system.physmem.readBursts 171884 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 167423 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10992576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue +system.physmem.bytesWritten 10315392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10823668 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10452212 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6228 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4543 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10965 # Per bank write bursts +system.physmem.perBankRdBursts::1 10116 # Per bank write bursts +system.physmem.perBankRdBursts::2 11197 # Per bank write bursts +system.physmem.perBankRdBursts::3 11389 # Per bank write bursts +system.physmem.perBankRdBursts::4 13120 # Per bank write bursts +system.physmem.perBankRdBursts::5 10535 # Per bank write bursts +system.physmem.perBankRdBursts::6 11120 # Per bank write bursts +system.physmem.perBankRdBursts::7 11540 # Per bank write bursts +system.physmem.perBankRdBursts::8 10348 # Per bank write bursts +system.physmem.perBankRdBursts::9 11053 # Per bank write bursts +system.physmem.perBankRdBursts::10 10478 # Per bank write bursts +system.physmem.perBankRdBursts::11 9244 # Per bank write bursts +system.physmem.perBankRdBursts::12 10124 # Per bank write bursts +system.physmem.perBankRdBursts::13 10758 # Per bank write bursts +system.physmem.perBankRdBursts::14 10029 # Per bank write bursts +system.physmem.perBankRdBursts::15 9743 # Per bank write bursts +system.physmem.perBankWrBursts::0 10407 # Per bank write bursts +system.physmem.perBankWrBursts::1 9909 # Per bank write bursts +system.physmem.perBankWrBursts::2 10642 # Per bank write bursts +system.physmem.perBankWrBursts::3 10446 # Per bank write bursts +system.physmem.perBankWrBursts::4 9703 # Per bank write bursts +system.physmem.perBankWrBursts::5 10218 # Per bank write bursts +system.physmem.perBankWrBursts::6 10399 # Per bank write bursts +system.physmem.perBankWrBursts::7 10626 # Per bank write bursts +system.physmem.perBankWrBursts::8 10202 # Per bank write bursts +system.physmem.perBankWrBursts::9 10761 # Per bank write bursts +system.physmem.perBankWrBursts::10 9802 # Per bank write bursts +system.physmem.perBankWrBursts::11 9030 # Per bank write bursts +system.physmem.perBankWrBursts::12 9755 # Per bank write bursts +system.physmem.perBankWrBursts::13 10443 # Per bank write bursts +system.physmem.perBankWrBursts::14 9720 # Per bank write bursts +system.physmem.perBankWrBursts::15 9115 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 2826844140500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2827041948500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2993 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168617 # Read request sizes (log2) +system.physmem.readPktSize::6 168336 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126850 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 163042 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -162,156 +159,174 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.286868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.931959 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.707872 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23391 37.64% 37.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14782 23.79% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3679 5.92% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2602 4.19% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1126 1.81% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1130 1.82% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7555 12.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62147 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6420 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.793614 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.638433 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6418 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6420 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6420 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.834891 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.369444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.492928 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5612 87.41% 87.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 54 0.84% 88.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.20% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.23% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.26% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.06% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.05% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 167 2.60% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.16% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.08% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6420 # Writes before turning the bus around for reads -system.physmem.totQLat 2072280000 # Total ticks spent queuing -system.physmem.totMemAccLat 5297692500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 860110000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12046.60 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64399 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.873212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 190.977516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.816153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23539 36.55% 36.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14785 22.96% 59.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6319 9.81% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3687 5.73% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2636 4.09% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1562 2.43% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1140 1.77% 83.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1107 1.72% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9624 14.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64399 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6814 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.206340 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 540.339482 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6812 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6814 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6814 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.653948 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.805353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.459775 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5702 83.68% 83.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 39 0.57% 84.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.38% 84.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 231 3.39% 88.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 131 1.92% 89.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 61 0.90% 90.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 35 0.51% 91.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 27 0.40% 91.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 123 1.81% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 13 0.19% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 19 0.28% 94.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.16% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 31 0.45% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 13 0.19% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 13 0.19% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.38% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 61 0.90% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 10 0.15% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 9 0.13% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 11 0.16% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 89 1.31% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 7 0.10% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 18 0.26% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.06% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 5 0.07% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.06% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 26 0.38% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 4 0.06% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.06% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.07% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 11 0.16% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 11 0.16% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.04% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.04% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6814 # Writes before turning the bus around for reads +system.physmem.totQLat 2084525750 # Total ticks spent queuing +system.physmem.totMemAccLat 5305007000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 858795000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12136.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30796.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30886.34 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 3.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing -system.physmem.readRowHits 142002 # Number of row buffer hits during reads -system.physmem.writeRowHits 95212 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes -system.physmem.avgGap 9317341.50 # Average gap between requests -system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2694665773000 # Time in different power states -system.physmem.memoryStateTime::REF 94394300000 # Time in different power states +system.physmem.avgWrQLen 25.50 # Average write queue length when enqueuing +system.physmem.readRowHits 141721 # Number of row buffer hits during reads +system.physmem.writeRowHits 126816 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.67 # Row buffer hit rate for writes +system.physmem.avgGap 8331811.45 # Average gap between requests +system.physmem.pageHitRate 80.65 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2694668588500 # Time in different power states +system.physmem.memoryStateTime::REF 94401060000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37784264500 # Time in different power states +system.physmem.memoryStateTime::ACT 37972497000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 245987280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 223844040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134219250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122137125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 638851200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 80264555415 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79079779350 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625694839250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1626734116500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1892104031955 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1891832874855 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.336036 # Core power per rank (mW) -system.physmem.averagePower::1 669.240113 # Core power per rank (mW) +system.physmem.actEnergy::0 254499840 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 232356600 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 138864000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 126781875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 701859600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 637852800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 533628000 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 510805440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184648473360 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184648473360 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 80377758270 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 79142156730 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625717004000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1626800865000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1892372087070 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1892099291805 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.382923 # Core power per rank (mW) +system.physmem.averagePower::1 669.286428 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory @@ -330,15 +345,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46964274 # Number of BP lookups -system.cpu.branchPred.condPredicted 24050124 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232745 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29560624 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21375180 # Number of BTB hits +system.cpu.branchPred.lookups 46933448 # Number of BP lookups +system.cpu.branchPred.condPredicted 24039449 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232882 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29542848 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21360620 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.309637 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11765118 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.303862 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11754095 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33720 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -363,25 +378,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25471879 # DTB read hits -system.cpu.dtb.read_misses 60408 # DTB read misses -system.cpu.dtb.write_hits 19919747 # DTB write hits -system.cpu.dtb.write_misses 9388 # DTB write misses +system.cpu.dtb.read_hits 25465003 # DTB read hits +system.cpu.dtb.read_misses 60438 # DTB read misses +system.cpu.dtb.write_hits 19916425 # DTB write hits +system.cpu.dtb.write_misses 9382 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 344 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2309 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25532287 # DTB read accesses -system.cpu.dtb.write_accesses 19929135 # DTB write accesses +system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25525441 # DTB read accesses +system.cpu.dtb.write_accesses 19925807 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45391626 # DTB hits -system.cpu.dtb.misses 69796 # DTB misses -system.cpu.dtb.accesses 45461422 # DTB accesses +system.cpu.dtb.hits 45381428 # DTB hits +system.cpu.dtb.misses 69820 # DTB misses +system.cpu.dtb.accesses 45451248 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -403,8 +418,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 66240582 # ITB inst hits -system.cpu.itb.inst_misses 11936 # ITB inst misses +system.cpu.itb.inst_hits 66294026 # ITB inst hits +system.cpu.itb.inst_misses 11939 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -413,98 +428,98 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66252518 # ITB inst accesses -system.cpu.itb.hits 66240582 # DTB hits -system.cpu.itb.misses 11936 # DTB misses -system.cpu.itb.accesses 66252518 # DTB accesses -system.cpu.numCycles 260548868 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66305965 # ITB inst accesses +system.cpu.itb.hits 66294026 # DTB hits +system.cpu.itb.misses 11939 # DTB misses +system.cpu.itb.accesses 66305965 # DTB accesses +system.cpu.numCycles 260580731 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104909639 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184558460 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46964274 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33140298 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145575332 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6162234 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66240894 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254585351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104873538 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184739295 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46933448 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33114715 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145635789 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6158762 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 168952 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8750 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 338958 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 503648 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66294321 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1128854 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4994 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 254609122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.884999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.237560 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155338707 61.02% 61.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29243843 11.49% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14083345 5.53% 78.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55919456 21.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155317216 61.00% 61.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29235163 11.48% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14076452 5.53% 78.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55980291 21.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254585351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180251 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708345 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78108823 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105363724 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64680632 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3828797 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2603375 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485996 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157495015 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3691306 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2603375 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83949795 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10013130 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74489960 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62673363 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20855728 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146845952 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 950144 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 437842 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18093439 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150530803 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678954009 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164472740 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141875467 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8655333 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2847772 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2651529 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13851116 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26418132 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21304063 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1686589 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2099460 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143580575 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143376028 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 269119 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6250781 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14651223 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254585351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 254609122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180111 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.708952 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78085586 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105431733 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64660886 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3829260 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2601657 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422216 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 485978 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157447803 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3691485 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2601657 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83925210 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10033565 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74541150 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62655394 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20852146 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146807646 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 950357 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 437123 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62766 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16447 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18089237 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150492315 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678770164 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164434086 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141835122 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8657190 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2845976 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2649716 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13845319 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26411369 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21300781 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1686386 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2189128 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143541895 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2120957 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143337283 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269192 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6251828 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14653372 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125306 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 254609122 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.562970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.882443 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166207835 65.29% 65.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45306594 17.80% 83.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31956972 12.55% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10300343 4.05% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813574 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166344309 65.33% 65.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45117660 17.72% 83.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32035421 12.58% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10298180 4.04% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813519 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -512,9 +527,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254585351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254609122 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7371879 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7370311 32.63% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available @@ -543,13 +558,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632028 24.93% 57.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9586948 42.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5632420 24.93% 57.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9586874 42.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96038086 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113978 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96009315 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113982 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -573,100 +588,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26200986 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21012051 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26194290 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21008765 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143376028 # Type of FU issued -system.cpu.iq.rate 0.550285 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22590887 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157564 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564161758 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151957264 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140260479 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 143337283 # Type of FU issued +system.cpu.iq.rate 0.550069 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22589637 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157598 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564106761 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151919680 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140223084 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35756 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165941227 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 324401 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 165901147 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23436 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 324147 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1490308 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18271 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701002 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18251 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701176 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88081 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6304 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2603375 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 948323 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 290944 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145902361 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2601657 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 950737 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 291154 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145863821 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26418132 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21304063 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 256072 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18271 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317509 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471618 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789127 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142433599 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25799978 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872737 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26411369 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21300781 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096076 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17895 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 256263 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18251 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317548 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471732 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789280 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142394540 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25793108 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 873030 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200927 # number of nop insts executed -system.cpu.iew.exec_refs 46682549 # number of memory reference insts executed -system.cpu.iew.exec_branches 26544085 # Number of branches executed -system.cpu.iew.exec_stores 20882571 # Number of stores executed -system.cpu.iew.exec_rate 0.546668 # Inst execution rate -system.cpu.iew.wb_sent 142046516 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140271910 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63301578 # num instructions producing a value -system.cpu.iew.wb_consumers 95887209 # num instructions consuming a value +system.cpu.iew.exec_nop 200969 # number of nop insts executed +system.cpu.iew.exec_refs 46672402 # number of memory reference insts executed +system.cpu.iew.exec_branches 26533167 # Number of branches executed +system.cpu.iew.exec_stores 20879294 # Number of stores executed +system.cpu.iew.exec_rate 0.546451 # Inst execution rate +system.cpu.iew.wb_sent 142007306 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140234515 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63283849 # num instructions producing a value +system.cpu.iew.wb_consumers 95860591 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back +system.cpu.iew.wb_rate 0.538161 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7591975 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755003 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251649065 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.145555 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7591533 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995651 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755158 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251674404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.546055 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.146686 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178084267 70.77% 70.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43398054 17.25% 88.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15481884 6.15% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4357721 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1589357 0.63% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777637 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414343 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1083780 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178222235 70.81% 70.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43294364 17.20% 88.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15476639 6.15% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4357303 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6369018 2.53% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1679088 0.67% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777340 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414271 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1084146 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251649065 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113359701 # Number of instructions committed -system.cpu.commit.committedOps 137466321 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251674404 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113328647 # Number of instructions committed +system.cpu.commit.committedOps 137428168 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45531319 # Number of memory references committed -system.cpu.commit.loads 24928258 # Number of loads committed -system.cpu.commit.membars 814674 # Number of memory barriers committed -system.cpu.commit.branches 26060472 # Number of branches committed +system.cpu.commit.refs 45520666 # Number of memory references committed +system.cpu.commit.loads 24921061 # Number of loads committed +system.cpu.commit.membars 814701 # Number of memory barriers committed +system.cpu.commit.branches 26049415 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120282111 # Number of committed integer instructions. -system.cpu.commit.function_calls 4896381 # Number of function calls committed. +system.cpu.commit.int_insts 120247607 # Number of committed integer instructions. +system.cpu.commit.function_calls 4892692 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91813423 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91785919 66.79% 66.79% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction @@ -691,43 +706,43 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24928258 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20603061 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24921061 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20599605 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137466321 # Class of committed instruction -system.cpu.commit.bw_lim_events 1083780 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137428168 # Class of committed instruction +system.cpu.commit.bw_lim_events 1084146 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373370450 # The number of ROB reads -system.cpu.rob.rob_writes 293050441 # The number of ROB writes -system.cpu.timesIdled 892831 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5963517 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393139836 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113204796 # Number of Instructions Simulated -system.cpu.committedOps 137311416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.301571 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.301571 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155870535 # number of integer regfile reads -system.cpu.int_regfile_writes 88662743 # number of integer regfile writes -system.cpu.fp_regfile_reads 9591 # number of floating regfile reads +system.cpu.rob.rob_reads 373381031 # The number of ROB reads +system.cpu.rob.rob_writes 292971684 # The number of ROB writes +system.cpu.timesIdled 892930 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5971609 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393503589 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113173742 # Number of Instructions Simulated +system.cpu.committedOps 137273263 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.302484 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.302484 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434314 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434314 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155831391 # number of integer regfile reads +system.cpu.int_regfile_writes 88636024 # number of integer regfile writes +system.cpu.fp_regfile_reads 9607 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503158959 # number of cc regfile reads -system.cpu.cc_regfile_writes 53196475 # number of cc regfile writes -system.cpu.misc_regfile_reads 444136009 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes -system.cpu.dcache.tags.replacements 837744 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40170152 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838256 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.921103 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 503020695 # number of cc regfile reads +system.cpu.cc_regfile_writes 53185327 # number of cc regfile writes +system.cpu.misc_regfile_reads 444130548 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521619 # number of misc regfile writes +system.cpu.dcache.tags.replacements 837995 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958491 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40159583 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838507 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.894154 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958491 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -735,170 +750,170 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179419983 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179419983 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23329792 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23329792 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15588565 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15588565 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38918357 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38918357 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39265000 # number of overall hits -system.cpu.dcache.overall_hits::total 39265000 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700458 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700458 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3573865 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3573865 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179379502 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179379502 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23322864 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23322864 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15584894 # 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number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792718250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792718250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233175703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233175703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017247 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017247 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015623 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227848 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227848 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017756 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017756 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.137326 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.137326 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39710.100865 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39710.100865 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.978015 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.978015 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.154259 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.154259 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.968880 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.968880 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016526 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016526 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019059 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019059 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12933.664152 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12933.664152 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39719.244523 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39719.244523 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12372.502816 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12372.502816 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.944972 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.944972 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 35900 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 35900 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24168.291953 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13509.119197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13509.119197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13509.119197 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1592 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 105 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 104 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.371429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.307692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2969 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7003 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55048 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 28437271 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 28437271 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53838 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11660 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1874564 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 528034 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2468096 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060884 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62575.460107 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66847.886438 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64300.918596 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.417490 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.417490 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59954.587219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59954.587219 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62768.277090 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67694.386848 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64757.304395 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10080.188003 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10080.188003 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59987.377561 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59987.377561 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1285,59 +1300,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2564949 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2565344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2565278 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695574 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2770 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795093 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495164 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128717 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6450154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121297808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349473 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215428 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219909377 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65488 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3561849 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296684 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296684 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795456 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495832 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128794 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6451318 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121309456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98375777 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215684 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219947773 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65392 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3562462 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.010230 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100625 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3525400 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36449 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3526018 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36444 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3561849 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2502926529 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3562462 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2503396529 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849434655 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2849706150 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334430859 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1334755109 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19527240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74882707 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74897454 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30181 # Transaction distribution system.iobus.trans_dist::ReadResp 30181 # Transaction distribution system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1428,42 +1444,44 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347066130 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36776516 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.000725 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.999676 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 251942535000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000725 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062545 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062545 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327996 # Number of tag accesses system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses system.iocache.demand_misses::total 220 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 220 # number of overall misses system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26406377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26406377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26406377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26406377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26406377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26406377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 26411377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 26411377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9622478237 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9622478237 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 26411377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 26411377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 26411377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 26411377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1474,104 +1492,114 @@ system.iocache.overall_accesses::realview.ide 220 system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120028.986364 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120028.986364 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120028.986364 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120028.986364 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 120051.713636 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120051.713636 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265638.202214 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265638.202214 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120051.713636 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120051.713636 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56749 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7275 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.800550 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14965377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14965377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2230292235 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2230292235 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14965377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14965377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14965377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14965377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 14970377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14970377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7738798269 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7738798269 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 14970377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14970377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 14970377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14970377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68024.440909 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68024.440909 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68047.168182 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68047.168182 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213637.319705 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213637.319705 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 67834 # Transaction distribution -system.membus.trans_dist::ReadResp 67833 # Transaction distribution +system.membus.trans_dist::ReadReq 67832 # Transaction distribution +system.membus.trans_dist::ReadResp 67831 # Transaction distribution system.membus.trans_dist::WriteReq 27608 # Transaction distribution system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 90626 # Transaction distribution +system.membus.trans_dist::Writeback 126818 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution -system.membus.trans_dist::ReadExReq 135127 # Transaction distribution -system.membus.trans_dist::ReadExResp 135127 # Transaction distribution +system.membus.trans_dist::ReadExReq 135125 # Transaction distribution +system.membus.trans_dist::ReadExResp 135125 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452492 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 669001 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 205 # Total snoops (count) -system.membus.snoop_fanout::samples 300222 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16640360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16803825 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21439281 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 484 # Total snoops (count) +system.membus.snoop_fanout::samples 336405 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 336405 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 300222 # Request fanout histogram -system.membus.reqLayer0.occupancy 94200000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 336405 # Request fanout histogram +system.membus.reqLayer0.occupancy 94190000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1697000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1357984749 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1678025205 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1683660499 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 1677935457 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38220484 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1605,6 +1633,6 @@ system.realview.ethernet.coalescedTotal nan # av system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index de918fa9c..053f94faa 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,156 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.817967 # Number of seconds simulated -sim_ticks 2817967230500 # Number of ticks simulated -final_tick 2817967230500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.818075 # Number of seconds simulated +sim_ticks 2818074786500 # Number of ticks simulated +final_tick 2818074786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 295085 # Simulator instruction rate (inst/s) -host_op_rate 358305 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6587585543 # Simulator tick rate (ticks/s) -host_mem_usage 567284 # Number of bytes of host memory used -host_seconds 427.77 # Real time elapsed on the host -sim_insts 126228232 # Number of instructions simulated -sim_ops 153272049 # Number of ops (including micro ops) simulated +host_inst_rate 252135 # Simulator instruction rate (inst/s) +host_op_rate 306151 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5631568448 # Simulator tick rate (ticks/s) +host_mem_usage 564964 # Number of bytes of host memory used +host_seconds 500.41 # Real time elapsed on the host +sim_insts 126169808 # Number of instructions simulated +sim_ops 153199842 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 652964 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4386528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 666212 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4384416 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 130944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1051396 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 6080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 516736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 4232960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 128384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1037892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 6016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 504320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 4231744 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10978952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 652964 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 130944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 516736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1300644 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5946048 # Number of bytes written to this memory +system.physmem.bytes_read::total 10960328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 666212 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 128384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 504320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1298916 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8261760 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8281908 # Number of bytes written to this memory +system.physmem.bytes_written::total 8279284 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 18656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 69058 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 18863 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 69025 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2046 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 95 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 8074 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 66140 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2006 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16218 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 94 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 7880 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 66121 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180519 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 92907 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180228 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 129090 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133512 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133471 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 231715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1556628 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 236407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1555820 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 46468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 373104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 2158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 183372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1502132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 368298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 2135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 178959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1501644 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3896054 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 231715 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 46468 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 183372 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 461554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2110049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3889296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 236407 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 178959 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 460923 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2931704 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 822698 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2938965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2110049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2937922 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2931704 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 231715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1562844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 236407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1562035 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 46468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 373107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 2158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 183372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1502132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 823039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6835019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 92786 # Number of read requests accepted -system.physmem.writeReqs 67811 # Number of write requests accepted -system.physmem.readBursts 92786 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 67811 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5933952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4352 # Total number of bytes read from write queue -system.physmem.bytesWritten 4338688 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5938244 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4339784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 68 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2462 # Number of requests that are neither read nor write +system.physmem.bw_total::cpu1.inst 45557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 368301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 2135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 178959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1501644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6827218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 92321 # Number of read requests accepted +system.physmem.writeReqs 90302 # Number of write requests accepted +system.physmem.readBursts 92321 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 90302 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5904000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4544 # Total number of bytes read from write queue +system.physmem.bytesWritten 5704128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5908484 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5779208 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 71 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1152 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2483 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 6041 # Per bank write bursts -system.physmem.perBankRdBursts::1 5815 # Per bank write bursts -system.physmem.perBankRdBursts::2 5576 # Per bank write bursts -system.physmem.perBankRdBursts::3 6089 # Per bank write bursts -system.physmem.perBankRdBursts::4 5555 # Per bank write bursts -system.physmem.perBankRdBursts::5 5469 # Per bank write bursts -system.physmem.perBankRdBursts::6 6176 # Per bank write bursts -system.physmem.perBankRdBursts::7 6795 # Per bank write bursts -system.physmem.perBankRdBursts::8 6466 # Per bank write bursts -system.physmem.perBankRdBursts::9 6395 # Per bank write bursts -system.physmem.perBankRdBursts::10 5737 # Per bank write bursts -system.physmem.perBankRdBursts::11 5121 # Per bank write bursts -system.physmem.perBankRdBursts::12 5306 # Per bank write bursts -system.physmem.perBankRdBursts::13 5463 # Per bank write bursts -system.physmem.perBankRdBursts::14 5326 # Per bank write bursts -system.physmem.perBankRdBursts::15 5388 # Per bank write bursts -system.physmem.perBankWrBursts::0 4259 # Per bank write bursts -system.physmem.perBankWrBursts::1 3941 # Per bank write bursts -system.physmem.perBankWrBursts::2 4227 # Per bank write bursts -system.physmem.perBankWrBursts::3 4690 # Per bank write bursts -system.physmem.perBankWrBursts::4 4139 # Per bank write bursts -system.physmem.perBankWrBursts::5 4140 # Per bank write bursts -system.physmem.perBankWrBursts::6 4396 # Per bank write bursts -system.physmem.perBankWrBursts::7 4907 # Per bank write bursts -system.physmem.perBankWrBursts::8 4559 # Per bank write bursts -system.physmem.perBankWrBursts::9 4641 # Per bank write bursts -system.physmem.perBankWrBursts::10 4210 # Per bank write bursts -system.physmem.perBankWrBursts::11 3556 # Per bank write bursts -system.physmem.perBankWrBursts::12 4023 # Per bank write bursts -system.physmem.perBankWrBursts::13 4273 # Per bank write bursts -system.physmem.perBankWrBursts::14 3931 # Per bank write bursts -system.physmem.perBankWrBursts::15 3900 # Per bank write bursts +system.physmem.perBankRdBursts::1 5798 # Per bank write bursts +system.physmem.perBankRdBursts::2 5558 # Per bank write bursts +system.physmem.perBankRdBursts::3 6021 # Per bank write bursts +system.physmem.perBankRdBursts::4 5562 # Per bank write bursts +system.physmem.perBankRdBursts::5 5457 # Per bank write bursts +system.physmem.perBankRdBursts::6 6123 # Per bank write bursts +system.physmem.perBankRdBursts::7 6801 # Per bank write bursts +system.physmem.perBankRdBursts::8 6403 # Per bank write bursts +system.physmem.perBankRdBursts::9 6349 # Per bank write bursts +system.physmem.perBankRdBursts::10 5693 # Per bank write bursts +system.physmem.perBankRdBursts::11 5092 # Per bank write bursts +system.physmem.perBankRdBursts::12 5281 # Per bank write bursts +system.physmem.perBankRdBursts::13 5450 # Per bank write bursts +system.physmem.perBankRdBursts::14 5307 # Per bank write bursts +system.physmem.perBankRdBursts::15 5314 # Per bank write bursts +system.physmem.perBankWrBursts::0 5390 # Per bank write bursts +system.physmem.perBankWrBursts::1 4962 # Per bank write bursts +system.physmem.perBankWrBursts::2 5472 # Per bank write bursts +system.physmem.perBankWrBursts::3 5886 # Per bank write bursts +system.physmem.perBankWrBursts::4 5376 # Per bank write bursts +system.physmem.perBankWrBursts::5 5734 # Per bank write bursts +system.physmem.perBankWrBursts::6 5792 # Per bank write bursts +system.physmem.perBankWrBursts::7 6324 # Per bank write bursts +system.physmem.perBankWrBursts::8 6132 # Per bank write bursts +system.physmem.perBankWrBursts::9 6057 # Per bank write bursts +system.physmem.perBankWrBursts::10 5626 # Per bank write bursts +system.physmem.perBankWrBursts::11 4872 # Per bank write bursts +system.physmem.perBankWrBursts::12 5573 # Per bank write bursts +system.physmem.perBankWrBursts::13 5712 # Per bank write bursts +system.physmem.perBankWrBursts::14 5197 # Per bank write bursts +system.physmem.perBankWrBursts::15 5022 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 2816401088000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2816508644000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 1 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 92785 # Read request sizes (log2) +system.physmem.readPktSize::6 92320 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 67809 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 61124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 90300 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 60706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28069 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,163 +183,182 @@ system.physmem.wrQLenPdf::4 53 # Wh system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 48 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 49 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.458450 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.413676 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 339.664106 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12770 38.84% 38.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7721 23.49% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2991 9.10% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1712 5.21% 76.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1344 4.09% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 774 2.35% 83.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 537 1.63% 84.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 552 1.68% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4475 13.61% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32876 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3255 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.482642 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 540.024143 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3254 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 33954 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 341.872416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.139988 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.706061 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12607 37.13% 37.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7646 22.52% 59.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2942 8.66% 68.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1742 5.13% 73.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1359 4.00% 77.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 780 2.30% 79.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 533 1.57% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 565 1.66% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5780 17.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 33954 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3432 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.875583 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 525.946384 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3431 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3255 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3255 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.827035 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.877074 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.588559 # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 3432 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3432 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.969406 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.900383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 25.459060 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.06% 0.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 2714 83.38% 83.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 41 1.26% 84.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 32 0.98% 85.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 140 4.30% 90.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 131 4.02% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 8 0.25% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 4 0.12% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.28% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 18 0.55% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.09% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.22% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.12% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 99 3.04% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.12% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.09% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.09% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.09% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.06% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.06% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.28% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3255 # Writes before turning the bus around for reads -system.physmem.totQLat 1187084500 # Total ticks spent queuing -system.physmem.totMemAccLat 2925547000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 463590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12803.17 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::4-7 2 0.06% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 3 0.09% 0.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 2 0.06% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 2696 78.55% 78.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 29 0.84% 79.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 30 0.87% 80.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 138 4.02% 84.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 83 2.42% 87.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 30 0.87% 87.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 20 0.58% 88.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 23 0.67% 89.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 73 2.13% 91.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.20% 91.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.15% 91.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.23% 91.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 20 0.58% 92.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.23% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.23% 92.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 21 0.61% 93.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 41 1.19% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.23% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.09% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 9 0.26% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 65 1.89% 97.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.12% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 7 0.20% 97.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 5 0.15% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 7 0.20% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.09% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 8 0.23% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.09% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 22 0.64% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 7 0.20% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.06% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.06% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.09% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.03% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.09% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 5 0.15% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.03% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.09% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3432 # Writes before turning the bus around for reads +system.physmem.totQLat 1184332750 # Total ticks spent queuing +system.physmem.totMemAccLat 2914020250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 461250000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12838.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31553.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31588.30 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.10 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.01 # Average write queue length when enqueuing -system.physmem.readRowHits 76742 # Number of row buffer hits during reads -system.physmem.writeRowHits 50891 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.05 # Row buffer hit rate for writes -system.physmem.avgGap 17537071.60 # Average gap between requests -system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2704795503250 # Time in different power states -system.physmem.memoryStateTime::REF 94097900000 # Time in different power states +system.physmem.avgWrQLen 8.03 # Average write queue length when enqueuing +system.physmem.readRowHits 76434 # Number of row buffer hits during reads +system.physmem.writeRowHits 70988 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes +system.physmem.avgGap 15422529.71 # Average gap between requests +system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2704815148250 # Time in different power states +system.physmem.memoryStateTime::REF 94101540000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 19068171250 # Time in different power states +system.physmem.memoryStateTime::ACT 19154581250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 130016880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 118525680 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 70941750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 64671750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 370624800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 352544400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 224849520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 214442640 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184055492400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184055492400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 70844118390 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 70005569445 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1628632585500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1629368154750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1884328629240 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1884179401065 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.685154 # Core power per rank (mW) -system.physmem.averagePower::1 668.632198 # Core power per rank (mW) +system.physmem.actEnergy::0 134477280 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 122214960 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 73375500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 66684750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 369415800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 350110800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 291185280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 286357680 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184062612240 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184062612240 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 70840900170 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 70013903985 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1628700821250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1629426256500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1884472787520 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1884328140915 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.710440 # Core power per rank (mW) +system.physmem.averagePower::1 668.659112 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -385,25 +401,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14476193 # DTB read hits -system.cpu0.dtb.read_misses 4879 # DTB read misses -system.cpu0.dtb.write_hits 11073999 # DTB write hits -system.cpu0.dtb.write_misses 930 # DTB write misses -system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 14476474 # DTB read hits +system.cpu0.dtb.read_misses 4869 # DTB read misses +system.cpu0.dtb.write_hits 11056177 # DTB write hits +system.cpu0.dtb.write_misses 893 # DTB write misses +system.cpu0.dtb.flush_tlb 188 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3272 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3212 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 946 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 944 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 215 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14481072 # DTB read accesses -system.cpu0.dtb.write_accesses 11074929 # DTB write accesses +system.cpu0.dtb.perms_faults 196 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14481343 # DTB read accesses +system.cpu0.dtb.write_accesses 11057070 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 25550192 # DTB hits -system.cpu0.dtb.misses 5809 # DTB misses -system.cpu0.dtb.accesses 25556001 # DTB accesses +system.cpu0.dtb.hits 25532651 # DTB hits +system.cpu0.dtb.misses 5762 # DTB misses +system.cpu0.dtb.accesses 25538413 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -425,366 +441,366 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 67954476 # ITB inst hits -system.cpu0.itb.inst_misses 2811 # ITB inst misses +system.cpu0.itb.inst_hits 67995752 # ITB inst hits +system.cpu0.itb.inst_misses 2758 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 188 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2005 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1969 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 67957287 # ITB inst accesses -system.cpu0.itb.hits 67954476 # DTB hits -system.cpu0.itb.misses 2811 # DTB misses -system.cpu0.itb.accesses 67957287 # DTB accesses -system.cpu0.numCycles 82556827 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 67998510 # ITB inst accesses +system.cpu0.itb.hits 67995752 # DTB hits +system.cpu0.itb.misses 2758 # DTB misses +system.cpu0.itb.accesses 67998510 # DTB accesses +system.cpu0.numCycles 82558276 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 66160398 # Number of instructions committed -system.cpu0.committedOps 80652664 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 70891762 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5582 # Number of float alu accesses -system.cpu0.num_func_calls 7292056 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 8778747 # number of instructions that are conditional controls -system.cpu0.num_int_insts 70891762 # number of integer instructions -system.cpu0.num_fp_insts 5582 # number of float instructions -system.cpu0.num_int_register_reads 131506051 # number of times the integer registers were read -system.cpu0.num_int_register_writes 49334508 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4358 # number of times the floating registers were read +system.cpu0.committedInsts 66186941 # Number of instructions committed +system.cpu0.committedOps 80639436 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 70858992 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5470 # Number of float alu accesses +system.cpu0.num_func_calls 7266542 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 8791397 # number of instructions that are conditional controls +system.cpu0.num_int_insts 70858992 # number of integer instructions +system.cpu0.num_fp_insts 5470 # number of float instructions +system.cpu0.num_int_register_reads 131380013 # number of times the integer registers were read +system.cpu0.num_int_register_writes 49295072 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4246 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245869189 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 29383374 # number of times the CC registers were written -system.cpu0.num_mem_refs 26220572 # number of memory refs -system.cpu0.num_load_insts 14652138 # Number of load instructions -system.cpu0.num_store_insts 11568434 # Number of store instructions -system.cpu0.num_idle_cycles 77950738.874403 # Number of idle cycles -system.cpu0.num_busy_cycles 4606088.125597 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055793 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944207 # Percentage of idle cycles -system.cpu0.Branches 16465662 # Number of branches fetched +system.cpu0.num_cc_register_reads 245776790 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 29457750 # number of times the CC registers were written +system.cpu0.num_mem_refs 26204570 # number of memory refs +system.cpu0.num_load_insts 14653679 # Number of load instructions +system.cpu0.num_store_insts 11550891 # Number of store instructions +system.cpu0.num_idle_cycles 77949108.406676 # Number of idle cycles +system.cpu0.num_busy_cycles 4609167.593324 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055829 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944171 # Percentage of idle cycles +system.cpu0.Branches 16455876 # Number of branches fetched system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 55785323 67.97% 67.97% # Class of executed instruction -system.cpu0.op_class::IntMult 58705 0.07% 68.05% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4540 0.01% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::MemRead 14652138 17.85% 85.90% # Class of executed instruction -system.cpu0.op_class::MemWrite 11568434 14.10% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 55779692 67.98% 67.99% # Class of executed instruction +system.cpu0.op_class::IntMult 58849 0.07% 68.06% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4532 0.01% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::MemRead 14653679 17.86% 85.92% # Class of executed instruction +system.cpu0.op_class::MemWrite 11550891 14.08% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 82071333 # Class of executed instruction +system.cpu0.op_class::total 82049836 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3056 # 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Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.630840 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.512458 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948933 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032482 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018579 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.818118 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.670897 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.507786 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948864 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032560 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018570 # 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number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022754369 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7574271637 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9597026006 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2275974119 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8232846143 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10508820262 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1018414500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1694074000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2712488500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 777507500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1315307000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092814500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1795922000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3009381000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4805303000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013282 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018224 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008074 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010645 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017902 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007425 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244496 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224072 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121879 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016125 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019906 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.009047 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000093 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012183 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018085 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.007794 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014609 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020654 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.009023 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13223.789167 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13258.656568 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13249.267455 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36486.585530 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45407.799551 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43438.284097 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12823.200993 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14993.841632 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14320.625978 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15996.299038 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12417.676939 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13558.209719 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11923 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21692.899019 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26980.435565 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25662.075491 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20142.789923 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25358.753578 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24012.092536 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 692650 # number of writebacks +system.cpu0.dcache.writebacks::total 692650 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 119 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 155404 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 155523 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1411618 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1411618 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1952 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6678 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8630 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 119 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 1567022 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1567141 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 119 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 1567022 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1567141 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 58803 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 160127 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 218930 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 35394 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 120023 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 155417 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 20830 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 43721 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 64551 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1344 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3001 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4345 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 15 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94197 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 280150 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 374347 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 115027 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 323871 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 438898 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779470500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2130747955 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2910218455 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1251702570 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5436442471 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6688145041 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 266097500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 651596008 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 917693508 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 21534500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 37307002 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58841502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 176999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 176999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2031173070 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7567190426 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9598363496 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2297270570 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8218786434 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10516057004 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1018847500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1696409500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2715257000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 779636500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1318509000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2098145500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1798484000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3014918500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4813402500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013196 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018162 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008033 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011055 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017935 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007508 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.254527 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.223103 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123558 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016071 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.020745 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.009271 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000107 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000033 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012301 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018064 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.007806 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014862 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020622 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.009054 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13255.624713 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13306.612595 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13292.917622 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35364.823699 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45295.005716 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43033.548717 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12774.723956 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14903.501933 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14216.565320 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16022.693452 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12431.523492 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13542.347986 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11799.933333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11799.933333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21563.033536 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27011.209802 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25640.284271 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19971.576847 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25376.728494 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23960.138811 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -795,142 +811,142 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1798304 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.545340 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 100886115 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1798815 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 56.084764 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1798241 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.545331 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 100915026 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1798752 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 56.102801 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 10926866250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.674781 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.513239 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.357321 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.932959 # 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Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 104533981 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 104533981 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 67090111 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 21677596 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 12118408 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 100886115 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 67090111 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 21677596 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 12118408 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 100886115 # 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number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13444010166 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 67956517 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 21927829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 12850786 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 102735132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 67956517 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 21927829 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 12850786 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 102735132 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 67956517 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 21927829 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 12850786 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 102735132 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012749 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011412 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.056991 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.017998 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012749 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011412 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.056991 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.017998 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012749 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011412 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.056991 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.017998 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13547.845408 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13727.736450 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7270.895923 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13547.845408 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13727.736450 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7270.895923 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13547.845408 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13727.736450 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7270.895923 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5362 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 104562639 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 104562639 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 67129206 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 21624080 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 12161740 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 100915026 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 67129206 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 21624080 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 12161740 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 100915026 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 67129206 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 21624080 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 12161740 # number of overall hits +system.cpu0.icache.overall_hits::total 100915026 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 868572 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 248802 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 731453 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1848827 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 868572 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 248802 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 731453 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1848827 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 868572 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 248802 # 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number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 67997778 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 21872882 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 12893193 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 102763853 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 67997778 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 21872882 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 12893193 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 102763853 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 67997778 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 21872882 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 12893193 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 102763853 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012774 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011375 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.056732 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.017991 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012774 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011375 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.056732 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.017991 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012774 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011375 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.056732 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.017991 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13537.178158 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13722.492032 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7250.778447 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13537.178158 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13722.492032 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7250.778447 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13537.178158 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13722.492032 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7250.778447 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5131 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 334 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 344 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.053892 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.915698 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50167 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 50167 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 50167 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 50167 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 50167 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 50167 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 250233 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 682211 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 932444 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 250233 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 682211 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 932444 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 250233 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 682211 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 932444 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2888910000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8203668345 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11092578345 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2888910000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8203668345 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11092578345 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2888910000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8203668345 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11092578345 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011412 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053087 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009076 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011412 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053087 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009076 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011412 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053087 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009076 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11544.880172 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12025.118834 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11896.240788 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11544.880172 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12025.118834 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11896.240788 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11544.880172 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12025.118834 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11896.240788 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50040 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 50040 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 50040 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 50040 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 50040 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 50040 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 248802 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 681413 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 930215 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 248802 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 681413 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 930215 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 248802 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 681413 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 930215 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2869743000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8188546795 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11058289795 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2869743000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8188546795 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11058289795 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2869743000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8188546795 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11058289795 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009052 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009052 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009052 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11887.885913 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11887.885913 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11887.885913 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -955,25 +971,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4634797 # DTB read hits -system.cpu1.dtb.read_misses 1583 # DTB read misses -system.cpu1.dtb.write_hits 3276695 # DTB write hits -system.cpu1.dtb.write_misses 231 # DTB write misses +system.cpu1.dtb.read_hits 4627532 # DTB read hits +system.cpu1.dtb.read_misses 1596 # DTB read misses +system.cpu1.dtb.write_hits 3288935 # DTB write hits +system.cpu1.dtb.write_misses 256 # DTB write misses system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 105 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 148 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1209 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1270 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 225 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 52 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4636380 # DTB read accesses -system.cpu1.dtb.write_accesses 3276926 # DTB write accesses +system.cpu1.dtb.perms_faults 69 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4629128 # DTB read accesses +system.cpu1.dtb.write_accesses 3289191 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7911492 # DTB hits -system.cpu1.dtb.misses 1814 # DTB misses -system.cpu1.dtb.accesses 7913306 # DTB accesses +system.cpu1.dtb.hits 7916467 # DTB hits +system.cpu1.dtb.misses 1852 # DTB misses +system.cpu1.dtb.accesses 7918319 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -995,98 +1011,98 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 21927829 # ITB inst hits -system.cpu1.itb.inst_misses 850 # ITB inst misses +system.cpu1.itb.inst_hits 21872882 # ITB inst hits +system.cpu1.itb.inst_misses 825 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 105 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 148 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 702 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 668 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 21928679 # ITB inst accesses -system.cpu1.itb.hits 21927829 # DTB hits -system.cpu1.itb.misses 850 # DTB misses -system.cpu1.itb.accesses 21928679 # DTB accesses -system.cpu1.numCycles 158012697 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 21873707 # ITB inst accesses +system.cpu1.itb.hits 21872882 # DTB hits +system.cpu1.itb.misses 825 # DTB misses +system.cpu1.itb.accesses 21873707 # DTB accesses +system.cpu1.numCycles 158012156 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21219424 # Number of instructions committed -system.cpu1.committedOps 25417661 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22602393 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1642 # Number of float alu accesses -system.cpu1.num_func_calls 2405355 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2700524 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22602393 # number of integer instructions -system.cpu1.num_fp_insts 1642 # number of float instructions -system.cpu1.num_int_register_reads 41665364 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15857744 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1194 # number of times the floating registers were read +system.cpu1.committedInsts 21172070 # Number of instructions committed +system.cpu1.committedOps 25390672 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22586857 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1738 # Number of float alu accesses +system.cpu1.num_func_calls 2402647 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2689176 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22586857 # number of integer instructions +system.cpu1.num_fp_insts 1738 # number of float instructions +system.cpu1.num_int_register_reads 41666783 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15854927 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1290 # number of times the floating registers were read system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 92377254 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9370530 # number of times the CC registers were written -system.cpu1.num_mem_refs 8126107 # number of memory refs -system.cpu1.num_load_insts 4682037 # Number of load instructions -system.cpu1.num_store_insts 3444070 # Number of store instructions -system.cpu1.num_idle_cycles 151526887.882406 # Number of idle cycles -system.cpu1.num_busy_cycles 6485809.117594 # Number of busy cycles -system.cpu1.not_idle_fraction 0.041046 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.958954 # Percentage of idle cycles -system.cpu1.Branches 5257446 # Number of branches fetched -system.cpu1.op_class::No_OpClass 36 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 17987711 68.83% 68.83% # Class of executed instruction -system.cpu1.op_class::IntMult 19014 0.07% 68.90% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1154 0.00% 68.91% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.91% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.91% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.91% # Class of executed instruction -system.cpu1.op_class::MemRead 4682037 17.92% 86.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 3444070 13.18% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 92283936 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9328431 # number of times the CC registers were written +system.cpu1.num_mem_refs 8130215 # number of memory refs +system.cpu1.num_load_insts 4674464 # Number of load instructions +system.cpu1.num_store_insts 3455751 # Number of store instructions +system.cpu1.num_idle_cycles 151523865.450182 # Number of idle cycles +system.cpu1.num_busy_cycles 6488290.549818 # Number of busy cycles +system.cpu1.not_idle_fraction 0.041062 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.958938 # Percentage of idle cycles +system.cpu1.Branches 5242761 # Number of branches fetched +system.cpu1.op_class::No_OpClass 34 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 17956106 68.78% 68.78% # Class of executed instruction +system.cpu1.op_class::IntMult 18827 0.07% 68.85% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1169 0.00% 68.86% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.86% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.86% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.86% # Class of executed instruction +system.cpu1.op_class::MemRead 4674464 17.91% 86.76% # Class of executed instruction +system.cpu1.op_class::MemWrite 3455751 13.24% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 26134022 # Class of executed instruction +system.cpu1.op_class::total 26106351 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 17408373 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9463731 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 400017 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 10864152 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 8142904 # Number of BTB hits +system.cpu2.branchPred.lookups 17443399 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9460519 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 398611 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 10920300 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 8161771 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 74.952044 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4071247 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21277 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 74.739439 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4093630 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21092 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1110,25 +1126,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 9689518 # DTB read hits -system.cpu2.dtb.read_misses 37575 # DTB read misses -system.cpu2.dtb.write_hits 7159699 # DTB write hits -system.cpu2.dtb.write_misses 5670 # DTB write misses -system.cpu2.dtb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 370 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 9671030 # DTB read hits +system.cpu2.dtb.read_misses 37752 # DTB read misses +system.cpu2.dtb.write_hits 7157940 # DTB write hits +system.cpu2.dtb.write_misses 5738 # DTB write misses +system.cpu2.dtb.flush_tlb 182 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 368 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2438 # Number of entries that have been flushed from TLB +system.cpu2.dtb.flush_entries 2464 # Number of entries that have been flushed from TLB system.cpu2.dtb.align_faults 439 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 968 # Number of TLB faults due to prefetch +system.cpu2.dtb.prefetch_faults 949 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 417 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 9727093 # DTB read accesses -system.cpu2.dtb.write_accesses 7165369 # DTB write accesses +system.cpu2.dtb.perms_faults 419 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 9708782 # DTB read accesses +system.cpu2.dtb.write_accesses 7163678 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 16849217 # DTB hits -system.cpu2.dtb.misses 43245 # DTB misses -system.cpu2.dtb.accesses 16892462 # DTB accesses +system.cpu2.dtb.hits 16828970 # DTB hits +system.cpu2.dtb.misses 43490 # DTB misses +system.cpu2.dtb.accesses 16872460 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1150,335 +1166,334 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 12852348 # ITB inst hits -system.cpu2.itb.inst_misses 6327 # ITB inst misses +system.cpu2.itb.inst_hits 12894617 # ITB inst hits +system.cpu2.itb.inst_misses 6298 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 370 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 182 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 368 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1763 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1799 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1147 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1027 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 12858675 # ITB inst accesses -system.cpu2.itb.hits 12852348 # DTB hits -system.cpu2.itb.misses 6327 # DTB misses -system.cpu2.itb.accesses 12858675 # DTB accesses -system.cpu2.numCycles 69828422 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 12900915 # ITB inst accesses +system.cpu2.itb.hits 12894617 # DTB hits +system.cpu2.itb.misses 6298 # DTB misses +system.cpu2.itb.accesses 12900915 # DTB accesses +system.cpu2.numCycles 69897742 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 26736882 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 69116574 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 17408373 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 12214151 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 39634943 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2070237 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 91943 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 882 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 273 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 329325 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 101475 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 454 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 12850788 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 270289 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2773 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 67931271 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.222867 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.347613 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 26768356 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 69154350 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 17443399 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12255401 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 39728052 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2075674 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 91833 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 964 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 303 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 279943 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 102540 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 510 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 12893196 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 269600 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2749 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 68010313 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.222372 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.345734 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49354668 72.65% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 2396025 3.53% 76.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 1561758 2.30% 78.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4875455 7.18% 85.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1102436 1.62% 87.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 704861 1.04% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 3873045 5.70% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 751493 1.11% 95.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3311530 4.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49396667 72.63% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 2406815 3.54% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 1558633 2.29% 78.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4908408 7.22% 85.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1099721 1.62% 87.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 702073 1.03% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 3889062 5.72% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 750470 1.10% 95.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3298464 4.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 67931271 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.249302 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.989806 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 18645308 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 36894831 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 10382963 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1080745 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 927203 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 1311099 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 109436 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 59339671 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 354865 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 927203 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 19270411 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4356096 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 27085706 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 10825258 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5466363 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 56871138 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2407 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 944494 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 157128 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 3862497 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 58808456 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 261172418 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 63777133 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4183 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 48694532 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10113908 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 954202 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 890607 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 6274956 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 10279229 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 7930666 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 1385426 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1931872 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 54639620 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 672070 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 52007794 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 68359 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7304876 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 18433205 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 69298 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 67931271 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.765594 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.467899 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 68010313 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.249556 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.989365 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 18657683 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36955851 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 10391299 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1075131 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 930120 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 1306172 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 109269 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 59268734 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 353681 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 930120 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 19279637 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4349454 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 27177493 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 10831041 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5442328 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 56795330 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2300 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 936981 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 152434 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 3851730 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 58689966 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 260889069 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 63678439 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4318 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 48634410 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10055540 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 957404 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 893614 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 6253924 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 10259989 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 7928891 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 1377694 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1916931 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 54575287 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 669934 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 51950842 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 68646 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7267604 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18361034 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 68925 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 68010313 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.763867 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.465859 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 47467453 69.88% 69.88% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6844404 10.08% 79.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 5089744 7.49% 87.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4188713 6.17% 93.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1618102 2.38% 95.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1074322 1.58% 97.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1126267 1.66% 99.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 361985 0.53% 99.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 160281 0.24% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 47556715 69.93% 69.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6835010 10.05% 79.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 5099948 7.50% 87.47% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4195226 6.17% 93.64% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1610331 2.37% 96.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1069065 1.57% 97.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1123688 1.65% 99.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 361159 0.53% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 159171 0.23% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 67931271 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 68010313 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 78971 9.77% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 376071 46.54% 56.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 352950 43.68% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 78624 9.78% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 373360 46.42% 56.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 352326 43.80% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 108 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 34454774 66.25% 66.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 39220 0.08% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 2865 0.01% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 9972711 19.18% 85.51% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 7538110 14.49% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 110 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 34419657 66.25% 66.25% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 39271 0.08% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 2 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 2864 0.01% 66.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.34% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 9952470 19.16% 85.49% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 7536463 14.51% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 52007794 # Type of FU issued -system.cpu2.iq.rate 0.744794 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 807993 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.015536 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 172813810 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 62649489 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 50408450 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9401 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 4928 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 4143 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 52810613 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5066 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 267388 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 51950842 # Type of FU issued +system.cpu2.iq.rate 0.743241 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 804311 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.015482 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 172775366 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 62545429 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 50354259 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9588 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 5092 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4209 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 52749857 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5186 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 265342 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1612297 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1915 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 38614 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 794248 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1601303 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1888 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 38444 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 793651 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 131416 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 121570 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 130825 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 118759 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 927203 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3248790 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 940039 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 55419045 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 93730 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 10279229 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 7930666 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 359745 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 34744 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 896292 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 38614 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 184316 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 163000 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 347316 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 51571999 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 9796032 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 392652 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 930120 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3238109 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 943841 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 55348166 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 92957 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 10259989 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 7928891 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 358502 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 33985 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 900757 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 38444 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 183146 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 162363 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 345509 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 51516440 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 9776464 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 391010 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 107355 # number of nop insts executed -system.cpu2.iew.exec_refs 17260233 # number of memory reference insts executed -system.cpu2.iew.exec_branches 9488063 # Number of branches executed -system.cpu2.iew.exec_stores 7464201 # Number of stores executed -system.cpu2.iew.exec_rate 0.738553 # Inst execution rate -system.cpu2.iew.wb_sent 51114762 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 50412593 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 26484469 # num instructions producing a value -system.cpu2.iew.wb_consumers 46017701 # num instructions consuming a value +system.cpu2.iew.exec_nop 102945 # number of nop insts executed +system.cpu2.iew.exec_refs 17239257 # number of memory reference insts executed +system.cpu2.iew.exec_branches 9485344 # Number of branches executed +system.cpu2.iew.exec_stores 7462793 # Number of stores executed +system.cpu2.iew.exec_rate 0.737026 # Inst execution rate +system.cpu2.iew.wb_sent 51063802 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 50358468 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 26440569 # num instructions producing a value +system.cpu2.iew.wb_consumers 45930116 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.721949 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575528 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.720459 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575670 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8145270 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 602772 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 292077 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 66207003 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.713906 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.618708 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8108589 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 601009 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 290869 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 66287251 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.712520 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.616760 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 48127722 72.69% 72.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 8087932 12.22% 84.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 3990373 6.03% 90.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 1725495 2.61% 93.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 876020 1.32% 94.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 623327 0.94% 95.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 1254839 1.90% 97.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 299711 0.45% 98.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1221584 1.85% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 48204047 72.72% 72.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 8094433 12.21% 84.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 3998554 6.03% 90.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 1723968 2.60% 93.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 875669 1.32% 94.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 615346 0.93% 95.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 1257319 1.90% 97.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 299111 0.45% 98.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1218804 1.84% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 66207003 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 38912247 # Number of instructions committed -system.cpu2.commit.committedOps 47265561 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 66287251 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 38872037 # Number of instructions committed +system.cpu2.commit.committedOps 47230974 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 15803350 # Number of memory references committed -system.cpu2.commit.loads 8666932 # Number of loads committed -system.cpu2.commit.membars 226535 # Number of memory barriers committed -system.cpu2.commit.branches 8911403 # Number of branches committed -system.cpu2.commit.fp_insts 4112 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 41364475 # Number of committed integer instructions. -system.cpu2.commit.function_calls 1635441 # Number of function calls committed. +system.cpu2.commit.refs 15793926 # Number of memory references committed +system.cpu2.commit.loads 8658686 # Number of loads committed +system.cpu2.commit.membars 225734 # Number of memory barriers committed +system.cpu2.commit.branches 8913791 # Number of branches committed +system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 41344274 # Number of committed integer instructions. +system.cpu2.commit.function_calls 1642310 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 31421440 66.48% 66.48% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 37906 0.08% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 2865 0.01% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 31396236 66.47% 66.47% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 37948 0.08% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 2864 0.01% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 8666932 18.34% 84.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 7136418 15.10% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 8658686 18.33% 84.89% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 7135240 15.11% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 47265561 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1221584 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 47230974 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1218804 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 113032454 # The number of ROB reads -system.cpu2.rob.rob_writes 112549271 # The number of ROB writes -system.cpu2.timesIdled 280538 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1897151 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 5250079706 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 38848410 # Number of Instructions Simulated -system.cpu2.committedOps 47201724 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.797459 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.797459 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.556341 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.556341 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 56460891 # number of integer regfile reads -system.cpu2.int_regfile_writes 31949429 # number of integer regfile writes -system.cpu2.fp_regfile_reads 15783 # number of floating regfile reads +system.cpu2.rob.rob_reads 112988408 # The number of ROB reads +system.cpu2.rob.rob_writes 112405622 # The number of ROB writes +system.cpu2.timesIdled 280375 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1887429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 5250225403 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 38810797 # Number of Instructions Simulated +system.cpu2.committedOps 47169734 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.800987 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.800987 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.555251 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.555251 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 56393520 # number of integer regfile reads +system.cpu2.int_regfile_writes 31926452 # number of integer regfile writes +system.cpu2.fp_regfile_reads 15872 # number of floating regfile reads system.cpu2.fp_regfile_writes 13692 # number of floating regfile writes -system.cpu2.cc_regfile_reads 182431289 # number of cc regfile reads -system.cpu2.cc_regfile_writes 19284860 # number of cc regfile writes -system.cpu2.misc_regfile_reads 124219174 # number of misc regfile reads -system.cpu2.misc_regfile_writes 483131 # number of misc regfile writes +system.cpu2.cc_regfile_reads 182232541 # number of cc regfile reads +system.cpu2.cc_regfile_writes 19215539 # number of cc regfile writes +system.cpu2.misc_regfile_reads 124355307 # number of misc regfile reads +system.cpu2.misc_regfile_writes 481535 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30188 # Transaction distribution system.iobus.trans_dist::ReadResp 30188 # Transaction distribution -system.iobus.trans_dist::WriteReq 59010 # Transaction distribution -system.iobus.trans_dist::WriteResp 45563 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 9 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 13456 # Transaction distribution +system.iobus.trans_dist::WriteReq 59019 # Transaction distribution +system.iobus.trans_dist::WriteResp 22795 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1551,7 +1566,7 @@ system.iobus.reqLayer19.occupancy 2000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 2719000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 2807000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -1559,387 +1574,395 @@ system.iobus.reqLayer25.occupancy 15730000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 205242577 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 217719639 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 39802000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39873000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 23020273 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 22974011 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 0.992769 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.993341 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.992769 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062048 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062048 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.993341 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062084 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062084 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328356 # Number of tag accesses -system.iocache.tags.data_accesses 328356 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 328284 # Number of tag accesses +system.iocache.tags.data_accesses 328284 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 9 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 9 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 14192930 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 14192930 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 14192930 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14192930 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 14192930 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14192930 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 14419928 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 14419928 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6029712700 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6029712700 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 14419928 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14419928 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 14419928 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14419928 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36233 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36233 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000248 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000248 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 56321.150794 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 56321.150794 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 56321.150794 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 56321.150794 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 57221.936508 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 57221.936508 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166456.291409 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 166456.291409 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 57221.936508 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 57221.936508 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34890 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4513 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.730999 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::realview.ide 125 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 125 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 125 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 125 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 7692930 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 7692930 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 1401235920 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1401235920 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 7692930 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7692930 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 7692930 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7692930 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.496032 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.496032 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.496032 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61543.440000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 61543.440000 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 127 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 127 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22720 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 22720 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 127 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 127 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 127 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 127 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 7815928 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 7815928 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4848250722 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4848250722 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 7815928 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7815928 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 7815928 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7815928 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.503968 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.627208 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.627208 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.503968 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.503968 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61542.740157 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 61542.740157 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213391.316989 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213391.316989 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 100842 # number of replacements -system.l2c.tags.tagsinuse 65118.786988 # Cycle average of tags in use -system.l2c.tags.total_refs 2894514 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166082 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.428222 # Average number of references to valid blocks. +system.l2c.tags.replacements 100831 # number of replacements +system.l2c.tags.tagsinuse 65118.744874 # Cycle average of tags in use +system.l2c.tags.total_refs 2894730 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166072 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.430572 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49797.172619 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939323 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 49795.493403 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939326 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5291.834831 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2854.505423 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969196 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1121.422857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 949.240769 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.966175 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 3505.217048 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1537.518652 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.759845 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5292.397633 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2853.974292 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969197 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1121.420686 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 949.232304 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.100226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 3505.367496 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1539.850216 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.759819 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080747 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043556 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080756 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043548 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.017112 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.014484 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000900 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.053485 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.023461 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993634 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65193 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000887 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.053488 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.023496 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993633 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65196 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 45 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3121 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8094 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53637 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27443398 # Number of tag accesses -system.l2c.tags.data_accesses 27443398 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4964 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2546 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 856761 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 242820 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1454 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 747 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 248185 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 77821 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 27355 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 6441 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 674046 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 203120 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2346260 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 692581 # number of Writeback hits -system.l2c.Writeback_hits::total 692581 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits +system.l2c.tags.age_task_id_blocks_1024::2 3290 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7951 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53614 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000687 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994812 # 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average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61486.916547 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59929.130010 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58411.611557 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63655.170279 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62806.217981 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62037.180604 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59455.882353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58558.171601 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 64427.787644 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62786.059428 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62106.440817 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59929.130010 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58411.611557 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63655.170279 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62806.217981 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62037.180604 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59455.882353 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58558.171601 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 64427.787644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62786.059428 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62106.440817 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2094,55 +2117,55 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74258 # Transaction distribution -system.membus.trans_dist::ReadResp 74257 # Transaction distribution +system.membus.trans_dist::ReadReq 74228 # Transaction distribution +system.membus.trans_dist::ReadResp 74227 # Transaction distribution system.membus.trans_dist::WriteReq 27571 # Transaction distribution system.membus.trans_dist::WriteResp 27571 # Transaction distribution -system.membus.trans_dist::Writeback 92907 # Transaction distribution +system.membus.trans_dist::Writeback 129090 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4549 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4545 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4552 # Transaction distribution -system.membus.trans_dist::ReadExReq 137040 # Transaction distribution -system.membus.trans_dist::ReadExResp 137040 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4548 # Transaction distribution +system.membus.trans_dist::ReadExReq 137060 # Transaction distribution +system.membus.trans_dist::ReadExResp 137060 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 579244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 652071 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 579048 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109015 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109015 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 688063 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16941564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17104683 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19431147 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125 # Total snoops (count) -system.membus.snoop_fanout::samples 304876 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16930172 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17093291 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4642496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21735787 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 288 # Total snoops (count) +system.membus.snoop_fanout::samples 341037 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 304876 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 341037 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 304876 # Request fanout histogram -system.membus.reqLayer0.occupancy 40704500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 341037 # Request fanout histogram +system.membus.reqLayer0.occupancy 40803000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 459000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 460500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 735607750 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 937458500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 907107038 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 904148767 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 23918727 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 23873989 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2175,54 +2198,54 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2443155 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2443152 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2443122 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2443118 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 692581 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 22776 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2772 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296442 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296442 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3615657 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484160 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29265 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88229 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6217311 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115156920 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97909811 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49244 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155812 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213271787 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 51771 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3431211 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.010633 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.102567 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 692650 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 22720 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2771 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2788 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296527 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296527 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3615529 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484690 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28930 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88144 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6217293 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115152760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97928947 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48448 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213285547 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 51952 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3431323 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.010630 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.102554 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3394727 98.94% 98.94% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36484 1.06% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3394847 98.94% 98.94% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36476 1.06% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3431211 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2367804213 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3431323 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2376326693 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 553500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 558000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4198919632 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4188826435 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2015022352 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2020844355 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11862428 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11830425 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 39524153 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 39636892 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index b052ee538..3bffe858b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,142 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.804324 # Number of seconds simulated -sim_ticks 2804324203000 # Number of ticks simulated -final_tick 2804324203000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.814521 # Number of seconds simulated +sim_ticks 2814521286500 # Number of ticks simulated +final_tick 2814521286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110825 # Simulator instruction rate (inst/s) -host_op_rate 134512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2657187313 # Simulator tick rate (ticks/s) -host_mem_usage 623780 # Number of bytes of host memory used -host_seconds 1055.37 # Real time elapsed on the host -sim_insts 116961789 # Number of instructions simulated -sim_ops 141959973 # Number of ops (including micro ops) simulated +host_inst_rate 106354 # Simulator instruction rate (inst/s) +host_op_rate 129085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2558515098 # Simulator tick rate (ticks/s) +host_mem_usage 570360 # Number of bytes of host memory used +host_seconds 1100.06 # Real time elapsed on the host +sim_insts 116996192 # Number of instructions simulated +sim_ops 142001364 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 4288 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 739200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5181280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 637568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4639684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 746368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5095008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 629952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4708740 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11207460 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 739200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 637568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1376768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6111936 # Number of bytes written to this memory +system.physmem.bytes_read::total 11189732 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 746368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 629952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1376320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8426816 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8447796 # Number of bytes written to this memory +system.physmem.bytes_written::total 8444340 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 67 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 81476 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 69 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 72496 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 80128 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 68 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9843 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 73575 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175636 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 95499 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175359 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131669 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136104 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1529 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136050 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1524 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 263593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1847604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 227352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1654475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3996492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 263593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 227352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2179468 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 265185 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1810257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 223822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1673016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3975714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265185 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 223822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 489007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2994049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6223 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 826700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3012418 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2179468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3000276 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2994049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1524 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 263593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1853850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 227352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1654478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 827043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7008910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175637 # Number of read requests accepted -system.physmem.writeReqs 136104 # Number of write requests accepted -system.physmem.readBursts 175637 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 136104 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11232064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 8461376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11207524 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8447796 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3870 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4652 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11117 # Per bank write bursts -system.physmem.perBankRdBursts::1 11147 # Per bank write bursts -system.physmem.perBankRdBursts::2 11719 # Per bank write bursts -system.physmem.perBankRdBursts::3 11225 # Per bank write bursts -system.physmem.perBankRdBursts::4 11363 # Per bank write bursts -system.physmem.perBankRdBursts::5 11390 # Per bank write bursts -system.physmem.perBankRdBursts::6 11955 # Per bank write bursts -system.physmem.perBankRdBursts::7 11820 # Per bank write bursts -system.physmem.perBankRdBursts::8 10213 # Per bank write bursts -system.physmem.perBankRdBursts::9 10442 # Per bank write bursts -system.physmem.perBankRdBursts::10 10593 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 265185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1816481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 223822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1673019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6975990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175360 # Number of read requests accepted +system.physmem.writeReqs 172246 # Number of write requests accepted +system.physmem.readBursts 175360 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 172246 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11215872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue +system.physmem.bytesWritten 10651968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11189796 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10760884 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5779 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4663 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11102 # Per bank write bursts +system.physmem.perBankRdBursts::1 11119 # Per bank write bursts +system.physmem.perBankRdBursts::2 11680 # Per bank write bursts +system.physmem.perBankRdBursts::3 11222 # Per bank write bursts +system.physmem.perBankRdBursts::4 11370 # Per bank write bursts +system.physmem.perBankRdBursts::5 11380 # Per bank write bursts +system.physmem.perBankRdBursts::6 11917 # Per bank write bursts +system.physmem.perBankRdBursts::7 11794 # Per bank write bursts +system.physmem.perBankRdBursts::8 10207 # Per bank write bursts +system.physmem.perBankRdBursts::9 10426 # Per bank write bursts +system.physmem.perBankRdBursts::10 10580 # Per bank write bursts system.physmem.perBankRdBursts::11 9765 # Per bank write bursts -system.physmem.perBankRdBursts::12 10406 # Per bank write bursts -system.physmem.perBankRdBursts::13 11413 # Per bank write bursts -system.physmem.perBankRdBursts::14 10638 # Per bank write bursts -system.physmem.perBankRdBursts::15 10295 # Per bank write bursts -system.physmem.perBankWrBursts::0 8316 # Per bank write bursts -system.physmem.perBankWrBursts::1 8444 # Per bank write bursts -system.physmem.perBankWrBursts::2 9040 # Per bank write bursts -system.physmem.perBankWrBursts::3 8545 # Per bank write bursts -system.physmem.perBankWrBursts::4 8340 # Per bank write bursts -system.physmem.perBankWrBursts::5 8537 # Per bank write bursts -system.physmem.perBankWrBursts::6 8974 # Per bank write bursts -system.physmem.perBankWrBursts::7 8818 # Per bank write bursts -system.physmem.perBankWrBursts::8 7762 # Per bank write bursts -system.physmem.perBankWrBursts::9 7809 # Per bank write bursts -system.physmem.perBankWrBursts::10 7936 # Per bank write bursts -system.physmem.perBankWrBursts::11 7396 # Per bank write bursts -system.physmem.perBankWrBursts::12 7882 # Per bank write bursts -system.physmem.perBankWrBursts::13 8742 # Per bank write bursts -system.physmem.perBankWrBursts::14 8045 # Per bank write bursts -system.physmem.perBankWrBursts::15 7623 # Per bank write bursts +system.physmem.perBankRdBursts::12 10349 # Per bank write bursts +system.physmem.perBankRdBursts::13 11405 # Per bank write bursts +system.physmem.perBankRdBursts::14 10639 # Per bank write bursts +system.physmem.perBankRdBursts::15 10293 # Per bank write bursts +system.physmem.perBankWrBursts::0 10392 # Per bank write bursts +system.physmem.perBankWrBursts::1 10480 # Per bank write bursts +system.physmem.perBankWrBursts::2 10999 # Per bank write bursts +system.physmem.perBankWrBursts::3 10520 # Per bank write bursts +system.physmem.perBankWrBursts::4 10645 # Per bank write bursts +system.physmem.perBankWrBursts::5 10713 # Per bank write bursts +system.physmem.perBankWrBursts::6 11169 # Per bank write bursts +system.physmem.perBankWrBursts::7 10762 # Per bank write bursts +system.physmem.perBankWrBursts::8 9958 # Per bank write bursts +system.physmem.perBankWrBursts::9 10000 # Per bank write bursts +system.physmem.perBankWrBursts::10 9968 # Per bank write bursts +system.physmem.perBankWrBursts::11 9745 # Per bank write bursts +system.physmem.perBankWrBursts::12 10100 # Per bank write bursts +system.physmem.perBankWrBursts::13 10962 # Per bank write bursts +system.physmem.perBankWrBursts::14 10229 # Per bank write bursts +system.physmem.perBankWrBursts::15 9795 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2804324017000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2814521100500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175082 # Read request sizes (log2) +system.physmem.readPktSize::6 174805 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131723 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 104376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 167865 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 104183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -165,195 +162,218 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 90 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 120 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.989874 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.723316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.460023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24407 37.68% 37.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15776 24.35% 62.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6538 10.09% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3738 5.77% 77.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2814 4.34% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1507 2.33% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1107 1.71% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1104 1.70% 87.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7792 12.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64783 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6707 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.165350 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 477.307058 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6704 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 325.854595 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.388710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 345.406571 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24509 36.52% 36.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15902 23.70% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6498 9.68% 69.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3742 5.58% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2828 4.21% 79.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1529 2.28% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1119 1.67% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1119 1.67% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9863 14.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67109 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7131 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.571869 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 462.936248 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7128 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6707 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.712092 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.230918 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.181787 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 16 0.24% 0.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.10% 0.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 4 0.06% 0.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 9 0.13% 0.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5755 85.81% 86.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 109 1.63% 87.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 46 0.69% 88.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 238 3.55% 92.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 224 3.34% 95.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 22 0.33% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 23 0.34% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.10% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 31 0.46% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.03% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.12% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 152 2.27% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.18% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 13 0.19% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.06% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6707 # Writes before turning the bus around for reads -system.physmem.totQLat 2727699250 # Total ticks spent queuing -system.physmem.totMemAccLat 6018343000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 877505000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15542.36 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7131 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7131 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.339924 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.576956 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.763951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 15 0.21% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.10% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 3 0.04% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 7 0.10% 0.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5889 82.58% 83.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 114 1.60% 84.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 53 0.74% 85.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 224 3.14% 88.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 142 1.99% 90.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 54 0.76% 91.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 26 0.36% 91.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 40 0.56% 92.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 124 1.74% 93.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.15% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 11 0.15% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.15% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 24 0.34% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 13 0.18% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 13 0.18% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 32 0.45% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 59 0.83% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 9 0.13% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.08% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 9 0.13% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 92 1.29% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.07% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 8 0.11% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.06% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 17 0.24% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 14 0.20% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.04% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 38 0.53% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 9 0.13% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.13% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 7 0.10% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7131 # Writes before turning the bus around for reads +system.physmem.totQLat 2737638250 # Total ticks spent queuing +system.physmem.totMemAccLat 6023538250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 876240000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15621.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34292.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34371.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.98 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.66 # Average write queue length when enqueuing -system.physmem.readRowHits 145124 # Number of row buffer hits during reads -system.physmem.writeRowHits 97802 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.96 # Row buffer hit rate for writes -system.physmem.avgGap 8995685.58 # Average gap between requests -system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2678459999250 # Time in different power states -system.physmem.memoryStateTime::REF 93642380000 # Time in different power states +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.89 # Average write queue length when enqueuing +system.physmem.readRowHits 144870 # Number of row buffer hits during reads +system.physmem.writeRowHits 129705 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.92 # Row buffer hit rate for writes +system.physmem.avgGap 8096871.46 # Average gap between requests +system.physmem.pageHitRate 80.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2688100208500 # Time in different power states +system.physmem.memoryStateTime::REF 93982980000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 32221812750 # Time in different power states +system.physmem.memoryStateTime::ACT 32438087000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 259096320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 230663160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 141372000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 125857875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 715533000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 653367000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 447210720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 409503600 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 183164495280 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 183164495280 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 77871628440 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 76866307470 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1614283197000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1615165057500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1876882532760 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1876615251885 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.282725 # Core power per rank (mW) -system.physmem.averagePower::1 669.187414 # Core power per rank (mW) +system.physmem.actEnergy::0 267820560 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 239523480 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 146132250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 130692375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 714347400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 652579200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 555206400 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 523305360 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 183830708880 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 183830708880 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 78196283910 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 77193580095 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1620118404000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1620997968750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1883828903400 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1883568358140 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.325253 # Core power per rank (mW) +system.physmem.averagePower::1 669.232681 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 640 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 640 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 640 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 10 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 10 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 228 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 228 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 228 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 228 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 228 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 228 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 227 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 227 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 227 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 227 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 227 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 227 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 27347795 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14227638 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 549324 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 17049849 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12874628 # Number of BTB hits +system.cpu0.branchPred.lookups 27454524 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14302225 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 560028 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 17144432 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12924274 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 75.511683 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6769747 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 30174 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 75.384673 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6779174 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 30579 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -378,25 +398,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14276180 # DTB read hits -system.cpu0.dtb.read_misses 49315 # DTB read misses -system.cpu0.dtb.write_hits 10339289 # DTB write hits -system.cpu0.dtb.write_misses 7532 # DTB write misses -system.cpu0.dtb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 14369333 # DTB read hits +system.cpu0.dtb.read_misses 50679 # DTB read misses +system.cpu0.dtb.write_hits 10383293 # DTB write hits +system.cpu0.dtb.write_misses 7631 # DTB write misses +system.cpu0.dtb.flush_tlb 181 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3434 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1022 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1284 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3537 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1074 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1312 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14325495 # DTB read accesses -system.cpu0.dtb.write_accesses 10346821 # DTB write accesses +system.cpu0.dtb.perms_faults 596 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14420012 # DTB read accesses +system.cpu0.dtb.write_accesses 10390924 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24615469 # DTB hits -system.cpu0.dtb.misses 56847 # DTB misses -system.cpu0.dtb.accesses 24672316 # DTB accesses +system.cpu0.dtb.hits 24752626 # DTB hits +system.cpu0.dtb.misses 58310 # DTB misses +system.cpu0.dtb.accesses 24810936 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -418,158 +438,158 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 20541420 # ITB inst hits -system.cpu0.itb.inst_misses 9178 # ITB inst misses +system.cpu0.itb.inst_hits 20633477 # ITB inst hits +system.cpu0.itb.inst_misses 8891 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 181 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2315 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2375 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1446 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1486 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20550598 # ITB inst accesses -system.cpu0.itb.hits 20541420 # DTB hits -system.cpu0.itb.misses 9178 # DTB misses -system.cpu0.itb.accesses 20550598 # DTB accesses -system.cpu0.numCycles 107861472 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20642368 # ITB inst accesses +system.cpu0.itb.hits 20633477 # DTB hits +system.cpu0.itb.misses 8891 # DTB misses +system.cpu0.itb.accesses 20642368 # DTB accesses +system.cpu0.numCycles 108176623 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 40570754 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 105629295 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 27347795 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19644375 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 61853082 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3245677 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 138610 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 7043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 456 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 740654 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 142990 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 184 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20540168 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 376427 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3608 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 105076575 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.207830 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.305137 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 40839610 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 106163283 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 27454524 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19703448 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 62043143 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3268003 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 133218 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 6760 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 444 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 566983 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 143911 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 303 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20632158 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 383201 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3475 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 105368337 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.210422 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.308267 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 75967097 72.30% 72.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3896975 3.71% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2393426 2.28% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 8192788 7.80% 86.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1656267 1.58% 87.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1057275 1.01% 88.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6246218 5.94% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1068490 1.02% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4598039 4.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 76140836 72.26% 72.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3909718 3.71% 75.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2409828 2.29% 78.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 8201309 7.78% 86.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1666024 1.58% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1066995 1.01% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6252269 5.93% 94.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1076692 1.02% 95.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4644666 4.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 105076575 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.253546 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.979305 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27994294 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58319975 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15794569 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1493949 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1473513 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1905038 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 151409 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 87407414 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 488746 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1473513 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28854924 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7818064 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 44554229 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16415102 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 5960455 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 83576128 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2157 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1234281 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 240945 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3763501 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 86207701 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 384903383 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 93172990 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5580 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 72433922 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13773763 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1548068 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1453832 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8905153 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 15025647 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11465948 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1963626 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2709003 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 80419048 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1054429 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 77104069 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 91403 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10038631 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24749704 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 115176 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 105076575 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.733789 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.427784 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 105368337 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.253794 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.981388 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 28207041 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58279935 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15901267 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1497528 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1482288 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1929977 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 153844 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 87989191 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 497994 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1482288 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 29073693 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7845343 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 44593101 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16518954 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 5854664 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 84134111 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 3122 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1216605 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 229511 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3673419 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 86811691 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 387318144 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 93734921 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 6132 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 72788537 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14023138 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1551068 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1456111 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8913232 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 15130036 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11520954 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1958410 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2751427 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 80936298 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1061855 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 77564111 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 93737 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10215309 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 25112322 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 116543 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 105368337 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.736124 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.430465 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 74341292 70.75% 70.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10185363 9.69% 80.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7872852 7.49% 87.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6575632 6.26% 94.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2323435 2.21% 96.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1484934 1.41% 97.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1562160 1.49% 99.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 492520 0.47% 99.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 238387 0.23% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74478008 70.68% 70.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10230371 9.71% 80.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7904463 7.50% 87.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6602787 6.27% 94.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2340926 2.22% 96.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1499410 1.42% 97.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1574332 1.49% 99.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 494613 0.47% 99.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 243427 0.23% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 105076575 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 105368337 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 112989 9.93% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 4 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 531745 46.73% 56.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 493078 43.34% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 114999 10.01% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 537121 46.77% 56.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 496300 43.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2199 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 51434902 66.71% 66.71% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57707 0.07% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2212 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 51748002 66.72% 66.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57664 0.07% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.79% # Type of FU issued @@ -579,7 +599,7 @@ system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.79% # Ty system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 2 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 66.79% # Type of FU issued @@ -593,410 +613,410 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.79% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4464 0.01% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14679264 19.04% 85.83% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10925524 14.17% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4488 0.01% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14779498 19.05% 85.85% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10972237 14.15% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 77104069 # Type of FU issued -system.cpu0.iq.rate 0.714843 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1137816 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014757 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 260501553 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 91556805 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 74656153 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12379 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6497 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5408 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 78233021 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6665 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 345101 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 77564111 # Type of FU issued +system.cpu0.iq.rate 0.717014 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1148423 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014806 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 261725178 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 92258450 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 75089604 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 13541 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 7156 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5898 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 78703023 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7299 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 349741 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2206473 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2440 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 52158 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1126677 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2246191 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2538 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 53151 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1141086 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 207379 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 207346 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 210404 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 206292 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1473513 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5378839 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2159961 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 81600157 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 131532 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 15025647 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11465948 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 550941 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44144 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2103435 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 52158 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 253796 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 219690 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 473486 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 76500063 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14443562 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 547275 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1482288 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5387849 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 2181647 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 82121235 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 133747 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 15130036 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11520954 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 554131 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 44613 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2124772 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 53151 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 259624 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 223920 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 483544 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 76945762 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14537604 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 560147 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 126680 # number of nop insts executed -system.cpu0.iew.exec_refs 25263883 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14430618 # Number of branches executed -system.cpu0.iew.exec_stores 10820321 # Number of stores executed -system.cpu0.iew.exec_rate 0.709244 # Inst execution rate -system.cpu0.iew.wb_sent 75840899 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 74661561 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 38996929 # num instructions producing a value -system.cpu0.iew.wb_consumers 67640251 # num instructions consuming a value +system.cpu0.iew.exec_nop 123082 # number of nop insts executed +system.cpu0.iew.exec_refs 25403316 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14507602 # Number of branches executed +system.cpu0.iew.exec_stores 10865712 # Number of stores executed +system.cpu0.iew.exec_rate 0.711298 # Inst execution rate +system.cpu0.iew.wb_sent 76276982 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 75095502 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 39231378 # num instructions producing a value +system.cpu0.iew.wb_consumers 67987446 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.692199 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.576534 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.694193 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.577039 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11313930 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 939253 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 399962 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 102521377 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.684763 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.574745 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11493235 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 945312 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 408278 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 102784889 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.686324 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.576953 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 75202228 73.35% 73.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12236708 11.94% 85.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6265954 6.11% 91.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2644751 2.58% 93.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1294412 1.26% 95.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 834681 0.81% 96.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1890114 1.84% 97.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 411979 0.40% 98.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1740550 1.70% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 75343720 73.30% 73.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12296354 11.96% 85.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6287520 6.12% 91.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2655547 2.58% 93.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1297923 1.26% 95.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 837088 0.81% 96.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1893538 1.84% 97.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 418210 0.41% 98.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1754989 1.71% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 102521377 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 57875239 # Number of instructions committed -system.cpu0.commit.committedOps 70202859 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 102784889 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 58163617 # Number of instructions committed +system.cpu0.commit.committedOps 70543777 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 23158445 # Number of memory references committed -system.cpu0.commit.loads 12819174 # Number of loads committed -system.cpu0.commit.membars 372518 # Number of memory barriers committed -system.cpu0.commit.branches 13646130 # Number of branches committed -system.cpu0.commit.fp_insts 5383 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 61467682 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2657552 # Number of function calls committed. +system.cpu0.commit.refs 23263713 # Number of memory references committed +system.cpu0.commit.loads 12883845 # Number of loads committed +system.cpu0.commit.membars 375648 # Number of memory barriers committed +system.cpu0.commit.branches 13703294 # Number of branches committed +system.cpu0.commit.fp_insts 5822 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 61764808 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2662565 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 46983958 66.93% 66.93% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55992 0.08% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4464 0.01% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12819174 18.26% 85.27% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10339271 14.73% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 47219648 66.94% 66.94% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55928 0.08% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4488 0.01% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12883845 18.26% 85.29% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10379868 14.71% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 70202859 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1740550 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 70543777 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1754989 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 169629703 # The number of ROB reads -system.cpu0.rob.rob_writes 165592947 # The number of ROB writes -system.cpu0.timesIdled 399199 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2784897 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2442098527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 57803575 # Number of Instructions Simulated -system.cpu0.committedOps 70131195 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.866000 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.866000 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.535906 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.535906 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 83223669 # number of integer regfile reads -system.cpu0.int_regfile_writes 47570918 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16180 # number of floating regfile reads -system.cpu0.fp_regfile_writes 12936 # number of floating regfile writes -system.cpu0.cc_regfile_reads 270428616 # number of cc regfile reads -system.cpu0.cc_regfile_writes 28197078 # number of cc regfile writes -system.cpu0.misc_regfile_reads 191501099 # number of misc regfile reads -system.cpu0.misc_regfile_writes 720417 # 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Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.862130 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.862130 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.537020 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.537020 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 83669019 # number of integer regfile reads +system.cpu0.int_regfile_writes 47858513 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16561 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13070 # number of floating regfile writes +system.cpu0.cc_regfile_reads 272007090 # number of cc regfile reads +system.cpu0.cc_regfile_writes 28371958 # number of cc regfile writes +system.cpu0.misc_regfile_reads 192053211 # number of misc regfile reads +system.cpu0.misc_regfile_writes 725022 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 853093 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.984491 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42526051 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 853605 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.819356 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 91705250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 328.271130 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 183.713292 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.641155 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.358815 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 331.074612 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 180.909879 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.646630 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.353340 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189853089 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189853089 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12598830 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12738851 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25337681 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7730207 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8172441 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15902648 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180909 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 181454 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 362363 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 207827 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 238877 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446704 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 213772 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 245645 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459417 # 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number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 84905 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 181845 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13431 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14182 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27613 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 189920314 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189920314 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12675400 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12670649 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25346049 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7759190 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 8148697 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15907887 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 181607 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180873 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 362480 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209218 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 237638 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 446856 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 215214 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 244406 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459620 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20434590 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20819346 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41253936 # 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number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14194 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 27682 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 28 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 49 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 77 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2336227 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2195424 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4531651 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2433167 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2280329 # number of overall misses -system.cpu0.dcache.overall_misses::total 4713496 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7006933211 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6629197868 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13636131079 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84645436904 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 74845310131 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 159490747035 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 183007245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 209517243 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 392524488 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 467508 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 867018 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 1334526 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 91652370115 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 81474507999 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 173126878114 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 91652370115 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 81474507999 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 173126878114 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 13021272 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 13144717 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26165989 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9643992 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9961999 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19605991 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 277849 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 266359 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 544208 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 221258 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 253059 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 474317 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 213800 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 245694 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459494 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 22665264 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 23106716 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 45771980 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 22943113 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 23373075 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 46316188 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032442 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030877 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.031656 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.198443 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.179638 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188888 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.348895 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.318762 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.334146 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060703 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056042 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058216 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000131 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000199 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000168 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.103075 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.095012 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.099005 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.106052 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.097562 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.101768 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16586.734300 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16333.464414 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16462.633560 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44229.334488 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41823.349749 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43066.695965 # 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average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35729.277661 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36730.036074 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1114371 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 157529 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 70035 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2409 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.911630 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 65.391864 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 50 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 78 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2352192 # 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miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16483.409943 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16522.409045 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16502.236047 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43525.591556 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42560.881650 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43061.672910 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13582.109579 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14764.178033 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14188.217506 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21161 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17070.320000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18538.769231 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38589.784552 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37779.535913 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 38199.871400 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37049.973471 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36377.084823 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36726.647281 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1109617 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 154794 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 70377 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 2390 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.766756 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 64.767364 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 703475 # number of writebacks -system.cpu0.dcache.writebacks::total 703475 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 210719 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 192078 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 402797 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1759982 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1643688 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 18739292039 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10628456705 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9989890346 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 20618347051 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3173952500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2610543001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784495501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2430739877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2005307000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436046877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5604692377 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4615850001 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220542378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016260 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016264 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016262 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015948 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014643 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228304 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.218521 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223516 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017780 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020470 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019215 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000131 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000199 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000168 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016127 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015565 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015843 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018697 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017878 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018284 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13513.315086 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13667.806116 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13590.935473 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44130.918058 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42289.243196 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43234.457208 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15447.701627 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15447.908376 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15447.800557 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11914.209710 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15351.351931 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13867.731402 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14696.142857 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15693.510204 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15330.831169 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26396.336239 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25276.081274 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25840.741162 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24777.267589 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23907.094780 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24347.882676 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 50 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 78 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 368071 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 357585 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 725656 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 432146 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 415143 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 847289 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2880376399 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2931260112 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5811636511 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6719128315 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6232840178 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12951968493 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 978421259 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 894015008 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1872436267 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 46952751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79934003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 126886754 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 536492 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 753484 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1289976 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9599504714 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9164100290 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 18763605004 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10577925973 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10058115298 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 20636041271 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3170222000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2614349000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784571000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2418015877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2018079000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436094877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5588237877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4632428000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220665877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016308 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016242 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016275 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015943 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014630 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015279 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229359 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.217205 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223443 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017732 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020772 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019345 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000205 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000170 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016153 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015546 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015848 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018735 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017843 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018287 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13478.219605 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13806.770002 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13641.954947 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43527.537428 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42902.554244 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43224.521409 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15269.937714 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15532.419612 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15394.146876 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11889.782477 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15280.826419 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13822.086492 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19160.428571 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15069.680000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16538.153846 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26080.578785 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25627.753653 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25857.437965 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24477.667207 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24228.073936 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24355.374932 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1007,150 +1027,150 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1944459 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.580154 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 39104715 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1944971 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.105552 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1945413 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.581807 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 39117111 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1945925 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.102065 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 9481344250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 279.534125 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 232.046029 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.545965 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.453215 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999180 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.889096 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 233.692710 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.542752 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.456431 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999183 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 158 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43134734 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43134734 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19500172 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19604543 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 39104715 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19500172 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19604543 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 39104715 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19500172 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19604543 # 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number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20650160 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 41189665 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 20539505 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20650160 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 41189665 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050602 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050635 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050618 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050602 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050635 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050618 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050602 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050635 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050618 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13676.030639 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13584.820646 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13630.288190 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13676.030639 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13584.820646 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13630.288190 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13676.030639 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13584.820646 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13630.288190 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 9244 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43149539 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43149539 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 19581058 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19536053 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 39117111 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19581058 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19536053 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 39117111 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19581058 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19536053 # number of overall hits +system.cpu0.icache.overall_hits::total 39117111 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1050436 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1035972 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2086408 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1050436 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1035972 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2086408 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1050436 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 1035972 # number of overall misses +system.cpu0.icache.overall_misses::total 2086408 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14355946637 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14071596928 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28427543565 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14355946637 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 14071596928 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28427543565 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14355946637 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14071596928 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28427543565 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 20631494 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20572025 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 41203519 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 20631494 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20572025 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 41203519 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 20631494 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20572025 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 41203519 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050914 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050358 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050637 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050914 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050358 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050637 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050914 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050358 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050637 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13666.655215 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13582.989625 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13625.112425 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13666.655215 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13582.989625 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13625.112425 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13666.655215 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13582.989625 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13625.112425 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 9173 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 502 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 525 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.414343 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.472381 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 69295 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 70585 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 139880 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 69295 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 70585 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 139880 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 69295 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 70585 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 139880 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 970038 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 975032 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1945070 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 970038 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 975032 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1945070 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 970038 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 975032 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1945070 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11608622245 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11596487286 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 23205109531 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11608622245 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11596487286 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 23205109531 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11608622245 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11596487286 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 23205109531 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 70447 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 69940 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 140387 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 70447 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 69940 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 140387 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 70447 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 69940 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 140387 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 979989 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 966032 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1946021 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 979989 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 966032 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1946021 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 979989 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 966032 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1946021 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11725666308 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11493227261 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 23218893569 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11725666308 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11493227261 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 23218893569 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11725666308 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11493227261 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 23218893569 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 49455500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 49455500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49455500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 49455500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047228 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047217 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047222 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047228 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047217 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047222 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047228 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047217 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047222 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.182981 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11893.442765 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11930.218209 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.182981 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11893.442765 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11930.218209 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.182981 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11893.442765 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11930.218209 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047500 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046959 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047229 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047500 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046959 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047229 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047500 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046959 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047229 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11965.099923 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11897.356672 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11931.471227 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11965.099923 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11897.356672 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11931.471227 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11965.099923 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11897.356672 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11931.471227 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27351704 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14236490 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 554287 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17308437 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 12845549 # Number of BTB hits +system.cpu1.branchPred.lookups 27255758 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14164958 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 545624 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17245755 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 12796801 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 74.215534 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6761805 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29778 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 74.202614 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6756979 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29539 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1174,25 +1194,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14383095 # DTB read hits -system.cpu1.dtb.read_misses 49639 # DTB read misses -system.cpu1.dtb.write_hits 10688826 # DTB write hits -system.cpu1.dtb.write_misses 9570 # DTB write misses -system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 14301761 # DTB read hits +system.cpu1.dtb.read_misses 48555 # DTB read misses +system.cpu1.dtb.write_hits 10652785 # DTB write hits +system.cpu1.dtb.write_misses 10002 # DTB write misses +system.cpu1.dtb.flush_tlb 175 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3468 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 807 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1316 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3340 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 749 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1278 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14432734 # DTB read accesses -system.cpu1.dtb.write_accesses 10698396 # DTB write accesses +system.cpu1.dtb.perms_faults 539 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14350316 # DTB read accesses +system.cpu1.dtb.write_accesses 10662787 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25071921 # DTB hits -system.cpu1.dtb.misses 59209 # DTB misses -system.cpu1.dtb.accesses 25131130 # DTB accesses +system.cpu1.dtb.hits 24954546 # DTB hits +system.cpu1.dtb.misses 58557 # DTB misses +system.cpu1.dtb.accesses 25013103 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1214,333 +1234,334 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 20651947 # ITB inst hits -system.cpu1.itb.inst_misses 7444 # ITB inst misses +system.cpu1.itb.inst_hits 20573712 # ITB inst hits +system.cpu1.itb.inst_misses 7567 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 175 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2253 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2209 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1346 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1224 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20659391 # ITB inst accesses -system.cpu1.itb.hits 20651947 # DTB hits -system.cpu1.itb.misses 7444 # DTB misses -system.cpu1.itb.accesses 20659391 # DTB accesses -system.cpu1.numCycles 107242437 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20581279 # ITB inst accesses +system.cpu1.itb.hits 20573712 # DTB hits +system.cpu1.itb.misses 7567 # DTB misses +system.cpu1.itb.accesses 20581279 # DTB accesses +system.cpu1.numCycles 106992745 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40725111 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 106781914 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27351704 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19607354 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 61789362 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3232365 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 107163 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 4234 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 436 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 251985 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 137059 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 228 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20650163 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 382444 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3144 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104631724 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.228100 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.325979 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40476291 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 106336791 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27255758 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19553780 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 61749013 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3214085 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 109935 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 4125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 398 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 310457 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 137038 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20572028 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 377209 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3305 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104394378 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.225923 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.323476 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 75276621 71.94% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3919456 3.75% 75.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2502030 2.39% 78.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8106690 7.75% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1591855 1.52% 87.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1179587 1.13% 88.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6153020 5.88% 94.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1148569 1.10% 95.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4753896 4.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 75141351 71.98% 71.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3905835 3.74% 75.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2486724 2.38% 78.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8099869 7.76% 85.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1581267 1.51% 87.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1170303 1.12% 88.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6153110 5.89% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1141979 1.09% 95.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4713940 4.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104631724 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.255046 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.995706 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27872686 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 57819434 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15751164 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1722324 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1465861 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1979467 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 152392 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 89250616 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 494405 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1465861 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28821025 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6714609 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 45327507 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16516394 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 5786062 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 85371989 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2599 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1571177 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 234219 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 3175787 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 88221695 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 393591898 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 95352384 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6204 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 74304877 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13916818 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1590220 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1488950 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10060689 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15200897 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11860337 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2181365 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2795831 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 82084086 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1161665 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 78697860 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94798 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10134538 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 25514104 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 106722 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104631724 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.752141 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.431263 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 104394378 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.254744 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.993869 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27669699 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 57891094 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15657559 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1717451 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1458318 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1956668 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 150768 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 88739686 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 487490 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1458318 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28613011 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 6694397 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 45325373 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16423590 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 5879419 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 84880856 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2064 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1581177 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 275105 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 3240122 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 87684483 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 391488803 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 94864107 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5764 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 73992323 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13692160 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1588753 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1487965 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10049323 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15109971 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11816534 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2163704 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2733219 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 81632312 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1156422 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 78295274 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93656 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9981310 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25207475 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 106198 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104394378 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.749995 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.429509 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 72948361 69.72% 69.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10716718 10.24% 79.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8047314 7.69% 87.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6681191 6.39% 94.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2496863 2.39% 96.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1548306 1.48% 97.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1467102 1.40% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 495605 0.47% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 230264 0.22% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72878860 69.81% 69.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10639333 10.19% 80.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8017923 7.68% 87.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6659758 6.38% 94.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2479715 2.38% 96.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1538380 1.47% 97.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1459445 1.40% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 494321 0.47% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 226643 0.22% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104631724 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104394378 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 103418 8.95% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 534479 46.25% 55.20% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 517677 44.80% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 101103 8.77% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 535174 46.44% 55.22% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 516045 44.78% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 138 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 52546114 66.77% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 58878 0.07% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4118 0.01% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14788040 18.79% 85.64% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11300566 14.36% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 125 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 52268288 66.76% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59024 0.08% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4106 0.01% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14700600 18.78% 85.61% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11263124 14.39% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 78697860 # Type of FU issued -system.cpu1.iq.rate 0.733831 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1155578 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014684 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 263263981 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 93425233 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 76303202 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 13839 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7410 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6119 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 79845879 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7421 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 368633 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 78295274 # Type of FU issued +system.cpu1.iq.rate 0.731781 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1152326 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014718 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 262217922 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 92814464 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 75924804 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12986 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6859 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5648 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 79440457 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7018 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 366358 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2206977 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2711 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 53558 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1154048 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2171723 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2780 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 52487 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1144439 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 194646 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 154093 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 191401 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 154292 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1465861 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4319089 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2154851 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 83386940 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 137036 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15200897 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11860337 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 585271 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 47319 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2094987 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 53558 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 256552 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 222245 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 478797 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 78084459 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14546039 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 554355 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1458318 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4304329 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2156600 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 82933418 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 134740 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15109971 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11816534 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 582996 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 47778 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2096463 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 52487 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 251579 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 218702 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 470281 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 77694436 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14463933 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 542445 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 141189 # number of nop insts executed -system.cpu1.iew.exec_refs 25737628 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14524352 # Number of branches executed -system.cpu1.iew.exec_stores 11191589 # Number of stores executed -system.cpu1.iew.exec_rate 0.728112 # Inst execution rate -system.cpu1.iew.wb_sent 77455792 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 76309321 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 39942887 # num instructions producing a value -system.cpu1.iew.wb_consumers 70003346 # num instructions consuming a value +system.cpu1.iew.exec_nop 144684 # number of nop insts executed +system.cpu1.iew.exec_refs 25618626 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14454326 # Number of branches executed +system.cpu1.iew.exec_stores 11154693 # Number of stores executed +system.cpu1.iew.exec_rate 0.726165 # Inst execution rate +system.cpu1.iew.wb_sent 77075073 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 75930452 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 39739983 # num instructions producing a value +system.cpu1.iew.wb_consumers 69711076 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.711559 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.570585 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.709679 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.570067 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 11462178 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1054943 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 403929 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 102065282 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.704569 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.588134 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11308333 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1050224 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 396863 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 101852612 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.703099 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.586744 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 73979562 72.48% 72.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12596710 12.34% 84.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6446210 6.32% 91.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2677597 2.62% 93.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1413220 1.38% 95.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 933927 0.92% 96.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1825426 1.79% 97.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 426013 0.42% 98.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1766617 1.73% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 73894552 72.55% 72.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12525380 12.30% 84.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6426003 6.31% 91.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2662589 2.61% 93.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1410437 1.38% 95.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 930996 0.91% 96.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1822810 1.79% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 425009 0.42% 98.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1754836 1.72% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 102065282 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 59241455 # Number of instructions committed -system.cpu1.commit.committedOps 71912019 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 101852612 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 58987480 # Number of instructions committed +system.cpu1.commit.committedOps 71612492 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23700209 # Number of memory references committed -system.cpu1.commit.loads 12993920 # Number of loads committed -system.cpu1.commit.membars 441872 # Number of memory barriers committed -system.cpu1.commit.branches 13745651 # Number of branches committed -system.cpu1.commit.fp_insts 6045 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 63021281 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2683532 # Number of function calls committed. +system.cpu1.commit.refs 23610343 # Number of memory references committed +system.cpu1.commit.loads 12938248 # Number of loads committed +system.cpu1.commit.membars 439261 # Number of memory barriers committed +system.cpu1.commit.branches 13694369 # Number of branches committed +system.cpu1.commit.fp_insts 5606 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 62760739 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2679383 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 48150599 66.96% 66.96% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57094 0.08% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4117 0.01% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 12993920 18.07% 85.11% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10706289 14.89% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 47940825 66.94% 66.94% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57221 0.08% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4103 0.01% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 12938248 18.07% 85.10% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10672095 14.90% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 71912019 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1766617 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 71612492 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1754836 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 171199210 # The number of ROB reads -system.cpu1.rob.rob_writes 169319306 # The number of ROB writes -system.cpu1.timesIdled 392561 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2610713 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2951410695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 59158214 # Number of Instructions Simulated -system.cpu1.committedOps 71828778 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.812807 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.812807 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.551631 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.551631 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 84962024 # number of integer regfile reads -system.cpu1.int_regfile_writes 48578648 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16598 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13166 # number of floating regfile writes -system.cpu1.cc_regfile_reads 275767015 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29005141 # number of cc regfile writes -system.cpu1.misc_regfile_reads 192510337 # number of misc regfile reads -system.cpu1.misc_regfile_writes 799392 # number of misc regfile writes +system.cpu1.rob.rob_reads 170535238 # The number of ROB reads +system.cpu1.rob.rob_writes 168387616 # The number of ROB writes +system.cpu1.timesIdled 388789 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2598367 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2951659136 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 58903233 # Number of Instructions Simulated +system.cpu1.committedOps 71528245 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.816415 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.816415 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550535 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550535 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 84575323 # number of integer regfile reads +system.cpu1.int_regfile_writes 48329446 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16299 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13042 # number of floating regfile writes +system.cpu1.cc_regfile_reads 274393748 # number of cc regfile reads +system.cpu1.cc_regfile_writes 28845956 # number of cc regfile writes +system.cpu1.misc_regfile_reads 191595742 # number of misc regfile reads +system.cpu1.misc_regfile_writes 795775 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30210 # Transaction distribution system.iobus.trans_dist::ReadResp 30210 # Transaction distribution system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1631,42 +1652,46 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326614949 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347069959 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36834534 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36834574 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 0.982055 # Cycle average of tags in use -system.iocache.tags.total_refs 16 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234012764000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.982055 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061378 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061378 # Average percentage of cache occupancy +system.iocache.tags.replacements 36411 # number of replacements +system.iocache.tags.tagsinuse 1.036467 # Cycle average of tags in use +system.iocache.tags.total_refs 28 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36427 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000769 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 234012835000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.036467 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064779 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064779 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328241 # Number of tag accesses -system.iocache.tags.data_accesses 328241 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 328229 # Number of tag accesses +system.iocache.tags.data_accesses 328229 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 27 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 27 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses system.iocache.ReadReq_misses::total 249 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36197 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36197 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29659377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29659377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29659377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29659377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29659377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29659377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29650777 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29650777 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9620896608 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9620896608 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29650777 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29650777 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29650777 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29650777 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1677,296 +1702,306 @@ system.iocache.overall_accesses::realview.ide 249 system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.999255 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.999255 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119113.963855 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119113.963855 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119113.963855 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119113.963855 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 119079.425703 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119079.425703 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265792.651546 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265792.651546 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119079.425703 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119079.425703 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119079.425703 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119079.425703 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56505 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7228 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.817515 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36162 # number of writebacks +system.iocache.writebacks::total 36162 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36197 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36197 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16710377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16710377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2225221106 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2225221106 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16710377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16710377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16710377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16710377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16701777 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16701777 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7738504756 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7738504756 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16701777 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16701777 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16701777 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16701777 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.999255 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999255 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67109.947791 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67109.947791 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67075.409639 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67075.409639 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213788.566898 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213788.566898 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67075.409639 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67075.409639 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67075.409639 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67075.409639 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104249 # number of replacements -system.l2c.tags.tagsinuse 65131.495439 # Cycle average of tags in use -system.l2c.tags.total_refs 3107593 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169488 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 18.335180 # Average number of references to valid blocks. +system.l2c.tags.replacements 104261 # number of replacements +system.l2c.tags.tagsinuse 65126.190512 # Cycle average of tags in use +system.l2c.tags.total_refs 3112631 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169500 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 18.363605 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48618.767189 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 47.674260 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000235 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5568.941246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2875.967216 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 44.339878 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4984.136716 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2991.668698 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.741864 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000727 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 48604.861621 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 48.289581 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000234 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5571.225601 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2881.829872 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 43.411642 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4982.002827 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2994.569133 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.741651 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 36739 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 964905 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 348035 # number of demand (read+write) hits -system.l2c.demand_hits::total 2711742 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 36819 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 9299 # number of overall hits -system.l2c.overall_hits::cpu0.inst 959030 # number of overall hits -system.l2c.overall_hits::cpu0.data 349621 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 36739 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7294 # number of overall hits -system.l2c.overall_hits::cpu1.inst 964905 # number of overall hits -system.l2c.overall_hits::cpu1.data 348035 # number of overall hits -system.l2c.overall_hits::total 2711742 # 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mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.320000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482325 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462572 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.472753 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001796 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000112 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.011238 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.189690 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001875 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010219 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.174210 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.061041 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001816 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000108 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.185622 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001869 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010193 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.178151 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061018 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001796 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000112 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.011238 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.189690 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001875 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010219 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.174210 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.061041 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67026.119403 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu0.data 0.185622 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001869 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010193 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.178151 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061018 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62939.311927 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68249.154993 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62482.734391 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69566.014635 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 65322.906692 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.781804 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10044.162983 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.500546 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62789.275336 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68457.461561 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62958.583037 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71153.569434 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 65815.992635 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.127916 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10161.450387 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10084.454182 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20050.800000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64274.914919 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65547.461649 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64869.592247 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67026.119403 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 13866.307692 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64141.581463 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65701.749106 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64881.275293 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62939.311927 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64620.091520 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62482.734391 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65977.465861 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64962.074596 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67026.119403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62789.275336 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64510.303765 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62958.583037 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66293.042370 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 65072.025171 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62939.311927 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64620.091520 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62482.734391 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65977.465861 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64962.074596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62789.275336 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64510.303765 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62958.583037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66293.042370 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 65072.025171 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -2147,57 +2182,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68015 # Transaction distribution -system.membus.trans_dist::ReadResp 68014 # Transaction distribution -system.membus.trans_dist::WriteReq 27608 # Transaction distribution -system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 95499 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4626 # Transaction distribution +system.membus.trans_dist::ReadReq 68031 # Transaction distribution +system.membus.trans_dist::ReadResp 68030 # Transaction distribution +system.membus.trans_dist::WriteReq 27609 # Transaction distribution +system.membus.trans_dist::WriteResp 27609 # Transaction distribution +system.membus.trans_dist::Writeback 131669 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36196 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36196 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4639 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 26 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4652 # Transaction distribution -system.membus.trans_dist::ReadExReq 138449 # Transaction distribution -system.membus.trans_dist::ReadExResp 138449 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4665 # Transaction distribution +system.membus.trans_dist::ReadExReq 138446 # Transaction distribution +system.membus.trans_dist::ReadExResp 138446 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464808 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 572448 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 572218 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681038 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17335960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17499937 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19819233 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 234 # Total snoops (count) -system.membus.snoop_fanout::samples 311043 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17318744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17482733 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4631872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22114605 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 524 # Total snoops (count) +system.membus.snoop_fanout::samples 347207 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 311043 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 347207 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 311043 # Request fanout histogram -system.membus.reqLayer0.occupancy 81528999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 347207 # Request fanout histogram +system.membus.reqLayer0.occupancy 81506999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 15812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1699500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1714000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1433996498 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1759264748 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1730108850 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1730266590 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38499466 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38512426 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2230,57 +2265,57 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2655847 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2655761 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 703475 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2657108 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2657013 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27609 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27609 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 704003 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36196 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2844 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 77 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 78 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2921 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296861 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296861 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891199 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533159 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43047 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169738 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6637143 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124509952 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99813985 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 66376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 294776 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224685089 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 69111 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3663534 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.009957 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.099284 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 296844 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296844 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3893099 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2534750 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42773 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169663 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6640285 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124570688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99881325 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 65944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 294780 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224812737 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 68939 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3665274 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.009944 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.099221 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3627058 99.00% 99.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36476 1.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3628828 99.01% 99.01% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36446 0.99% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3663534 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4671361722 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3665274 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4674358232 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 697500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 8762587438 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 8766890883 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3909721674 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3912089949 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26515368 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 26359345 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 96849116 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96778607 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 3042 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 0d43a2133..120ee67e1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,140 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.904683 # Number of seconds simulated -sim_ticks 2904682547500 # Number of ticks simulated -final_tick 2904682547500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.904915 # Number of seconds simulated +sim_ticks 2904914753500 # Number of ticks simulated +final_tick 2904914753500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 744036 # Simulator instruction rate (inst/s) -host_op_rate 897074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19213049576 # Simulator tick rate (ticks/s) -host_mem_usage 562336 # Number of bytes of host memory used -host_seconds 151.18 # Real time elapsed on the host -sim_insts 112485415 # Number of instructions simulated -sim_ops 135622211 # Number of ops (including micro ops) simulated +host_inst_rate 754235 # Simulator instruction rate (inst/s) +host_op_rate 909375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19474929667 # Simulator tick rate (ticks/s) +host_mem_usage 559844 # Number of bytes of host memory used +host_seconds 149.16 # Real time elapsed on the host +sim_insts 112502966 # Number of instructions simulated +sim_ops 135643907 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 557732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4265248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 552740 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4263328 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 631552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4773892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 636352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4758276 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10229960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 557732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 631552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1189284 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5300352 # Number of bytes written to this memory +system.physmem.bytes_read::total 10212232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 552740 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 636352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1189092 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7616448 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 7636212 # Number of bytes written to this memory +system.physmem.bytes_written::total 7633972 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 67163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17090 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67133 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9868 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9943 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74349 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168816 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82818 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168539 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119007 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123423 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123388 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 192011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1468404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 190278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1467626 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 217425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1643516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3521886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 192011 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 217425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409437 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1824761 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 219060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1638009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3515501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 219060 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 409338 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2621918 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 798137 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2628932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1824761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2627950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2621918 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 192011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1474434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 190278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1473656 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 217425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1643519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 798468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6150817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168816 # Number of read requests accepted -system.physmem.writeReqs 123423 # Number of write requests accepted -system.physmem.readBursts 168816 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123423 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10794880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 7651200 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10229960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7636212 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9768 # Per bank write bursts -system.physmem.perBankRdBursts::1 9653 # Per bank write bursts -system.physmem.perBankRdBursts::2 10324 # Per bank write bursts -system.physmem.perBankRdBursts::3 9994 # Per bank write bursts -system.physmem.perBankRdBursts::4 18675 # Per bank write bursts -system.physmem.perBankRdBursts::5 10148 # Per bank write bursts -system.physmem.perBankRdBursts::6 10372 # Per bank write bursts -system.physmem.perBankRdBursts::7 10429 # Per bank write bursts -system.physmem.perBankRdBursts::8 9938 # Per bank write bursts -system.physmem.perBankRdBursts::9 10451 # Per bank write bursts -system.physmem.perBankRdBursts::10 9811 # Per bank write bursts -system.physmem.perBankRdBursts::11 9561 # Per bank write bursts -system.physmem.perBankRdBursts::12 9986 # Per bank write bursts -system.physmem.perBankRdBursts::13 9803 # Per bank write bursts -system.physmem.perBankRdBursts::14 9966 # Per bank write bursts -system.physmem.perBankRdBursts::15 9791 # Per bank write bursts -system.physmem.perBankWrBursts::0 7253 # Per bank write bursts -system.physmem.perBankWrBursts::1 7191 # Per bank write bursts -system.physmem.perBankWrBursts::2 8157 # Per bank write bursts -system.physmem.perBankWrBursts::3 7614 # Per bank write bursts -system.physmem.perBankWrBursts::4 7092 # Per bank write bursts -system.physmem.perBankWrBursts::5 7380 # Per bank write bursts -system.physmem.perBankWrBursts::6 7560 # Per bank write bursts -system.physmem.perBankWrBursts::7 7725 # Per bank write bursts -system.physmem.perBankWrBursts::8 7575 # Per bank write bursts -system.physmem.perBankWrBursts::9 8007 # Per bank write bursts -system.physmem.perBankWrBursts::10 7415 # Per bank write bursts -system.physmem.perBankWrBursts::11 7436 # Per bank write bursts -system.physmem.perBankWrBursts::12 7462 # Per bank write bursts -system.physmem.perBankWrBursts::13 7248 # Per bank write bursts -system.physmem.perBankWrBursts::14 7309 # Per bank write bursts -system.physmem.perBankWrBursts::15 7126 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 219060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1638012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6143452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168539 # Number of read requests accepted +system.physmem.writeReqs 159612 # Number of write requests accepted +system.physmem.readBursts 168539 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159612 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10780160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue +system.physmem.bytesWritten 9866880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10212232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9952308 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5435 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4495 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9752 # Per bank write bursts +system.physmem.perBankRdBursts::1 9630 # Per bank write bursts +system.physmem.perBankRdBursts::2 10293 # Per bank write bursts +system.physmem.perBankRdBursts::3 9989 # Per bank write bursts +system.physmem.perBankRdBursts::4 18671 # Per bank write bursts +system.physmem.perBankRdBursts::5 10140 # Per bank write bursts +system.physmem.perBankRdBursts::6 10341 # Per bank write bursts +system.physmem.perBankRdBursts::7 10423 # Per bank write bursts +system.physmem.perBankRdBursts::8 9932 # Per bank write bursts +system.physmem.perBankRdBursts::9 10445 # Per bank write bursts +system.physmem.perBankRdBursts::10 9791 # Per bank write bursts +system.physmem.perBankRdBursts::11 9555 # Per bank write bursts +system.physmem.perBankRdBursts::12 9939 # Per bank write bursts +system.physmem.perBankRdBursts::13 9802 # Per bank write bursts +system.physmem.perBankRdBursts::14 9961 # Per bank write bursts +system.physmem.perBankRdBursts::15 9776 # Per bank write bursts +system.physmem.perBankWrBursts::0 9466 # Per bank write bursts +system.physmem.perBankWrBursts::1 9312 # Per bank write bursts +system.physmem.perBankWrBursts::2 10445 # Per bank write bursts +system.physmem.perBankWrBursts::3 9717 # Per bank write bursts +system.physmem.perBankWrBursts::4 9000 # Per bank write bursts +system.physmem.perBankWrBursts::5 9463 # Per bank write bursts +system.physmem.perBankWrBursts::6 9580 # Per bank write bursts +system.physmem.perBankWrBursts::7 9878 # Per bank write bursts +system.physmem.perBankWrBursts::8 9939 # Per bank write bursts +system.physmem.perBankWrBursts::9 10290 # Per bank write bursts +system.physmem.perBankWrBursts::10 9717 # Per bank write bursts +system.physmem.perBankWrBursts::11 9744 # Per bank write bursts +system.physmem.perBankWrBursts::12 9808 # Per bank write bursts +system.physmem.perBankWrBursts::13 9372 # Per bank write bursts +system.physmem.perBankWrBursts::14 9292 # Per bank write bursts +system.physmem.perBankWrBursts::15 9147 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2904682181000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2904914374000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159244 # Read request sizes (log2) +system.physmem.readPktSize::6 158967 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 119042 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.physmem.writePktSize::6 155231 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 244 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,170 +161,194 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58500 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 315.315419 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.678002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.865134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21233 36.30% 36.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14762 25.23% 61.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5741 9.81% 71.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3177 5.43% 76.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2294 3.92% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1562 2.67% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1019 1.74% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1097 1.88% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7615 13.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58500 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5866 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.752472 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 562.127013 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5865 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11010 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60664 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.349730 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 196.021429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 354.920810 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21349 35.19% 35.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14624 24.11% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5778 9.52% 68.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3154 5.20% 74.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2318 3.82% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1542 2.54% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1044 1.72% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1115 1.84% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9740 16.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60664 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6204 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.148614 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 546.636063 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6203 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5866 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.380157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.599784 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.515949 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 10 0.17% 0.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 13 0.22% 0.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 18 0.31% 0.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4930 84.04% 85.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 59 1.01% 86.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 57 0.97% 86.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 249 4.24% 91.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 210 3.58% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.34% 95.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 11 0.19% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.14% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 30 0.51% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.09% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.07% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.05% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 157 2.68% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 19 0.32% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 6 0.10% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.10% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 6 0.10% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.12% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5866 # Writes before turning the bus around for reads -system.physmem.totQLat 1486855250 # Total ticks spent queuing -system.physmem.totMemAccLat 4649417750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 843350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8815.17 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6204 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6204 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.850097 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.346548 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.047003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 14 0.23% 0.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 12 0.19% 0.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 8 0.13% 0.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 18 0.29% 0.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4939 79.61% 80.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 68 1.10% 81.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 50 0.81% 82.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 255 4.11% 86.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 123 1.98% 88.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 43 0.69% 89.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.74% 89.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 38 0.61% 90.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 127 2.05% 92.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.18% 92.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 16 0.26% 92.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.13% 93.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 34 0.55% 93.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 17 0.27% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 13 0.21% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 28 0.45% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 70 1.13% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 11 0.18% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.11% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 13 0.21% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 92 1.48% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 97.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 13 0.21% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 5 0.08% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 13 0.21% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.06% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 6 0.10% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 29 0.47% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 12 0.19% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 7 0.11% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.10% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 6 0.10% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 4 0.06% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.06% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 6 0.10% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6204 # Writes before turning the bus around for reads +system.physmem.totQLat 1487388750 # Total ticks spent queuing +system.physmem.totMemAccLat 4645638750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 842200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8830.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27565.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27580.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.43 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.56 # Average write queue length when enqueuing -system.physmem.readRowHits 139006 # Number of row buffer hits during reads -system.physmem.writeRowHits 90713 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.41 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.88 # Row buffer hit rate for writes -system.physmem.avgGap 9939406.38 # Average gap between requests -system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2756105768250 # Time in different power states -system.physmem.memoryStateTime::REF 96993520000 # Time in different power states +system.physmem.avgWrQLen 11.55 # Average write queue length when enqueuing +system.physmem.readRowHits 138839 # Number of row buffer hits during reads +system.physmem.writeRowHits 123106 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.85 # Row buffer hit rate for writes +system.physmem.avgGap 8852370.93 # Average gap between requests +system.physmem.pageHitRate 81.19 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2756204372250 # Time in different power states +system.physmem.memoryStateTime::REF 97001320000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 51577106750 # Time in different power states +system.physmem.memoryStateTime::ACT 51708967750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 224736120 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 217523880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 122623875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 118688625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 697031400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 618579000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 388618560 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 386065440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 189719325120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 189719325120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86946648885 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 86006740545 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1666536838500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1667361319500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1944635822460 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1944428242110 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.484503 # Core power per rank (mW) -system.physmem.averagePower::1 669.413038 # Core power per rank (mW) +system.physmem.actEnergy::0 232462440 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 226157400 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 126839625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 123399375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 696064200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 617760000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 498059280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 500962320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 189734581920 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 189734581920 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 86971409685 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 86091461640 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1666655279250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1667427163500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1944914696400 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1944721486155 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.526666 # Core power per rank (mW) +system.physmem.averagePower::1 669.460155 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -370,25 +391,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12289553 # DTB read hits -system.cpu0.dtb.read_misses 5977 # DTB read misses -system.cpu0.dtb.write_hits 9834643 # DTB write hits -system.cpu0.dtb.write_misses 1047 # DTB write misses -system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12308215 # DTB read hits +system.cpu0.dtb.read_misses 6223 # DTB read misses +system.cpu0.dtb.write_hits 9796614 # DTB write hits +system.cpu0.dtb.write_misses 1025 # DTB write misses +system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4657 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4667 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 865 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 862 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12295530 # DTB read accesses -system.cpu0.dtb.write_accesses 9835690 # DTB write accesses +system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12314438 # DTB read accesses +system.cpu0.dtb.write_accesses 9797639 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22124196 # DTB hits -system.cpu0.dtb.misses 7024 # DTB misses -system.cpu0.dtb.accesses 22131220 # DTB accesses +system.cpu0.dtb.hits 22104829 # DTB hits +system.cpu0.dtb.misses 7248 # DTB misses +system.cpu0.dtb.accesses 22112077 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -410,224 +431,228 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 58032770 # ITB inst hits -system.cpu0.itb.inst_misses 3465 # ITB inst misses +system.cpu0.itb.inst_hits 58194599 # ITB inst hits +system.cpu0.itb.inst_misses 3600 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2765 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58036235 # ITB inst accesses -system.cpu0.itb.hits 58032770 # DTB hits -system.cpu0.itb.misses 3465 # DTB misses -system.cpu0.itb.accesses 58036235 # DTB accesses -system.cpu0.numCycles 2905319694 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 58198199 # ITB inst accesses +system.cpu0.itb.hits 58194599 # DTB hits +system.cpu0.itb.misses 3600 # DTB misses +system.cpu0.itb.accesses 58198199 # DTB accesses +system.cpu0.numCycles 2905784484 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 56513131 # Number of instructions committed -system.cpu0.committedOps 68067849 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60172046 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 6287 # Number of float alu accesses -system.cpu0.num_func_calls 4924583 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7649378 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60172046 # number of integer instructions -system.cpu0.num_fp_insts 6287 # number of float instructions -system.cpu0.num_int_register_reads 109432768 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41532346 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4990 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245794871 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26123486 # number of times the CC registers were written -system.cpu0.num_mem_refs 22763364 # number of memory refs -system.cpu0.num_load_insts 12450622 # Number of load instructions -system.cpu0.num_store_insts 10312742 # Number of store instructions -system.cpu0.num_idle_cycles 2685746001.120693 # Number of idle cycles -system.cpu0.num_busy_cycles 219573692.879307 # Number of busy cycles -system.cpu0.not_idle_fraction 0.075576 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.924424 # Percentage of idle cycles -system.cpu0.Branches 12983457 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46789630 67.21% 67.21% # Class of executed instruction -system.cpu0.op_class::IntMult 58620 0.08% 67.30% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4273 0.01% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::MemRead 12450622 17.88% 85.19% # Class of executed instruction -system.cpu0.op_class::MemWrite 10312742 14.81% 100.00% # Class of executed instruction +system.cpu0.committedInsts 56652370 # Number of instructions committed +system.cpu0.committedOps 68154355 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60226518 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5995 # Number of float alu accesses +system.cpu0.num_func_calls 4919534 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7679282 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60226518 # number of integer instructions +system.cpu0.num_fp_insts 5995 # number of float instructions +system.cpu0.num_int_register_reads 109459523 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41576844 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4468 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1530 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 246082665 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26221599 # number of times the CC registers were written +system.cpu0.num_mem_refs 22745945 # number of memory refs +system.cpu0.num_load_insts 12471278 # Number of load instructions +system.cpu0.num_store_insts 10274667 # Number of store instructions +system.cpu0.num_idle_cycles 2686990403.807933 # Number of idle cycles +system.cpu0.num_busy_cycles 218794080.192067 # Number of busy cycles +system.cpu0.not_idle_fraction 0.075296 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.924704 # Percentage of idle cycles +system.cpu0.Branches 13013332 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46892920 67.27% 67.28% # Class of executed instruction +system.cpu0.op_class::IntMult 58660 0.08% 67.36% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4258 0.01% 67.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.37% # Class of executed instruction +system.cpu0.op_class::MemRead 12471278 17.89% 85.26% # Class of executed instruction +system.cpu0.op_class::MemWrite 10274667 14.74% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 69618091 # Class of executed instruction +system.cpu0.op_class::total 69703986 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 822992 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.850755 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43241503 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 823504 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.509160 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 822947 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.850765 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43250055 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 823459 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.522415 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.068917 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.781838 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625135 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374574 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.083666 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.767099 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625163 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374545 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999709 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177151535 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177151535 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11581583 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11533865 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23115448 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9437909 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9389790 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18827699 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199753 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192262 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392015 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227025 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 216269 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443294 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 235239 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 225055 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460294 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 21019492 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20923655 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41943147 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 21219245 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21115917 # number of overall hits -system.cpu0.dcache.overall_hits::total 42335162 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197297 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 205526 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 402823 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 150193 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 148466 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298659 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58530 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 60464 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118994 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11127 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11645 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22772 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 177185510 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177185510 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11600521 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791429000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2186315500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2243484000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429799500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4875127500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5346101000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221228500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016885 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017304 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017094 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.218539 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.238633 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228599 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017166 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019626 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018366 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016250 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016621 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016435 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018721 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019177 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018948 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.616669 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.159388 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12718.720786 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36064.216235 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.478231 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37237.026000 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12075.821059 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12533.247780 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11788.705739 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11808.144746 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11798.843188 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23999 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23999 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.506490 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.434296 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.655297 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.687876 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22026.725583 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21614.799112 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016260 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016603 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016431 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018649 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019238 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018943 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12637.196667 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12818.141148 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12728.480263 # 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average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 73500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 73500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22711.466274 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23634.542734 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23177.325257 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21248.542343 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21993.461902 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21626.398123 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # 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mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11699.709629 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11699.709629 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11699.709629 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014572 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014847 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014572 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014847 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014572 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014847 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014708 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11631.383891 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11764.580979 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11698.151448 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11631.383891 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11764.580979 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11698.151448 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11631.383891 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11764.580979 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11698.151448 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency @@ -898,25 +927,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12236392 # DTB read hits -system.cpu1.dtb.read_misses 5657 # DTB read misses -system.cpu1.dtb.write_hits 9775692 # DTB write hits -system.cpu1.dtb.write_misses 790 # DTB write misses -system.cpu1.dtb.flush_tlb 2934 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12222550 # DTB read hits +system.cpu1.dtb.read_misses 5478 # DTB read misses +system.cpu1.dtb.write_hits 9817405 # DTB write hits +system.cpu1.dtb.write_misses 801 # DTB write misses +system.cpu1.dtb.flush_tlb 2935 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4044 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4101 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 918 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 936 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12242049 # DTB read accesses -system.cpu1.dtb.write_accesses 9776482 # DTB write accesses +system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12228028 # DTB read accesses +system.cpu1.dtb.write_accesses 9818206 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22012084 # DTB hits -system.cpu1.dtb.misses 6447 # DTB misses -system.cpu1.dtb.accesses 22018531 # DTB accesses +system.cpu1.dtb.hits 22039955 # DTB hits +system.cpu1.dtb.misses 6279 # DTB misses +system.cpu1.dtb.accesses 22046234 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -938,93 +967,94 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 57551182 # ITB inst hits -system.cpu1.itb.inst_misses 3277 # ITB inst misses +system.cpu1.itb.inst_hits 57407239 # ITB inst hits +system.cpu1.itb.inst_misses 3155 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2934 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2935 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2396 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2356 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 57554459 # ITB inst accesses -system.cpu1.itb.hits 57551182 # DTB hits -system.cpu1.itb.misses 3277 # DTB misses -system.cpu1.itb.accesses 57554459 # DTB accesses -system.cpu1.numCycles 2904045401 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 57410394 # ITB inst accesses +system.cpu1.itb.hits 57407239 # DTB hits +system.cpu1.itb.misses 3155 # DTB misses +system.cpu1.itb.accesses 57410394 # DTB accesses +system.cpu1.numCycles 2904045023 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55972284 # Number of instructions committed -system.cpu1.committedOps 67554362 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59752131 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5003 # Number of float alu accesses -system.cpu1.num_func_calls 4972365 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7584533 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59752131 # number of integer instructions -system.cpu1.num_fp_insts 5003 # number of float instructions -system.cpu1.num_int_register_reads 108688988 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41135378 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3588 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 244071190 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25783552 # number of times the CC registers were written -system.cpu1.num_mem_refs 22653716 # number of memory refs -system.cpu1.num_load_insts 12397911 # Number of load instructions -system.cpu1.num_store_insts 10255805 # Number of store instructions -system.cpu1.num_idle_cycles 2693922745.089012 # Number of idle cycles -system.cpu1.num_busy_cycles 210122655.910988 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072355 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927645 # Percentage of idle cycles -system.cpu1.Branches 12941389 # Number of branches fetched -system.cpu1.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46411475 67.14% 67.14% # Class of executed instruction -system.cpu1.op_class::IntMult 56055 0.08% 67.22% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4164 0.01% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::MemRead 12397911 17.94% 85.16% # Class of executed instruction -system.cpu1.op_class::MemWrite 10255805 14.84% 100.00% # Class of executed instruction +system.cpu1.committedInsts 55850596 # Number of instructions committed +system.cpu1.committedOps 67489552 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59717976 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5231 # Number of float alu accesses +system.cpu1.num_func_calls 4978644 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7556287 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59717976 # number of integer instructions +system.cpu1.num_fp_insts 5231 # number of float instructions +system.cpu1.num_int_register_reads 108697708 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41105654 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4046 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1186 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 243864682 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25692319 # number of times the CC registers were written +system.cpu1.num_mem_refs 22680019 # number of memory refs +system.cpu1.num_load_insts 12382292 # Number of load instructions +system.cpu1.num_store_insts 10297727 # Number of store instructions +system.cpu1.num_idle_cycles 2693854199.172201 # Number of idle cycles +system.cpu1.num_busy_cycles 210190823.827799 # Number of busy cycles +system.cpu1.not_idle_fraction 0.072379 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.927621 # Percentage of idle cycles +system.cpu1.Branches 12914403 # Number of branches fetched +system.cpu1.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 46321486 67.07% 67.07% # Class of executed instruction +system.cpu1.op_class::IntMult 56040 0.08% 67.15% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4215 0.01% 67.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.16% # Class of executed instruction +system.cpu1.op_class::MemRead 12382292 17.93% 85.09% # Class of executed instruction +system.cpu1.op_class::MemWrite 10297727 14.91% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69125543 # Class of executed instruction +system.cpu1.op_class::total 69061894 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 30195 # Transaction distribution system.iobus.trans_dist::ReadResp 30195 # Transaction distribution system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1115,38 +1145,40 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347067538 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804759 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804503 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.083103 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084296 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309429741000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.083103 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067694 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067694 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 309429812000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084296 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067768 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067768 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9591408658 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9591408658 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles @@ -1161,288 +1193,303 @@ system.iocache.overall_accesses::realview.ide 234 system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264780.495197 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264780.495197 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 55572 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7176 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.744147 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2203719731 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2203719731 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7707754664 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7707754664 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212780.329726 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212780.329726 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 89435 # number of replacements -system.l2c.tags.tagsinuse 64928.071220 # Cycle average of tags in use -system.l2c.tags.total_refs 2766032 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 64927.975067 # Cycle average of tags in use +system.l2c.tags.total_refs 2767630 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 154676 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.882748 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 17.893080 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50556.019197 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943993 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 50554.064375 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943925 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3889.866505 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2064.899938 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768384 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5760.330465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2651.242275 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.771424 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 3889.108934 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2070.927660 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768402 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5762.879674 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2645.281633 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.771394 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059355 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.031508 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.059343 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.031600 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.087896 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.040455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990724 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.087935 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.040364 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990722 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65236 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6815 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56246 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6816 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56245 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.995422 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26292076 # Number of tag accesses -system.l2c.tags.data_accesses 26292076 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6208 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3383 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 836467 # 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average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55979.022115 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56397.243053 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59800.427350 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63444.730466 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61469.007922 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.370370 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10079.045222 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10055.391768 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 60500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60500 # 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average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60084.515606 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56618.658303 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57321.604441 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59800.427350 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56812.065606 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57370.855040 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59942.185008 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57386.469559 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60112.752384 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57307.407335 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60084.515606 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56618.658303 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57321.604441 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59800.427350 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56812.065606 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57370.855040 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1604,57 +1655,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70576 # Transaction distribution -system.membus.trans_dist::ReadResp 70576 # Transaction distribution +system.membus.trans_dist::ReadReq 70575 # Transaction distribution +system.membus.trans_dist::ReadResp 70575 # Transaction distribution system.membus.trans_dist::WriteReq 27613 # Transaction distribution system.membus.trans_dist::WriteResp 27613 # Transaction distribution -system.membus.trans_dist::Writeback 82818 # Transaction distribution +system.membus.trans_dist::Writeback 119007 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4495 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 129059 # Transaction distribution -system.membus.trans_dist::ReadExResp 129059 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4497 # Transaction distribution +system.membus.trans_dist::ReadExReq 129060 # Transaction distribution +system.membus.trans_dist::ReadExResp 129060 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438204 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 545868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 618565 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 437896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 545560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 654447 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15710301 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18029597 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 219 # Total snoops (count) -system.membus.snoop_fanout::samples 283019 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15529084 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15692509 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20327965 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 498 # Total snoops (count) +system.membus.snoop_fanout::samples 319191 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 283019 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 319191 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 283019 # Request fanout histogram -system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 319191 # Request fanout histogram +system.membus.reqLayer0.occupancy 87172500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1736000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1735000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1336695000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1640329489 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1662315000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 1640286255 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38333497 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1687,54 +1738,54 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2301469 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2301454 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2303097 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2303082 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 686960 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36226 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 686899 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2744 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295908 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295908 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415392 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457281 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34351 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5925146 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868901 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46156 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205690309 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 53730 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3283144 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104794 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2746 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295999 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295999 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3418625 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457116 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18180 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34622 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5928543 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108853880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96862117 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24836 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205787617 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 53694 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3284793 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.011099 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104766 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3246684 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36460 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3248335 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3283144 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4418882248 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3284793 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4419462750 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 7658490749 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 7665779999 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3782924511 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3782690745 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11971000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22834207 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22951201 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 864e98054..ecc4cd446 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,165 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.349475 # Number of seconds simulated -sim_ticks 47349475204500 # Number of ticks simulated -final_tick 47349475204500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.349389 # Number of seconds simulated +sim_ticks 47349388766500 # Number of ticks simulated +final_tick 47349388766500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170024 # Simulator instruction rate (inst/s) -host_op_rate 200007 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9521770968 # Simulator tick rate (ticks/s) -host_mem_usage 827688 # Number of bytes of host memory used -host_seconds 4972.76 # Real time elapsed on the host -sim_insts 845490438 # Number of instructions simulated -sim_ops 994586036 # Number of ops (including micro ops) simulated +host_inst_rate 148460 # Simulator instruction rate (inst/s) +host_op_rate 174619 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7799944718 # Simulator tick rate (ticks/s) +host_mem_usage 883812 # Number of bytes of host memory used +host_seconds 6070.48 # Real time elapsed on the host +sim_insts 901223526 # Number of instructions simulated +sim_ops 1060022042 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 457024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 242432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 409152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 13269720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 28432512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 254656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 419648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 10291040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 23441792 # Number of bytes read from this memory -system.physmem.bytes_read::total 77217976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3825664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 566400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4392064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 33722560 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.inst 56250828 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 43534148 # Number of bytes written to this memory -system.physmem.bytes_written::total 140338128 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 7141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 3788 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 6393 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 207361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 444258 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3979 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 6557 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 160812 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 366278 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1206567 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 526915 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.inst 881196 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 680222 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2195061 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 9652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 5120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 8641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 280251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 600482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 5378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 8863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 217342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 495080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1630810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 80796 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 712206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 144259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 1187993 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 919422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2963879 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 712206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 153911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 5120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 8641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 1468243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 600482 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 5378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 8863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1136764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 495080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4594689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1206567 # Number of read requests accepted -system.physmem.writeReqs 2195061 # Number of write requests accepted -system.physmem.readBursts 1206567 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2195061 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 76928704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 291584 # Total number of bytes read from write queue -system.physmem.bytesWritten 135133184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 77217976 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 140338128 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 4556 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 83588 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 93227 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 68916 # Per bank write bursts -system.physmem.perBankRdBursts::1 78372 # Per bank write bursts -system.physmem.perBankRdBursts::2 66961 # Per bank write bursts -system.physmem.perBankRdBursts::3 74483 # Per bank write bursts -system.physmem.perBankRdBursts::4 67860 # Per bank write bursts -system.physmem.perBankRdBursts::5 84994 # Per bank write bursts -system.physmem.perBankRdBursts::6 78873 # Per bank write bursts -system.physmem.perBankRdBursts::7 74831 # Per bank write bursts -system.physmem.perBankRdBursts::8 70689 # Per bank write bursts -system.physmem.perBankRdBursts::9 121049 # Per bank write bursts -system.physmem.perBankRdBursts::10 55712 # Per bank write bursts -system.physmem.perBankRdBursts::11 71204 # Per bank write bursts -system.physmem.perBankRdBursts::12 68805 # Per bank write bursts -system.physmem.perBankRdBursts::13 80552 # Per bank write bursts -system.physmem.perBankRdBursts::14 71313 # Per bank write bursts -system.physmem.perBankRdBursts::15 67397 # Per bank write bursts -system.physmem.perBankWrBursts::0 131295 # Per bank write bursts -system.physmem.perBankWrBursts::1 120115 # Per bank write bursts -system.physmem.perBankWrBursts::2 136218 # Per bank write bursts -system.physmem.perBankWrBursts::3 122111 # Per bank write bursts -system.physmem.perBankWrBursts::4 136290 # Per bank write bursts -system.physmem.perBankWrBursts::5 134780 # Per bank write bursts -system.physmem.perBankWrBursts::6 183921 # Per bank write bursts -system.physmem.perBankWrBursts::7 113990 # Per bank write bursts -system.physmem.perBankWrBursts::8 112648 # Per bank write bursts -system.physmem.perBankWrBursts::9 120303 # Per bank write bursts -system.physmem.perBankWrBursts::10 105255 # Per bank write bursts -system.physmem.perBankWrBursts::11 150368 # Per bank write bursts -system.physmem.perBankWrBursts::12 133266 # Per bank write bursts -system.physmem.perBankWrBursts::13 132701 # Per bank write bursts -system.physmem.perBankWrBursts::14 112511 # Per bank write bursts -system.physmem.perBankWrBursts::15 165684 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 126592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 108352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 12219800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 55224576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 171840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 160768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 11630176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 36221056 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 451968 # Number of bytes read from this memory +system.physmem.bytes_read::total 116315128 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4075008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 659840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4734848 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 84862912 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory +system.physmem.bytes_written::total 84883728 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1693 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 190956 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 862884 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2685 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2512 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 181736 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 565954 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7062 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1817460 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1325983 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1328586 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 258077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1166321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 245625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 764974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2456529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 86063 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 13936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 99998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1792270 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1792710 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1792270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 258517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1166321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 245625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 764974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4249239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1817460 # Number of read requests accepted +system.physmem.writeReqs 1459105 # Number of write requests accepted +system.physmem.readBursts 1817460 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1459105 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 116259968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 57472 # Total number of bytes read from write queue +system.physmem.bytesWritten 92884608 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 116315128 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 93236944 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 898 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7766 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 92270 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 109521 # Per bank write bursts +system.physmem.perBankRdBursts::1 125500 # Per bank write bursts +system.physmem.perBankRdBursts::2 109858 # Per bank write bursts +system.physmem.perBankRdBursts::3 118807 # Per bank write bursts +system.physmem.perBankRdBursts::4 114750 # Per bank write bursts +system.physmem.perBankRdBursts::5 133958 # Per bank write bursts +system.physmem.perBankRdBursts::6 108183 # Per bank write bursts +system.physmem.perBankRdBursts::7 109296 # Per bank write bursts +system.physmem.perBankRdBursts::8 104951 # Per bank write bursts +system.physmem.perBankRdBursts::9 157608 # Per bank write bursts +system.physmem.perBankRdBursts::10 96466 # Per bank write bursts +system.physmem.perBankRdBursts::11 111139 # Per bank write bursts +system.physmem.perBankRdBursts::12 103753 # Per bank write bursts +system.physmem.perBankRdBursts::13 116262 # Per bank write bursts +system.physmem.perBankRdBursts::14 95073 # Per bank write bursts +system.physmem.perBankRdBursts::15 101437 # Per bank write bursts +system.physmem.perBankWrBursts::0 88391 # Per bank write bursts +system.physmem.perBankWrBursts::1 94888 # Per bank write bursts +system.physmem.perBankWrBursts::2 89089 # Per bank write bursts +system.physmem.perBankWrBursts::3 94540 # Per bank write bursts +system.physmem.perBankWrBursts::4 92096 # Per bank write bursts +system.physmem.perBankWrBursts::5 104028 # Per bank write bursts +system.physmem.perBankWrBursts::6 87215 # Per bank write bursts +system.physmem.perBankWrBursts::7 89925 # Per bank write bursts +system.physmem.perBankWrBursts::8 85891 # Per bank write bursts +system.physmem.perBankWrBursts::9 90043 # Per bank write bursts +system.physmem.perBankWrBursts::10 85085 # Per bank write bursts +system.physmem.perBankWrBursts::11 94536 # Per bank write bursts +system.physmem.perBankWrBursts::12 86659 # Per bank write bursts +system.physmem.perBankWrBursts::13 94890 # Per bank write bursts +system.physmem.perBankWrBursts::14 85144 # Per bank write bursts +system.physmem.perBankWrBursts::15 88902 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 47349473266500 # Total gap between requests +system.physmem.totGap 47349386828500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1206525 # Read request sizes (log2) +system.physmem.readPktSize::6 1817418 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2192458 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 701586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 159041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 78388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 62534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 48409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 42357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24739 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 6356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1456502 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 724796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 275224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 218778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 130576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 121480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 92297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 78276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 67824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 54542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29215 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 6539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 3658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -183,158 +180,156 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 77454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 97715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 98472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 108608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 137758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 125184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 127483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 141417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 129468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 120366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 126014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 120082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 115005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 123737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 112481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 110136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 106316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 102758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 691339 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 306.739519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.472793 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.323128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 329714 47.69% 47.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 128094 18.53% 66.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 46159 6.68% 72.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24419 3.53% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20272 2.93% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13585 1.97% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10457 1.51% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 11430 1.65% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 107209 15.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 691339 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 99075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.132152 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 222.564559 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 99072 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 99075 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 99075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.311693 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.731664 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.258880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 33791 34.11% 34.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 48957 49.41% 83.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 10331 10.43% 93.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 2038 2.06% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1546 1.56% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 746 0.75% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 511 0.52% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 316 0.32% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 116 0.12% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 38 0.04% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 31 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 20 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 438 0.44% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 35 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 39 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 38 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 24 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 10 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 7 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 99075 # Writes before turning the bus around for reads -system.physmem.totQLat 32464480274 # Total ticks spent queuing -system.physmem.totMemAccLat 55002186524 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6010055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27008.47 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 20715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 37146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 48711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 55470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 75025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 82665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 93812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 97796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 101866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 103500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 107192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 100425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 105997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 102597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 17377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 13177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 894898 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 233.707153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.846498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.283402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 463489 51.79% 51.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 185877 20.77% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 67737 7.57% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36988 4.13% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 29329 3.28% 87.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 22133 2.47% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 15835 1.77% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13649 1.53% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 59861 6.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 894898 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 77790 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.351999 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 144.403085 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 77788 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 77790 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 77790 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.656922 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.550932 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.537959 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 73893 94.99% 94.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 1079 1.39% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 616 0.79% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 255 0.33% 97.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 611 0.79% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 159 0.20% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 204 0.26% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 127 0.16% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 198 0.25% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 57 0.07% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 225 0.29% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 47 0.06% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 57 0.07% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 49 0.06% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 102 0.13% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 22 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 26 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 13 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 77790 # Writes before turning the bus around for reads +system.physmem.totQLat 101322311265 # Total ticks spent queuing +system.physmem.totMemAccLat 135382848765 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9082810000 # Total ticks spent in databus transfers +system.physmem.avgQLat 55776.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45758.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.63 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.96 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 74526.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.37 # Average write queue length when enqueuing -system.physmem.readRowHits 944165 # Number of row buffer hits during reads -system.physmem.writeRowHits 1677959 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.47 # Row buffer hit rate for writes -system.physmem.avgGap 13919650.61 # Average gap between requests -system.physmem.pageHitRate 79.13 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45391806829500 # Time in different power states -system.physmem.memoryStateTime::REF 1581102900000 # Time in different power states +system.physmem.avgWrQLen 27.53 # Average write queue length when enqueuing +system.physmem.readRowHits 1479200 # Number of row buffer hits during reads +system.physmem.writeRowHits 893785 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.58 # Row buffer hit rate for writes +system.physmem.avgGap 14450922.48 # Average gap between requests +system.physmem.pageHitRate 72.61 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 45452153624500 # Time in different power states +system.physmem.memoryStateTime::REF 1581100040000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 376561525500 # Time in different power states +system.physmem.memoryStateTime::ACT 316134376000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2682083880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2544438960 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1463438625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1388334750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 4643184000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 4732392600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 6990105600 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 6692129280 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3092637272400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3092637272400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1220178523320 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1215644323230 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27339350706750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27343328075250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31667945314575 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31666966966470 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.813072 # Core power per rank (mW) -system.physmem.averagePower::1 668.792410 # Core power per rank (mW) +system.physmem.actEnergy::0 3577346640 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3188082240 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1951925250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1739529000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 7253009400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 6916111800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 4796314560 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 4608252000 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3092631678240 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3092631678240 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1196963299980 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1185023558430 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 27359663548500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 27370137006000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 31666837122570 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 31664244217710 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.790877 # Core power per rank (mW) +system.physmem.averagePower::1 668.736116 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory @@ -353,703 +348,22 @@ system.realview.nvmem.bw_inst_read::total 27 # I system.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1114990 # Transaction distribution -system.membus.trans_dist::ReadResp 1114990 # Transaction distribution -system.membus.trans_dist::WriteReq 37937 # Transaction distribution -system.membus.trans_dist::WriteResp 37937 # Transaction distribution -system.membus.trans_dist::Writeback 526915 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1665543 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1665543 # Transaction distribution -system.membus.trans_dist::UpgradeReq 343558 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 290459 # Transaction distribution -system.membus.trans_dist::UpgradeResp 93233 # Transaction distribution -system.membus.trans_dist::ReadExReq 145423 # Transaction distribution -system.membus.trans_dist::ReadExResp 131308 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 23584 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6789962 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6936516 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 229526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7166042 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 47168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210268488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 210473028 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7287616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7287616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 217760644 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 556693 # Total snoops (count) -system.membus.snoop_fanout::samples 3996553 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3996553 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3996553 # Request fanout histogram -system.membus.reqLayer0.occupancy 106711482 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 35984 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20060995 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 21791270978 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 13392760110 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187374753 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 893379 # number of replacements -system.l2c.tags.tagsinuse 64139.353797 # Cycle average of tags in use -system.l2c.tags.total_refs 6866398 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 953433 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 7.201762 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 10411.534254 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 170.665758 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 236.653363 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5522.014615 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 25703.497535 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 145.004713 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 188.005532 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6322.307070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 15439.670958 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.158867 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002604 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003611 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.084259 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.392204 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002213 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002869 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.096471 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.235591 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.978689 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 36012 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 260 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 23782 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 41 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 716 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1957 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 33290 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 190 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1450 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3907 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18298 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.549500 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.362885 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 80317062 # Number of tag accesses -system.l2c.tags.data_accesses 80317062 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 7070 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4466 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 557041 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 2033838 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 7318 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4580 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 521752 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1881001 # number of ReadReq hits -system.l2c.ReadReq_hits::total 5017066 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1844732 # number of Writeback hits -system.l2c.Writeback_hits::total 1844732 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 30097 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 27244 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 57341 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 7329 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 7124 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 14453 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 51408 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 52005 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 103413 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 7070 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4466 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 608449 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 2033838 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 7318 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4580 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 573757 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1881001 # number of demand (read+write) hits -system.l2c.demand_hits::total 5120479 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 7070 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4466 # number of overall hits -system.l2c.overall_hits::cpu0.inst 608449 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 2033838 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 7318 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4580 # number of overall hits -system.l2c.overall_hits::cpu1.inst 573757 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 1881001 # number of overall hits -system.l2c.overall_hits::total 5120479 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3788 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 6393 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 87512 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 444466 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3979 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 6557 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 97026 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 366468 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1016189 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 36620 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 34601 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 71221 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 9478 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 8512 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 17990 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 69660 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 65667 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 135327 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3788 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 6393 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 157172 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 444466 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3979 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 6557 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 162693 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 366468 # number of demand (read+write) misses -system.l2c.demand_misses::total 1151516 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3788 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 6393 # number of overall misses -system.l2c.overall_misses::cpu0.inst 157172 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 444466 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3979 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 6557 # number of overall misses -system.l2c.overall_misses::cpu1.inst 162693 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 366468 # number of overall misses -system.l2c.overall_misses::total 1151516 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 295641239 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 507564744 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 6935191428 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 312400496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 512318742 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 7688372365 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 99681339970 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 177719564 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 161535756 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 339255320 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 49426933 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 49799411 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 99226344 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 5124274653 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 4787449538 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9911724191 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 295641239 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 507564744 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 12059466081 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 312400496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 512318742 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 12475821903 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 109593064161 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 295641239 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 507564744 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 12059466081 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 312400496 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 512318742 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 12475821903 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of overall miss cycles -system.l2c.overall_miss_latency::total 109593064161 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 10858 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10859 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 644553 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2478304 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 11297 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 11137 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 618778 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2247469 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 6033255 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1844732 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1844732 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 66717 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 61845 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 128562 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 16807 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 15636 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 32443 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 121068 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 117672 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 238740 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 10858 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10859 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 765621 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2478304 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 11297 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 11137 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 736450 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2247469 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 6271995 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 10858 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10859 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 765621 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2478304 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 11297 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 11137 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 736450 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2247469 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 6271995 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.588728 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.135772 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.588758 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.156803 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.168431 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.548886 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.559479 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.553982 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.563932 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.544385 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.554511 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.575379 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.558051 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.566838 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.588728 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.205287 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.588758 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.220915 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.183596 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.588728 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.205287 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.588758 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.220915 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.183596 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79393.828250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79248.462245 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 78133.100808 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79240.331097 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 98093.307416 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 4853.073839 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 4668.528540 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4763.416970 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 5214.911690 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 5850.494713 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5515.638911 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 73561.220973 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 72904.952838 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73242.768930 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79393.828250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76727.827355 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 78133.100808 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76683.212572 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 95172.854012 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79393.828250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 76727.827355 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 78133.100808 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76683.212572 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 95172.854012 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 9985 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 293 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 34.078498 # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 526915 # number of writebacks -system.l2c.writebacks::total 526915 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 41 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 208 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 31 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 190 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 470 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 41 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 208 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 31 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 190 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 470 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 41 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 208 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 31 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 190 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 470 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3788 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 6393 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 87471 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3979 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 6557 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 96995 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 1015719 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 36620 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 34601 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 71221 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 9478 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 8512 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 17990 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 69660 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 65667 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 135327 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 3788 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 6393 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 157131 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 3979 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 6557 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 162662 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1151046 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 3788 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 6393 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 157131 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 3979 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 6557 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 162662 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1151046 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 428022244 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 5837610680 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 430600242 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 6471220731 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 87083288091 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 17889181875 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 13903512484 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 31792694359 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 372768590 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 351692080 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 724460670 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 96695300 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 86940850 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 183636150 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 4247852269 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 3960733380 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8208585649 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 428022244 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 10085462949 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 430600242 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 10431954111 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 95291873740 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 428022244 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 10085462949 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 430600242 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 10431954111 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 95291873740 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4946669501 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3170681000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 8117350501 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 2118382500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 3125324001 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5243706501 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7065052001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6296005001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 13361057002 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.135708 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.156753 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.168353 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.548886 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.559479 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.553982 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.563932 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.544385 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.554511 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.575379 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.558051 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.566838 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.205233 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.220873 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.183522 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.205233 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.220873 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.183522 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 66737.669399 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66717.054807 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 85735.610037 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10179.371655 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10164.217219 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10172.009239 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10202.078498 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10213.915648 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10207.679266 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 60979.791401 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60315.430582 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60657.412408 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 6929805 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 6922247 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 37937 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 37937 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1844732 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1558815 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 396880 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 304912 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 701792 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 286652 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 286652 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10302950 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9169444 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 19472394 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 332778181 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290120831 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 622899012 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1503135 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 11338555 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.010201 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.100485 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 11222888 98.98% 98.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115667 1.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 11338555 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 19325316227 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 6157500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 17505808152 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 16090621161 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40386 # Transaction distribution -system.iobus.trans_dist::ReadResp 40386 # Transaction distribution -system.iobus.trans_dist::WriteReq 136543 # Transaction distribution -system.iobus.trans_dist::WriteResp 136730 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 187 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48036 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354232 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156048 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36503000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 982100345 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92919000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179226247 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 130284886 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91971902 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5996877 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 97983342 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 71203631 # Number of BTB hits +system.cpu0.branchPred.lookups 127854962 # Number of BP lookups +system.cpu0.branchPred.condPredicted 91169153 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5795491 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 97464931 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 70565780 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.669119 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15456951 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1030979 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.401200 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 14662444 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 979053 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1073,25 +387,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 84560824 # DTB read hits -system.cpu0.dtb.read_misses 213472 # DTB read misses -system.cpu0.dtb.write_hits 73762718 # DTB write hits -system.cpu0.dtb.write_misses 44801 # DTB write misses +system.cpu0.dtb.read_hits 80634882 # DTB read hits +system.cpu0.dtb.read_misses 217470 # DTB read misses +system.cpu0.dtb.write_hits 71942682 # DTB write hits +system.cpu0.dtb.write_misses 47848 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35801 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1794 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7921 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 34852 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1874 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8493 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10648 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 84774296 # DTB read accesses -system.cpu0.dtb.write_accesses 73807519 # DTB write accesses +system.cpu0.dtb.perms_faults 11561 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 80852352 # DTB read accesses +system.cpu0.dtb.write_accesses 71990530 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 158323542 # DTB hits -system.cpu0.dtb.misses 258273 # DTB misses -system.cpu0.dtb.accesses 158581815 # DTB accesses +system.cpu0.dtb.hits 152577564 # DTB hits +system.cpu0.dtb.misses 265318 # DTB misses +system.cpu0.dtb.accesses 152842882 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1113,93 +427,294 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 233888906 # ITB inst hits -system.cpu0.itb.inst_misses 61464 # ITB inst misses +system.cpu0.itb.inst_hits 228743332 # ITB inst hits +system.cpu0.itb.inst_misses 63317 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25786 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24510 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 208811 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 202277 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 233950370 # ITB inst accesses -system.cpu0.itb.hits 233888906 # DTB hits -system.cpu0.itb.misses 61464 # DTB misses -system.cpu0.itb.accesses 233950370 # DTB accesses -system.cpu0.numCycles 883850249 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 228806649 # ITB inst accesses +system.cpu0.itb.hits 228743332 # DTB hits +system.cpu0.itb.misses 63317 # DTB misses +system.cpu0.itb.accesses 228806649 # DTB accesses +system.cpu0.numCycles 867293351 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 434327088 # Number of instructions committed -system.cpu0.committedOps 509859279 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 43671037 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93815840018 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.034988 # CPI: cycles per instruction -system.cpu0.ipc 0.491403 # IPC: instructions per cycle +system.cpu0.committedInsts 417325536 # Number of instructions committed +system.cpu0.committedOps 490736323 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 44793539 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4342 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93832115526 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.078218 # CPI: cycles per instruction +system.cpu0.ipc 0.481182 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5406 # number of quiesce instructions executed -system.cpu0.tickCycles 675499590 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 208350659 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 9024677 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.937426 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 224649292 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9025189 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.891367 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 16724996500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937426 # Average occupied blocks per requestor +system.cpu0.kern.inst.quiesce 4790 # number of quiesce instructions executed +system.cpu0.tickCycles 682045150 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 185248201 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5375859 # number of replacements +system.cpu0.dcache.tags.tagsinuse 504.387778 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 144555742 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5376371 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.887233 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 504.387778 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.985132 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.985132 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 308078040 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 308078040 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 74032777 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 74032777 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 66638302 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 66638302 # number of WriteReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 115191 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 115191 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1688442 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1688442 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1614699 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1614699 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 140671079 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 140671079 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 140671079 # number of overall hits +system.cpu0.dcache.overall_hits::total 140671079 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 3863790 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3863790 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 2319255 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2319255 # number of WriteReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst 742685 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 742685 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 105957 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 105957 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 178436 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 178436 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 6183045 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6183045 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 6183045 # number of overall misses +system.cpu0.dcache.overall_misses::total 6183045 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54382834533 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 54382834533 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36195221997 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36195221997 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 21037893950 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 21037893950 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1466052740 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 1466052740 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3737583856 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3737583856 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 3062000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3062000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 90578056530 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 90578056530 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 90578056530 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 90578056530 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 77896567 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 77896567 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 68957557 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 68957557 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 857876 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 857876 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1794399 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1794399 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1793135 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1793135 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 146854124 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 146854124 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 146854124 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 146854124 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.049602 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.049602 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.033633 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033633 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.865725 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.865725 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.059049 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059049 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.099511 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099511 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.042103 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.042103 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.042103 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.042103 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14074.997485 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14074.997485 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15606.400330 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15606.400330 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 28326.806048 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 28326.806048 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13836.299065 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13836.299065 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20946.355309 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20946.355309 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14649.425409 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14649.425409 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14649.425409 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14649.425409 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 3741617 # number of writebacks +system.cpu0.dcache.writebacks::total 3741617 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 374932 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 374932 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 967778 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 967778 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst 26 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 26 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 53 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 53 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 76 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 76 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1342710 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1342710 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1342710 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1342710 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3488858 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3488858 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1351477 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1351477 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst 742659 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 742659 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 105904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 105904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 178360 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 178360 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4840335 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4840335 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4840335 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4840335 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 42020078260 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42020078260 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 19120911908 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19120911908 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 19537847050 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 61140990168 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 61140990168 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2949307890 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2949307890 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 3070097397 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3070097397 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 6019405287 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6019405287 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.044788 # 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mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032960 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.032960 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032960 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12044.078108 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.078108 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14148.159316 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14148.159316 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 26307.965096 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26307.965096 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11827.827447 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11827.827447 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18893.067908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18893.067908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 8781546 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.937582 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 219752565 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 8782058 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 25.022901 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 16633914000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937582 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999878 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999878 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 476374153 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 476374153 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 224649292 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 224649292 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 224649292 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 224649292 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 224649292 # number of overall hits -system.cpu0.icache.overall_hits::total 224649292 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9025190 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9025190 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9025190 # 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number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 233674482 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 233674482 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 233674482 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 233674482 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038623 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.038623 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038623 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.038623 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038623 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.038623 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8457.370251 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8457.370251 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8457.370251 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8457.370251 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 465851331 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 465851331 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 219752565 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 219752565 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 219752565 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 219752565 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 219752565 # 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miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038428 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.038428 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8560.851474 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8560.851474 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8560.851474 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8560.851474 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1208,384 +723,353 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 62781832574 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62781832574 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 62781832574 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713380500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713380500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6956.289294 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8782067 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 61997855741 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713229500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713229500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038428 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.038428 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.038428 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7059.597216 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 16744363 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13538941 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 16377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 2993146 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 4286145 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 878594 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 389729 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 340122 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 446153 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1234377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1099479 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18154960 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15139641 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 334891 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1016427 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34645919 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 580958656 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 555417413 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1211560 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3676024 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1141263653 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 9180766 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 27586114 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.321691 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.467125 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 18711910 67.83% 67.83% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 8874204 32.17% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 27586114 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 13279117937 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 196246989 # Layer occupancy (ticks) -system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 13633302169 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7744080967 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 184135419 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 557460915 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 80006652 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1538976 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75387543 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49644 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 84003023 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4398912 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 74572645 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1090360 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2517 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3027964 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6795468 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 154166 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3786940 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6742713 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 3295318 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16239.521092 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15183735 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3311433 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.585246 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 14515776000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5108.942549 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.019654 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 70.169979 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2735.324727 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8261.064181 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.311825 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003907 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004283 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.166951 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.504215 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.991182 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 10731 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5301 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 4037603 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16229.874548 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15269588 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 4053811 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.766724 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 14918796500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 3465.639505 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 40.958286 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.625357 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2577.016988 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 10118.634411 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.211526 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002500 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001686 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.157289 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.617592 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.990593 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 10250 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5866 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 116 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 730 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2564 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4307 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 3014 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 30 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 447 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1426 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2059 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.654968 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.323547 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 302494843 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 302494843 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 445653 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140462 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 11717958 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 12304073 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 2993146 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 2993146 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 70651 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 70651 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 35155 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 35155 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 863705 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 863705 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 445653 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140462 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 12581663 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 13167778 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 445653 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140462 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 12581663 # number of overall hits -system.cpu0.l2cache.overall_hits::total 13167778 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13850 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10983 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 913042 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 937875 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 117562 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 117562 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 153389 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 153389 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 228005 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 228005 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13850 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10983 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 1141047 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1165880 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13850 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10983 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 1141047 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1165880 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 571410377 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 698481694 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 26359609041 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 27629501112 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 2365914343 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2365914343 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 3101977603 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3101977603 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 2176500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2176500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 9967705721 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 9967705721 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 571410377 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 698481694 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 36327314762 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 37597206833 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 571410377 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 698481694 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 36327314762 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 37597206833 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 459503 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 151445 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 12631000 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 13241948 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 2993146 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 2993146 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 188213 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 188213 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 188544 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 188544 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 1091710 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1091710 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 459503 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 151445 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 13722710 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 14333658 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 459503 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 151445 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 13722710 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 14333658 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.030141 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.072521 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.072286 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.070826 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.624622 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.624622 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.813545 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813545 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 1048 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 4016 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3415 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1655 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 22 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 525 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2441 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1975 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 887 # 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average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 24744.850767 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39995.599759 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1593,202 +1077,68 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 5337320 # number of replacements -system.cpu0.dcache.tags.tagsinuse 473.198574 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 150291577 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5337832 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.155921 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 473.198574 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.924216 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.924216 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 319289852 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 319289852 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 77767484 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77767484 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 68524145 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 68524145 # number of WriteReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 878594 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 878594 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1744720 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1744720 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1671495 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1671495 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 146291629 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 146291629 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 146291629 # number of overall hits -system.cpu0.dcache.overall_hits::total 146291629 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 3855307 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3855307 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 2180509 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2180509 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 116717 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 116717 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 188600 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 188600 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 6035816 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6035816 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 6035816 # number of overall misses -system.cpu0.dcache.overall_misses::total 6035816 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 52949262121 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 52949262121 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36682258766 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36682258766 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1582680255 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 1582680255 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3978646923 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3978646923 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 2553000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2553000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 89631520887 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 89631520887 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 89631520887 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 89631520887 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 81622791 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 81622791 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 70704654 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 70704654 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 878594 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 878594 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1861437 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1861437 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1860095 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1860095 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 152327445 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 152327445 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 152327445 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 152327445 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.047233 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.047233 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030840 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030840 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.062703 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062703 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.101393 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101393 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.039624 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.039624 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.039624 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.039624 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 13734.123410 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13734.123410 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 16822.796313 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 16822.796313 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13559.980594 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13559.980594 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21095.688881 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21095.688881 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14849.942557 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14849.942557 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 878594 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 2993146 # number of writebacks -system.cpu0.dcache.writebacks::total 2993146 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 365860 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 365860 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 900170 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 900170 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 65 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 53 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1266030 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1266030 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1266030 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1266030 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3489447 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3489447 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1279618 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1279618 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 116652 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116652 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 188547 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 188547 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4769065 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4769065 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4769065 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4769065 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 40912958493 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40912958493 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 19695838269 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19695838269 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 39725259601 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 39725259601 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1347811737 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1347811737 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3591126546 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3591126546 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2234500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2234500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 60608796762 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 60608796762 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 60608796762 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 60608796762 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2590105703 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2590105703 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2521930197 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2521930197 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 5112035900 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5112035900 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.042751 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.042751 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018098 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018098 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.062668 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062668 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.101364 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101364 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.031308 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031308 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11724.768564 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11724.768564 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 15391.967188 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15391.967188 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11554.124550 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11554.124550 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19046.320260 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19046.320260 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 124419206 # Number of BP lookups -system.cpu1.branchPred.condPredicted 87805046 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6051921 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 92935126 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 66733716 # Number of BTB hits +system.cpu0.toL2Bus.trans_dist::ReadReq 17406363 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 13329872 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19688 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19687 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3741617 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 5530609 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 862152 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 741495 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 486160 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 325301 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 465486 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1278141 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1152631 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17668715 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15752783 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 346532 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1063511 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 34831541 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 565398848 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598192623 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1259640 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3873096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1168724207 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 10729638 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 29561564 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.351841 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.477545 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 19160579 64.82% 64.82% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 10400985 35.18% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 29561564 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14119794312 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 225496496 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 13269247990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 7748577182 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 189385144 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 579874631 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.branchPred.lookups 146637664 # Number of BP lookups +system.cpu1.branchPred.condPredicted 104244557 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6464776 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 109760718 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 80092874 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.806774 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14888837 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1052333 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.970436 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17287162 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1125459 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1812,25 +1162,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 80858392 # DTB read hits -system.cpu1.dtb.read_misses 227532 # DTB read misses -system.cpu1.dtb.write_hits 71539111 # DTB write hits -system.cpu1.dtb.write_misses 46368 # DTB write misses +system.cpu1.dtb.read_hits 95196820 # DTB read hits +system.cpu1.dtb.read_misses 258683 # DTB read misses +system.cpu1.dtb.write_hits 82774540 # DTB write hits +system.cpu1.dtb.write_misses 48918 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35324 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1220 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8196 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 40938 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1166 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8454 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10514 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 81085924 # DTB read accesses -system.cpu1.dtb.write_accesses 71585479 # DTB write accesses +system.cpu1.dtb.perms_faults 11190 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 95455503 # DTB read accesses +system.cpu1.dtb.write_accesses 82823458 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 152397503 # DTB hits -system.cpu1.dtb.misses 273900 # DTB misses -system.cpu1.dtb.accesses 152671403 # DTB accesses +system.cpu1.dtb.hits 177971360 # DTB hits +system.cpu1.dtb.misses 307601 # DTB misses +system.cpu1.dtb.accesses 178278961 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1852,92 +1202,294 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 221287255 # ITB inst hits -system.cpu1.itb.inst_misses 68040 # ITB inst misses +system.cpu1.itb.inst_hits 262373201 # ITB inst hits +system.cpu1.itb.inst_misses 66107 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25097 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29545 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 202601 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 222220 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 221355295 # ITB inst accesses -system.cpu1.itb.hits 221287255 # DTB hits -system.cpu1.itb.misses 68040 # DTB misses -system.cpu1.itb.accesses 221355295 # DTB accesses -system.cpu1.numCycles 841372178 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 262439308 # ITB inst accesses +system.cpu1.itb.hits 262373201 # DTB hits +system.cpu1.itb.misses 66107 # DTB misses +system.cpu1.itb.accesses 262439308 # DTB accesses +system.cpu1.numCycles 965776076 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 411163350 # Number of instructions committed -system.cpu1.committedOps 484726757 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 42974941 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4643 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93858235376 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.046321 # CPI: cycles per instruction -system.cpu1.ipc 0.488682 # IPC: instructions per cycle +system.cpu1.committedInsts 483897990 # Number of instructions committed +system.cpu1.committedOps 569285719 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 49152054 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5850 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93733878410 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 1.995826 # CPI: cycles per instruction +system.cpu1.ipc 0.501046 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13250 # number of quiesce instructions executed -system.cpu1.tickCycles 646022417 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 195349761 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 9199343 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.111645 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 211878543 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9199855 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 23.030639 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8364993861000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.111645 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990452 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990452 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 14403 # number of quiesce instructions executed +system.cpu1.tickCycles 777604637 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 188171439 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5691678 # number of replacements +system.cpu1.dcache.tags.tagsinuse 432.252247 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 169393329 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5692190 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.758903 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8364525946500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 432.252247 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.844243 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.844243 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 358720623 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 358720623 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.inst 87552380 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 87552380 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.inst 77214593 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 77214593 # number of WriteReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 211985 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 211985 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1994962 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1994962 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1944639 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1944639 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.inst 164766973 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 164766973 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 164766973 # number of overall hits +system.cpu1.dcache.overall_hits::total 164766973 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 4362572 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 4362572 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 2362737 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2362737 # number of WriteReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 497251 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 497251 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 139927 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 139927 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 188742 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 188742 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.inst 6725309 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 6725309 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.inst 6725309 # number of overall misses +system.cpu1.dcache.overall_misses::total 6725309 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 63153941750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 63153941750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 37295206516 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 37295206516 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst 9223332559 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 9223332559 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1921743254 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 1921743254 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3886161820 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3886161820 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 3267000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3267000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 100449148266 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 100449148266 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.inst 100449148266 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 100449148266 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.inst 91914952 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 91914952 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.inst 79577330 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 79577330 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 709236 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 709236 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 2134889 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2134889 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 2133381 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2133381 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 171492282 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 171492282 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 171492282 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 171492282 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.047463 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.047463 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.029691 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029691 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst 0.701108 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.701108 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.065543 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.065543 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.088471 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088471 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.039216 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.039216 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.039216 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039216 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14476.309331 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14476.309331 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 15784.747315 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 15784.747315 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 18548.645571 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 18548.645571 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13733.898776 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13733.898776 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20589.809475 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20589.809475 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14935.990044 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14935.990044 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14935.990044 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14935.990044 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # 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number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 49100377691 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 49100377691 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 20233474919 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20233474919 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 8220345441 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 8220345441 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1640188222 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1640188222 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3498307132 # 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number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3123925989 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3123925989 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 6535099721 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6535099721 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.043110 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043110 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.017631 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017631 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.701042 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.701042 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.065512 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065512 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.088436 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088436 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031287 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031287 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12391.309416 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12391.309416 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14421.445075 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14421.445075 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 16533.144225 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 16533.144225 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11727.357515 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11727.357515 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18542.231190 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18542.231190 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # 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average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 10003641 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.113561 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 252141010 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 10004153 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.203634 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8364450905000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.113561 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990456 # 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average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8498.421941 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8498.421941 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8498.421941 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1946,380 +1498,353 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9199864 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9199864 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9199864 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9199864 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 9199864 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 9199864 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63970402202 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 63970402202 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63970402202 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 63970402202 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63970402202 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 63970402202 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8551999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8551999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8551999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8551999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.041614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.041614 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.041614 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6953.407377 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 10004155 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 10004155 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 10004155 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 10004155 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 10004155 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 10004155 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 70001431618 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 70001431618 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 70001431618 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 70001431618 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 70001431618 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 70001431618 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8751000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8751000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8751000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8751000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038163 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.038163 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.038163 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6997.235810 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 16974832 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13523495 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 21560 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 21560 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 2756922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 3912463 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 680221 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 382477 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337171 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 432582 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1151878 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1012928 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18399906 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13962178 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 374507 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1077414 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 33814005 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 588796992 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 509690879 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1369000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3931224 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1103788095 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 9217690 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 27159033 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.328913 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.469818 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 18226076 67.11% 67.11% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 8932957 32.89% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 27159033 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 12584209028 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175099992 # Layer occupancy (ticks) -system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13805070808 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7247611234 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 204139691 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 586587181 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 79358164 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1355061 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75203006 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49096 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 91266400 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2590593 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 83739964 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1124296 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 3073 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2747928 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6733876 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 159143 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 3652396 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 7945944 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 3063828 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13784.638052 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 15005563 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 3079680 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.872442 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9994842368500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 2928.842366 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.432287 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 61.914602 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.974382 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7961.474415 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.178762 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004116 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003779 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168761 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485930 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.841348 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9851 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 102 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5899 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 232 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4639 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 3547 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1433 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 75 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2951 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2204 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 483 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.601257 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006226 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.360046 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 294450591 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 294450591 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 477253 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159835 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 11727223 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 12364311 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 2756922 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 2756922 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 68490 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 68490 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 32200 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 32200 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 776956 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 776956 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 477253 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 159835 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 12504179 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 13141267 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 477253 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 159835 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 12504179 # number of overall hits -system.cpu1.l2cache.overall_hits::total 13141267 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 14150 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11290 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 893170 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 918610 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 118620 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 118620 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 151637 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 151637 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 230937 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 230937 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 14150 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11290 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 1124107 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1149547 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 14150 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11290 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 1124107 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1149547 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 593312131 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 709102173 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 26528840524 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 27831254828 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2374329628 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2374329628 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 3078262421 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3078262421 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 2493000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2493000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9672285471 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 9672285471 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 593312131 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 709102173 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 36201125995 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 37503540299 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 593312131 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 709102173 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 36201125995 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 37503540299 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 491403 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 171125 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 12620393 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 13282921 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 2756922 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 2756922 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 187110 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 187110 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 183837 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 183837 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # 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number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065975 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.070772 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.069157 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.633959 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.633959 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.824845 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.824845 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.replacements 3964575 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13771.716542 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 17209014 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 3980703 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.323109 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9604482251250 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4186.861890 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.243250 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.010570 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2902.209445 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6553.391387 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.255546 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004043 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003846 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.177137 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.399987 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.840559 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9777 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6309 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 89 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 734 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4083 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 3317 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1554 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 691 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1911 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 531 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.596741 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.385071 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 336896441 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 336896441 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 545727 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151675 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 13043643 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 13741045 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3739269 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3739269 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst 314994 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 314994 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 88927 # 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number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 414121710 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 33089400106 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 34029256940 # number of ReadReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst 5173608568 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 5173608568 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2603383383 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2603383383 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 2990869344 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2990869344 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 2444000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2444000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9524400999 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 9524400999 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 525735124 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 414121710 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 42613801105 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 43553657939 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 525735124 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 414121710 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 42613801105 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 43553657939 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 560431 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 161995 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 14106151 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 14828577 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3739269 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3739269 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst 495851 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 495851 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 221605 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 221605 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 188661 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 188661 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1183115 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1183115 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 560431 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 161995 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 15289266 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 16011692 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 560431 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 161995 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 15289266 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 16011692 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063706 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.075322 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.073340 # miss rate for ReadReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst 0.364741 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.364741 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.598714 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.598714 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.779186 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.779186 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.229128 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.229128 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065975 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.082483 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.080440 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065975 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.082483 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.080440 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62807.986980 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29701.893843 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30297.138969 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 20016.267307 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20016.267307 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20300.206552 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20300.206552 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 498600 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 498600 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41882.788254 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41882.788254 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62807.986980 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32204.341753 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 32624.625439 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62807.986980 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32204.341753 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 32624.625439 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 62499 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.201781 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.201781 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.063706 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.085108 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.082831 # 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mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.078920 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.267419 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23593.848957 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24209.025291 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25406.756702 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25406.756702 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16790.097429 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16790.097429 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13706.327130 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13706.327130 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 409000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 409000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 33608.899504 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33608.899504 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25748.347788 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26183.273757 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25748.347788 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25406.756702 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25624.933726 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.305025 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25061.739913 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25197.269516 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30135.091093 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 17739.767756 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 17739.767756 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16370.695888 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16370.695888 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13815.637468 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13815.637468 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 337333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30032.586754 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30032.586754 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26092.290194 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29115.574710 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2327,327 +1852,904 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 4834403 # number of replacements -system.cpu1.dcache.tags.tagsinuse 460.748614 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 144950857 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4834915 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.980022 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8365240216000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 460.748614 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.899900 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.899900 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 306842506 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 306842506 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 74397461 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 74397461 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 66754653 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 66754653 # number of WriteReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 680221 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 680221 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1623333 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1623333 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1553141 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1553141 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 141152114 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 141152114 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 141152114 # number of overall hits -system.cpu1.dcache.overall_hits::total 141152114 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 3628151 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3628151 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 2024929 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2024929 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 114968 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 114968 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 183901 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 183901 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 5653080 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5653080 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 5653080 # number of overall misses -system.cpu1.dcache.overall_misses::total 5653080 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 51111445827 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 51111445827 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 34750982270 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 34750982270 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1576484749 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 1576484749 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3893749340 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3893749340 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 2823500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2823500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 85862428097 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 85862428097 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 85862428097 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 85862428097 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 78025612 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 78025612 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 68779582 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 68779582 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 680221 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 680221 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 1738301 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1738301 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 1737042 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1737042 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 146805194 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 146805194 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 146805194 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 146805194 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046499 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.046499 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.029441 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029441 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.066138 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066138 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.105870 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105870 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.038507 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038507 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.038507 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.038507 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14087.463787 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14087.463787 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 17161.580613 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17161.580613 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13712.378653 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13712.378653 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 21173.073230 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21173.073230 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 15188.610120 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15188.610120 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 15188.610120 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15188.610120 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 680221 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 2756922 # number of writebacks -system.cpu1.dcache.writebacks::total 2756922 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 322268 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 322268 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 829273 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 829273 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 78 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 78 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 59 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 1151541 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1151541 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 1151541 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1151541 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3305883 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3305883 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1194736 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1194736 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 114890 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 114890 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 183842 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 183842 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 4500619 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4500619 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 4500619 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4500619 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 39848912237 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39848912237 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 18776610903 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18776610903 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 30844406102 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 30844406102 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1344930230 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1344930230 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3516398127 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3516398127 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 2557000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2557000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 58625523140 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 58625523140 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 58625523140 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 58625523140 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3752867967 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3752867967 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3654726713 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3654726713 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 7407594680 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7407594680 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042369 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042369 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.017371 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017371 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.066093 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066093 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.105836 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105836 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030657 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030657 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030657 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030657 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12053.939065 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12053.939065 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 15716.117120 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15716.117120 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11706.242754 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11706.242754 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 19127.283901 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19127.283901 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 13026.102218 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13026.102218 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 13026.102218 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13026.102218 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 115612 # number of replacements -system.iocache.tags.tagsinuse 11.299913 # Cycle average of tags in use +system.cpu1.toL2Bus.trans_dist::ReadReq 19283354 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 15081139 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 18583 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 18583 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3739269 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 5170827 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 625737 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495851 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 477449 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330499 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 473092 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1314338 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1188302 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 20008489 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16359278 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 359533 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1226091 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 37953391 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640271616 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 615594373 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1295960 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4483448 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1261645397 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 10423087 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 30921485 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.327379 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.469257 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 20798445 67.26% 67.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 10123040 32.74% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 30921485 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 14664539498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176010242 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 15012316370 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 8461463125 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 197959664 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 666269864 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40348 # Transaction distribution +system.iobus.trans_dist::ReadResp 40348 # Transaction distribution +system.iobus.trans_dist::WriteReq 136740 # Transaction distribution +system.iobus.trans_dist::WriteResp 30012 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122926 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7496838 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36517000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 1042881499 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 92917000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179159841 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115566 # number of replacements +system.iocache.tags.tagsinuse 11.298842 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115582 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9121131291000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.419527 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.880386 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463720 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.242524 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706245 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9120788284000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.841658 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.457184 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240104 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466074 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706178 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042406 # Number of tag accesses -system.iocache.tags.data_accesses 1042406 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1040622 # Number of tag accesses +system.iocache.tags.data_accesses 1040622 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8894 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 187 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 187 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8889 # number of demand (read+write) misses -system.iocache.demand_misses::total 8929 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8857 # number of demand (read+write) misses +system.iocache.demand_misses::total 8897 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8889 # number of overall misses -system.iocache.overall_misses::total 8929 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5701000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1965059357 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1970760357 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8857 # number of overall misses +system.iocache.overall_misses::total 8897 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1971462847 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1977169847 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6058000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1965059357 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1971117357 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6058000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1965059357 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1971117357 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28907198811 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28907198811 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1971462847 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1977526847 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1971462847 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1977526847 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8894 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106915 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106915 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8889 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8929 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8857 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8897 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8889 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8929 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8857 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8897 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001749 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.001749 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 221066.414332 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 220788.747143 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 222588.105115 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 222303.783112 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151450 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 221066.414332 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220754.547766 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151450 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 221066.414332 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220754.547766 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 54362 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270849.250534 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270849.250534 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 222268.949871 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 222268.949871 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 228015 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27566 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.902004 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.271603 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106728 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8857 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8889 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8929 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8857 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8897 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8889 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8929 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3777000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1502702365 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1506479365 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8857 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8897 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1510755865 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1514538865 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6627847227 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6627847227 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3978000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1502702365 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1506680365 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3978000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1502702365 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1506680365 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23356679475 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23356679475 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1510755865 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1514739865 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1510755865 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1514739865 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 169051.902914 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 168774.295877 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170571.961725 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 170287.706881 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218843.035333 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218843.035333 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 1797599 # number of replacements +system.l2c.tags.tagsinuse 64905.725288 # Cycle average of tags in use +system.l2c.tags.total_refs 8591301 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1860596 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.617499 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6896032000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 7600.616161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.639535 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 9.409863 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1890.006249 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16961.129535 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 324.497512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 441.216776 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 10554.786238 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 27107.423418 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.115976 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000254 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.028839 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.258806 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004951 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006732 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.161053 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.413626 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990383 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 43530 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 179 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 19288 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 252 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1656 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6242 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 35370 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1730 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 16555 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.664215 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.002731 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.294312 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 89688959 # Number of tag accesses +system.l2c.tags.data_accesses 89688959 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8987 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6604 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 578381 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 2301852 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 8168 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5333 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 630016 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 2353942 # number of ReadReq hits +system.l2c.ReadReq_hits::total 5893283 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2942617 # number of Writeback hits +system.l2c.Writeback_hits::total 2942617 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.inst 6235 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.inst 6750 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 12985 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.inst 39044 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 35229 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 74273 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 7514 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 7779 # 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number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 53447323 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 50683879 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 104131202 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.inst 3468272337 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.inst 3934530582 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7402802919 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 165226748 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 144557248 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 11443079250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 222345248 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 209364000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 14578667281 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 227453390829 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 165226748 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 144557248 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 11443079250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 222345248 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 209364000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 14578667281 # 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number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2942617 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2942617 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.inst 23153 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.inst 13924 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 37077 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.inst 75486 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.inst 68480 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 143966 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.inst 17008 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.inst 16789 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 33797 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.inst 109471 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.inst 107228 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 216699 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 10965 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 8297 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 783366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 3165373 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10853 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7845 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 868570 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2920422 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 7775691 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 10965 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 8297 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 783366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 3165373 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10853 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7845 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 868570 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2920422 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 7775691 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.180392 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.204050 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.141734 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.272802 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.320204 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.172493 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.193972 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.220361 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.inst 0.730704 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.inst 0.515226 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.649783 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 205814996987 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5245081248 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2881233750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8126314998 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 2584862001 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 2667893000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5252755001 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7829943249 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5549126750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13379069999 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.141662 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172423 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.220284 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.730704 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.515226 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.649783 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.482765 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.485558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.484093 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.558208 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.536661 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.547504 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.414174 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.485330 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.449384 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.179744 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.211053 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.226669 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.179744 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.211053 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.226669 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70987.456062 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68543.294912 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 119894.183825 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22805.866355 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 21921.053805 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22542.391126 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10198.876736 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10176.275781 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10188.093668 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10317.976090 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10215.249057 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10267.956064 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 63897.708006 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63002.486155 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63419.295992 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68704.517411 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66970.315060 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 116773.870084 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68704.517411 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66970.315060 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 116773.870084 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 1764688 # Transaction distribution +system.membus.trans_dist::ReadResp 1764688 # Transaction distribution +system.membus.trans_dist::WriteReq 38271 # Transaction distribution +system.membus.trans_dist::WriteResp 38271 # Transaction distribution +system.membus.trans_dist::Writeback 1325983 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 130519 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 130519 # Transaction distribution +system.membus.trans_dist::UpgradeReq 461811 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 273493 # Transaction distribution +system.membus.trans_dist::UpgradeResp 92294 # Transaction distribution +system.membus.trans_dist::ReadExReq 109929 # Transaction distribution +system.membus.trans_dist::ReadExResp 93588 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5737506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5885368 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336109 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336109 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6221477 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 195441096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 195648244 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14110976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 209759220 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 661928 # Total snoops (count) +system.membus.snoop_fanout::samples 3975767 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 3975767 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 3975767 # Request fanout histogram +system.membus.reqLayer0.occupancy 109763969 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 20835993 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 15443357238 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 16944581187 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 187180159 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 8566773 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 8559524 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38271 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38271 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2942617 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 143810 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 37077 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 531990 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 288786 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 820776 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 117 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 266520 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 266520 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10703555 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10080815 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 20784370 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 361515951 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 330513413 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 692029364 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1718447 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 12650717 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.009140 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.095166 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 12535087 99.09% 99.09% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115630 0.91% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 12650717 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 18290340474 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 7404000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 20424320611 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 19750107809 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 19a412b67..0607c3606 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,138 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.727209 # Number of seconds simulated -sim_ticks 51727209160500 # Number of ticks simulated -final_tick 51727209160500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.688410 # Number of seconds simulated +sim_ticks 51688410348500 # Number of ticks simulated +final_tick 51688410348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180889 # Simulator instruction rate (inst/s) -host_op_rate 212546 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9849373518 # Simulator tick rate (ticks/s) -host_mem_usage 656984 # Number of bytes of host memory used -host_seconds 5251.83 # Real time elapsed on the host -sim_insts 949996153 # Number of instructions simulated -sim_ops 1116252474 # Number of ops (including micro ops) simulated +host_inst_rate 152333 # Simulator instruction rate (inst/s) +host_op_rate 179011 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8275752383 # Simulator tick rate (ticks/s) +host_mem_usage 662164 # Number of bytes of host memory used +host_seconds 6245.77 # Real time elapsed on the host +sim_insts 951433762 # Number of instructions simulated +sim_ops 1118058358 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 424768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 725248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 1005696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 91312008 # Number of bytes read from this memory -system.physmem.bytes_read::total 93467720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 9575168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 9575168 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 57345920 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.inst 101255460 # Number of bytes written to this memory -system.physmem.bytes_written::total 165427876 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 6637 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 11332 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 15714 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 1426763 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1460446 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 896030 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.inst 1584368 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2587062 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 8212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 14021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 19442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 1765261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1806935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 185109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 185109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1108622 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 131971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 1957489 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3198082 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1108622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 140183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 14021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 19442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3722750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5005018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1460446 # Number of read requests accepted -system.physmem.writeReqs 2587062 # Number of write requests accepted -system.physmem.readBursts 1460446 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2587062 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 93277376 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 191168 # Total number of bytes read from write queue -system.physmem.bytesWritten 160708736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 93467720 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 165427876 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2987 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 75973 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 39020 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 90929 # Per bank write bursts -system.physmem.perBankRdBursts::1 88965 # Per bank write bursts -system.physmem.perBankRdBursts::2 84770 # Per bank write bursts -system.physmem.perBankRdBursts::3 81753 # Per bank write bursts -system.physmem.perBankRdBursts::4 95872 # Per bank write bursts -system.physmem.perBankRdBursts::5 100020 # Per bank write bursts -system.physmem.perBankRdBursts::6 87194 # Per bank write bursts -system.physmem.perBankRdBursts::7 85191 # Per bank write bursts -system.physmem.perBankRdBursts::8 88300 # Per bank write bursts -system.physmem.perBankRdBursts::9 142631 # Per bank write bursts -system.physmem.perBankRdBursts::10 90249 # Per bank write bursts -system.physmem.perBankRdBursts::11 90988 # Per bank write bursts -system.physmem.perBankRdBursts::12 86795 # Per bank write bursts -system.physmem.perBankRdBursts::13 81108 # Per bank write bursts -system.physmem.perBankRdBursts::14 81197 # Per bank write bursts -system.physmem.perBankRdBursts::15 81497 # Per bank write bursts -system.physmem.perBankWrBursts::0 153488 # Per bank write bursts -system.physmem.perBankWrBursts::1 130402 # Per bank write bursts -system.physmem.perBankWrBursts::2 156905 # Per bank write bursts -system.physmem.perBankWrBursts::3 130743 # Per bank write bursts -system.physmem.perBankWrBursts::4 190154 # Per bank write bursts -system.physmem.perBankWrBursts::5 164896 # Per bank write bursts -system.physmem.perBankWrBursts::6 144797 # Per bank write bursts -system.physmem.perBankWrBursts::7 175639 # Per bank write bursts -system.physmem.perBankWrBursts::8 162274 # Per bank write bursts -system.physmem.perBankWrBursts::9 194391 # Per bank write bursts -system.physmem.perBankWrBursts::10 215398 # Per bank write bursts -system.physmem.perBankWrBursts::11 156932 # Per bank write bursts -system.physmem.perBankWrBursts::12 147011 # Per bank write bursts -system.physmem.perBankWrBursts::13 124629 # Per bank write bursts -system.physmem.perBankWrBursts::14 132966 # Per bank write bursts -system.physmem.perBankWrBursts::15 130449 # Per bank write bursts +system.physmem.bytes_read::cpu.dtb.walker 411264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 350272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 77213320 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 415808 # Number of bytes read from this memory +system.physmem.bytes_read::total 78390664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10284736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10284736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 94966144 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.inst 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 94986724 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6426 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5473 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1206471 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6497 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1224867 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1483846 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.inst 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1486419 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1493823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1516600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1837281 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.inst 398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1837679 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1837281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1494221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3354280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1224867 # Number of read requests accepted +system.physmem.writeReqs 2137165 # Number of write requests accepted +system.physmem.readBursts 1224867 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2137165 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 78347456 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 44032 # Total number of bytes read from write queue +system.physmem.bytesWritten 136289472 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 78390664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 136634468 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 688 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7616 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 39979 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 71039 # Per bank write bursts +system.physmem.perBankRdBursts::1 73325 # Per bank write bursts +system.physmem.perBankRdBursts::2 71985 # Per bank write bursts +system.physmem.perBankRdBursts::3 70214 # Per bank write bursts +system.physmem.perBankRdBursts::4 72864 # Per bank write bursts +system.physmem.perBankRdBursts::5 82821 # Per bank write bursts +system.physmem.perBankRdBursts::6 75004 # Per bank write bursts +system.physmem.perBankRdBursts::7 73137 # Per bank write bursts +system.physmem.perBankRdBursts::8 67826 # Per bank write bursts +system.physmem.perBankRdBursts::9 129786 # Per bank write bursts +system.physmem.perBankRdBursts::10 72316 # Per bank write bursts +system.physmem.perBankRdBursts::11 77203 # Per bank write bursts +system.physmem.perBankRdBursts::12 71594 # Per bank write bursts +system.physmem.perBankRdBursts::13 74115 # Per bank write bursts +system.physmem.perBankRdBursts::14 68849 # Per bank write bursts +system.physmem.perBankRdBursts::15 72101 # Per bank write bursts +system.physmem.perBankWrBursts::0 128045 # Per bank write bursts +system.physmem.perBankWrBursts::1 133141 # Per bank write bursts +system.physmem.perBankWrBursts::2 133329 # Per bank write bursts +system.physmem.perBankWrBursts::3 132983 # Per bank write bursts +system.physmem.perBankWrBursts::4 135529 # Per bank write bursts +system.physmem.perBankWrBursts::5 141007 # Per bank write bursts +system.physmem.perBankWrBursts::6 130525 # Per bank write bursts +system.physmem.perBankWrBursts::7 133720 # Per bank write bursts +system.physmem.perBankWrBursts::8 132879 # Per bank write bursts +system.physmem.perBankWrBursts::9 138815 # Per bank write bursts +system.physmem.perBankWrBursts::10 133616 # Per bank write bursts +system.physmem.perBankWrBursts::11 135999 # Per bank write bursts +system.physmem.perBankWrBursts::12 129210 # Per bank write bursts +system.physmem.perBankWrBursts::13 131804 # Per bank write bursts +system.physmem.perBankWrBursts::14 128438 # Per bank write bursts +system.physmem.perBankWrBursts::15 130483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 51727207457500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 51688408694500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1460431 # Read request sizes (log2) +system.physmem.readPktSize::6 1224852 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2584489 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1416507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 34555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 309 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2134592 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1187733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 30120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 307 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -158,160 +155,155 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 72795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 99197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 141412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 149421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 158127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 155282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 155338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 158469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 154756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 163262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 150399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 141869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 140112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 143384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 124899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 123820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 121368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 119840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 780499 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 325.414218 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.439490 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 353.699104 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 309228 39.62% 39.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 174811 22.40% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 65731 8.42% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36715 4.70% 75.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 26784 3.43% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 18838 2.41% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14160 1.81% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 15996 2.05% 84.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 118236 15.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 780499 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 115810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.584803 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 189.442624 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 115806 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::49152-51199 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 115810 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 115810 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.682704 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.755419 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.614982 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 58231 50.28% 50.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 24453 21.11% 71.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 18350 15.84% 87.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 9042 7.81% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1932 1.67% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 855 0.74% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 730 0.63% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 458 0.40% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 355 0.31% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 216 0.19% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 209 0.18% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 191 0.16% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 504 0.44% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 74 0.06% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 53 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 51 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 44 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 5 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 14 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 5 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 8 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 115810 # Writes before turning the bus around for reads -system.physmem.totQLat 16665773749 # Total ticks spent queuing -system.physmem.totMemAccLat 43993129999 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7287295000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11434.81 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 48573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 74403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 119873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 132680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 128553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 131972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 134309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 139176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 138776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 138399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 133829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 121319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 116942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 113077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 105310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 728572 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.598947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.664587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.125501 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 296144 40.65% 40.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 177091 24.31% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 64790 8.89% 73.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35671 4.90% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 25285 3.47% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 17267 2.37% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13064 1.79% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11522 1.58% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 87738 12.04% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 728572 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97844 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.511242 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 125.941708 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 97842 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97844 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97844 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.764472 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.107027 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.533220 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 71394 72.97% 72.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 19346 19.77% 92.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 3261 3.33% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 806 0.82% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 888 0.91% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 399 0.41% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 342 0.35% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 242 0.25% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 261 0.27% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 243 0.25% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 222 0.23% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 63 0.06% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 71 0.07% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 48 0.05% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 149 0.15% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 24 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 24 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 7 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 12 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 10 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97844 # Writes before turning the bus around for reads +system.physmem.totQLat 16127261998 # Total ticks spent queuing +system.physmem.totMemAccLat 39080618248 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6120895000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13173.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30184.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.20 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31923.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing -system.physmem.readRowHits 1137142 # Number of row buffer hits during reads -system.physmem.writeRowHits 2050889 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.67 # Row buffer hit rate for writes -system.physmem.avgGap 12780013.64 # Average gap between requests -system.physmem.pageHitRate 80.33 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49431156944750 # Time in different power states -system.physmem.memoryStateTime::REF 1727285040000 # Time in different power states +system.physmem.avgWrQLen 23.82 # Average write queue length when enqueuing +system.physmem.readRowHits 946951 # Number of row buffer hits during reads +system.physmem.writeRowHits 1678178 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.35 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.80 # Row buffer hit rate for writes +system.physmem.avgGap 15374157.26 # Average gap between requests +system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49562808778250 # Time in different power states +system.physmem.memoryStateTime::REF 1725989460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 568765880250 # Time in different power states +system.physmem.memoryStateTime::ACT 399611675250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2969235360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2931337080 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1620118500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1599439875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 5574566400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 5793535800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 8080715520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 8191044000 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3378569538240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3378569538240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1383201002250 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1386870926445 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29822988580500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29819769348750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34603003756770 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34603725170190 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.951744 # Core power per rank (mW) -system.physmem.averagePower::1 668.965690 # Core power per rank (mW) +system.physmem.actEnergy::0 2776243680 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2731760640 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1514815500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1490544000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 4604987400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 4943562000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 6922447920 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 6876861120 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3376035383760 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3376035383760 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1310091236460 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1307916167760 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29863840623750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29865748578750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34565785738470 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34565742858030 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.733833 # Core power per rank (mW) +system.physmem.averagePower::1 668.733004 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory @@ -324,201 +316,22 @@ system.realview.nvmem.bw_inst_read::cpu.inst 14 system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 594629 # Transaction distribution -system.membus.trans_dist::ReadResp 594629 # Transaction distribution -system.membus.trans_dist::WriteReq 33870 # Transaction distribution -system.membus.trans_dist::WriteResp 33870 # Transaction distribution -system.membus.trans_dist::Writeback 896030 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1688459 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1688459 # Transaction distribution -system.membus.trans_dist::UpgradeReq 39025 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 39026 # Transaction distribution -system.membus.trans_dist::ReadExReq 901834 # Transaction distribution -system.membus.trans_dist::ReadExResp 901834 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7050430 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7180576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228843 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 228843 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7409419 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 251644332 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 251815240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7251264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7251264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 259066504 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2247 # Total snoops (count) -system.membus.snoop_fanout::samples 4033943 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4033943 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4033943 # Request fanout histogram -system.membus.reqLayer0.occupancy 113743500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5505500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 25619760742 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 15669502469 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186602993 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 40404 # Transaction distribution -system.iobus.trans_dist::ReadResp 40404 # Transaction distribution -system.iobus.trans_dist::WriteReq 136687 # Transaction distribution -system.iobus.trans_dist::WriteResp 136733 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 46 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354274 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492854 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 981194482 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179049007 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 259878452 # Number of BP lookups -system.cpu.branchPred.condPredicted 182434681 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12106293 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 193171007 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136122005 # Number of BTB hits +system.cpu.branchPred.lookups 261297703 # Number of BP lookups +system.cpu.branchPred.condPredicted 183348683 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12210638 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 193789546 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136743179 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.467099 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31463060 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2055318 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.562722 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31690204 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2146162 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -542,25 +355,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183357098 # DTB read hits -system.cpu.dtb.read_misses 476791 # DTB read misses -system.cpu.dtb.write_hits 162738381 # DTB write hits -system.cpu.dtb.write_misses 102414 # DTB write misses +system.cpu.dtb.read_hits 183672011 # DTB read hits +system.cpu.dtb.read_misses 484545 # DTB read misses +system.cpu.dtb.write_hits 163011983 # DTB write hits +system.cpu.dtb.write_misses 101734 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47228 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 80239 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 828 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14730 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 47427 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 80165 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 779 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14148 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23395 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183833889 # DTB read accesses -system.cpu.dtb.write_accesses 162840795 # DTB write accesses +system.cpu.dtb.perms_faults 23574 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 184156556 # DTB read accesses +system.cpu.dtb.write_accesses 163113717 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 346095479 # DTB hits -system.cpu.dtb.misses 579205 # DTB misses -system.cpu.dtb.accesses 346674684 # DTB accesses +system.cpu.dtb.hits 346683994 # DTB hits +system.cpu.dtb.misses 586279 # DTB misses +system.cpu.dtb.accesses 347270273 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -582,93 +395,285 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 453041166 # ITB inst hits -system.cpu.itb.inst_misses 137089 # ITB inst misses +system.cpu.itb.inst_hits 455292001 # ITB inst hits +system.cpu.itb.inst_misses 136900 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47228 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57684 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 47427 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 57667 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 391598 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 366615 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 453178255 # ITB inst accesses -system.cpu.itb.hits 453041166 # DTB hits -system.cpu.itb.misses 137089 # DTB misses -system.cpu.itb.accesses 453178255 # DTB accesses -system.cpu.numCycles 2529291390 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 455428901 # ITB inst accesses +system.cpu.itb.hits 455292001 # DTB hits +system.cpu.itb.misses 136900 # DTB misses +system.cpu.itb.accesses 455428901 # DTB accesses +system.cpu.numCycles 2518825477 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 949996153 # Number of instructions committed -system.cpu.committedOps 1116252474 # Number of ops (including micro ops) committed -system.cpu.discardedOps 97459423 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7746 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100926289028 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.662423 # CPI: cycles per instruction -system.cpu.ipc 0.375598 # IPC: instructions per cycle +system.cpu.committedInsts 951433762 # Number of instructions committed +system.cpu.committedOps 1118058358 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97427430 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7769 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100859175256 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.647400 # CPI: cycles per instruction +system.cpu.ipc 0.377729 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16606 # number of quiesce instructions executed -system.cpu.tickCycles 1758931949 # Number of cycles that the object actually ticked -system.cpu.idleCycles 770359441 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 24421267 # number of replacements -system.cpu.icache.tags.tagsinuse 511.933272 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 428216370 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24421779 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.534201 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20287456250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.933272 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999870 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16629 # number of quiesce instructions executed +system.cpu.tickCycles 1804872231 # Number of cycles that the object actually ticked +system.cpu.idleCycles 713953246 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 11184340 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.959663 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 330369377 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11184852 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.537215 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959663 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1387996074 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1387996074 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 169370817 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 169370817 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 152148495 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 152148495 # number of WriteReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst 336885 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 336885 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 4109295 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4109295 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 4353813 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4353813 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 321519312 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 321519312 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 321519312 # number of overall hits +system.cpu.dcache.overall_hits::total 321519312 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 8065146 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 8065146 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 4327048 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4327048 # number of WriteReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.inst 1245044 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1245044 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 246250 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 246250 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.inst 12392194 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12392194 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 12392194 # number of overall misses +system.cpu.dcache.overall_misses::total 12392194 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128575099737 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128575099737 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 143976164605 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 143976164605 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.inst 29659207447 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 29659207447 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 3578517253 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 3578517253 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 150500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 272551264342 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 272551264342 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 272551264342 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 272551264342 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 177435963 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177435963 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 156475543 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 156475543 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst 1581929 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1581929 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 4355545 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4355545 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 4353815 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4353815 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 333911506 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 333911506 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 333911506 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 333911506 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.045454 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.045454 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.027653 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027653 # miss rate for WriteReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.inst 0.787042 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787042 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.056537 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056537 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.037112 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037112 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.037112 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037112 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15942.067228 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15942.067228 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 33273.530732 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33273.530732 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.inst 23821.814688 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23821.814688 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14532.049758 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14532.049758 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 75250 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 21993.786116 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21993.786116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 21993.786116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21993.786116 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 8574653 # number of writebacks +system.cpu.dcache.writebacks::total 8574653 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 754189 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 754189 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1894189 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1894189 # number of WriteReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.inst 150 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 150 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 2648378 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2648378 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 2648378 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2648378 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7310957 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7310957 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2432859 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2432859 # number of WriteReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.inst 1244894 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244894 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 246248 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 246248 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # 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mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.054205 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054205 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.054205 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11291.261554 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11291.261554 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11291.261554 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11291.261554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11291.261554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11291.261554 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 33751616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33743319 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7503603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1688467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1581795 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 49741 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 49742 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2372919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2372919 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48947837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30709223 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 697396 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2259044 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 82613500 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1566322176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1215506888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2302360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7713224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2791844648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 568944 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 45280303 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.002552 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.050452 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 45164753 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115550 0.26% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 45280303 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 31745616637 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 870000 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36745726780 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15986739626 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 411079115 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1295977131 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 1126830 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64583.745426 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 39448197 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1188930 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 33.179579 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 13946888021000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 34952.581213 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 365.608431 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 461.071203 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 28804.484579 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.533334 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005579 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007035 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.439522 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.985470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 475 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61625 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 455 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1805 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5403 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54172 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.007248 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.940323 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 361655243 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 361655243 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 952821 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 272081 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 31479251 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 32704153 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 7503603 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7503603 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.inst 11325 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 11325 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1470476 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1470476 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 952821 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 272081 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 32949727 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 34174629 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 952821 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 272081 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 32949727 # number of overall hits -system.cpu.l2cache.overall_hits::total 34174629 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11332 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 15714 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 472686 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 499732 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.inst 38413 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 38413 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 1 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 902443 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 902443 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 11332 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 15714 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 1375129 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1402175 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 11332 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 15714 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 1375129 # number of overall misses -system.cpu.l2cache.overall_misses::total 1402175 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 888032250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1212828000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35148842209 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 37249702459 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 434827365 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 434827365 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 23499 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 23499 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 65253641861 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 65253641861 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 888032250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1212828000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 100402484070 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 102503344320 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 888032250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1212828000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 100402484070 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 102503344320 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 964153 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 287795 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 31951937 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 33203885 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 7503603 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 7503603 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 49738 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 49738 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2372919 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2372919 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 964153 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 287795 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 34324856 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 35576804 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 964153 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 287795 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 34324856 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 35576804 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011753 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.054601 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014794 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015050 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.772307 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.772307 # miss rate for UpgradeReq accesses +system.cpu.l2cache.tags.replacements 1618781 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65312.211718 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 40301488 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1682083 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.959274 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5745484000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36153.667077 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 338.579375 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 416.289773 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 28403.675493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.551661 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005166 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006352 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.433406 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996585 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63024 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 277 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2429 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5550 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54509 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961670 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 370683226 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 370683226 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 969390 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 282718 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 31773452 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 33025560 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 8574653 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 8574653 # number of Writeback hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.inst 700619 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::total 700619 # number of WriteInvalidateReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.inst 10899 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 10899 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1669806 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1669806 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 969390 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 282718 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 33443258 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 34695366 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 969390 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 282718 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 33443258 # number of overall hits +system.cpu.l2cache.overall_hits::total 34695366 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6426 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5473 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 442244 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 454143 # number of ReadReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.inst 544275 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::total 544275 # number of WriteInvalidateReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.inst 39165 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 39165 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 713266 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 713266 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 6426 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5473 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 1155510 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1167409 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 6426 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5473 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 1155510 # number of overall misses +system.cpu.l2cache.overall_misses::total 1167409 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018991 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.013727 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013564 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.inst 0.437206 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.437206 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.782299 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782299 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.380309 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.380309 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011753 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.054601 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040062 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.039412 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011753 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.054601 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040062 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039412 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65925.630957 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64757.286496 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61777.015049 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61964.812173 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst inf # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10015.186499 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.186499 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59479.473034 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59479.473034 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65925.630957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64757.286496 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60269.204596 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60365.217187 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65925.630957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64757.286496 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60269.204596 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60365.217187 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.299305 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.299305 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006585 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033397 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.032551 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006585 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033397 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.032551 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67053.809611 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63089.856716 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63183.817112 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 23362.548706 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23362.548706 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10009.234087 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.234087 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61833.318672 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61833.318672 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67053.809611 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62314.213317 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62358.670485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67053.809611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62314.213317 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62358.670485 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -1005,246 +974,203 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1384853655 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1384853655 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 168902945 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 168902945 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 151918527 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 151918527 # number of WriteReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst 1581795 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 1581795 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 4090248 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4090248 # 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number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.inst 12349880 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12349880 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 12349880 # number of overall misses -system.cpu.dcache.overall_misses::total 12349880 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 130169188997 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 130169188997 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 162013771213 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 162013771213 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 3579343752 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 3579343752 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 26501 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 26501 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 292182960210 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 292182960210 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 292182960210 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 292182960210 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 176940842 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 176940842 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 156230510 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 156230510 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst 1581795 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1581795 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 4337484 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4337484 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 4335752 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4335752 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 333171352 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 333171352 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 333171352 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 333171352 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.045427 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.045427 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.027600 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027600 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.057000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.037068 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037068 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.037068 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037068 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16194.433569 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.433569 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 37572.915110 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37572.915110 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14477.437558 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14477.437558 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26501 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23658.769171 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23658.769171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23658.769171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23658.769171 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 1581795 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7503603 # number of writebacks -system.cpu.dcache.writebacks::total 7503603 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 754441 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 754441 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1888429 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1888429 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 2642870 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2642870 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 2642870 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2642870 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7283456 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7283456 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2422384 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2422384 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 247233 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 247233 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9705840 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9705840 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9705840 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9705840 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 104220169248 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 104220169248 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 83386178898 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83386178898 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 50958353731 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 50958353731 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 3083220248 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3083220248 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 24499 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 24499 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 187606348146 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 187606348146 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 187606348146 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187606348146 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5728567000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5728567000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 5584485000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5584485000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 11313052000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11313052000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.041163 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041163 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.056999 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056999 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.029132 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029132 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.029132 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029132 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14309.164392 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14309.164392 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 34423.187611 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34423.187611 # average WriteReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst inf # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12470.909013 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.909013 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 19329.223246 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19329.223246 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 19329.223246 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19329.223246 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 115484 # number of replacements -system.iocache.tags.tagsinuse 10.452726 # Cycle average of tags in use +system.cpu.toL2Bus.trans_dist::ReadReq 34021842 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 34013749 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8574653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244894 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 50067 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 50069 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2383072 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2383072 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49422067 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31180667 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 697225 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2277994 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 83577953 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581505984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1264852800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2305528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7806528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2856470840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 563561 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 46295151 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.002496 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.049898 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 46179597 99.75% 99.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115554 0.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 46295151 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32987192886 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 1194000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 37103090732 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 15825165926 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 409755911 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 1302956232 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40416 # Transaction distribution +system.iobus.trans_dist::ReadResp 40416 # Transaction distribution +system.iobus.trans_dist::WriteReq 136733 # Transaction distribution +system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231028 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231028 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354298 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334544 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334544 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492950 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 1042369212 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179072505 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115495 # number of replacements +system.iocache.tags.tagsinuse 10.448328 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115511 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13140359698000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.516791 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935936 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219799 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433496 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653295 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13141221301000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.519405 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928922 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219963 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433058 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653020 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040243 # Number of tag accesses -system.iocache.tags.data_accesses 1040243 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1039983 # Number of tag accesses +system.iocache.tags.data_accesses 1039983 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8850 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8887 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 46 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 46 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8838 # number of demand (read+write) misses -system.iocache.demand_misses::total 8878 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8850 # number of demand (read+write) misses +system.iocache.demand_misses::total 8890 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8838 # number of overall misses -system.iocache.overall_misses::total 8878 # number of overall misses +system.iocache.overall_misses::realview.ide 8850 # number of overall misses +system.iocache.overall_misses::total 8890 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1936499108 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1941984108 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1921500610 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1926985610 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28836803097 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28836803097 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1936499108 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1942323108 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1921500610 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1927324610 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1936499108 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1942323108 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1921500610 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1927324610 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8850 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8887 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106710 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106710 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8838 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8878 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8850 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8890 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8838 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8878 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8850 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8890 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000431 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000431 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -1252,53 +1178,61 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 219110.557592 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 218815.110761 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 217118.712994 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 216831.957916 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270351.787829 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270351.787829 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 219110.557592 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 218779.354359 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 217118.712994 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 216796.919010 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 219110.557592 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 218779.354359 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 53642 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 217118.712994 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 216796.919010 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 224459 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27520 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.770856 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.156214 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8850 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8887 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8838 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8878 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8850 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8890 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8838 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8878 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8850 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8890 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1476815114 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1480376114 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1461199612 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1464760612 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6530998375 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6530998375 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23290267105 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23290267105 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1476815114 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1480559114 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1461199612 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1464943612 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1476815114 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1480559114 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1461199612 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1464943612 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses @@ -1306,18 +1240,112 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167098.338312 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 166802.942423 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165107.300791 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 164820.593226 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218351.712902 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218351.712902 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 167098.338312 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 166767.190133 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 165107.300791 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 164785.558155 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 167098.338312 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 166767.190133 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 165107.300791 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 164785.558155 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 549050 # Transaction distribution +system.membus.trans_dist::ReadResp 549050 # Transaction distribution +system.membus.trans_dist::WriteReq 33869 # Transaction distribution +system.membus.trans_dist::WriteResp 33869 # Transaction distribution +system.membus.trans_dist::Writeback 1483846 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 650746 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 650746 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39985 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39987 # Transaction distribution +system.membus.trans_dist::ReadExReq 712642 # Transaction distribution +system.membus.trans_dist::ReadExResp 712642 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4987889 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5118031 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335345 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335345 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5453376 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 200958508 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201129408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14066624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 215196032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3058 # Total snoops (count) +system.membus.snoop_fanout::samples 3350229 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 3350229 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 3350229 # Request fanout histogram +system.membus.reqLayer0.occupancy 113834500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5697498 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 21359860992 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 12431404244 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186704495 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index 173ad2168..4496ee012 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,142 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.557115 # Number of seconds simulated -sim_ticks 51557114994500 # Number of ticks simulated -final_tick 51557114994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.320621 # Number of seconds simulated +sim_ticks 51320620981500 # Number of ticks simulated +final_tick 51320620981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81227 # Simulator instruction rate (inst/s) -host_op_rate 95475 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3758004040 # Simulator tick rate (ticks/s) -host_mem_usage 668380 # Number of bytes of host memory used -host_seconds 13719.28 # Real time elapsed on the host -sim_insts 1114380469 # Number of instructions simulated -sim_ops 1309844804 # Number of ops (including micro ops) simulated +host_inst_rate 75246 # Simulator instruction rate (inst/s) +host_op_rate 88415 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4505389037 # Simulator tick rate (ticks/s) +host_mem_usage 667676 # Number of bytes of host memory used +host_seconds 11390.94 # Real time elapsed on the host +sim_insts 857117694 # Number of instructions simulated +sim_ops 1007133124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 437568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1002304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 1237760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6145632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 128560840 # Number of bytes read from this memory -system.physmem.bytes_read::total 137384104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6145632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6145632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 102180288 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 102783780 # Number of bytes written to this memory -system.physmem.bytes_written::total 211790564 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 6837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 15661 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 19340 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 111978 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2008776 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2162592 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1596567 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 1608248 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3311479 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 8487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 19441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 24008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 119200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2493562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2664697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 119200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 119200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1981885 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 132406 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1993591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4107882 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1981885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 140894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 19441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 24008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 119200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4487152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6772580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2162592 # Number of read requests accepted -system.physmem.writeReqs 3311479 # Number of write requests accepted -system.physmem.readBursts 2162592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 3311479 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 138204608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 201280 # Total number of bytes read from write queue -system.physmem.bytesWritten 207618304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 137384104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 211790564 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 3145 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 67428 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48470 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 140382 # Per bank write bursts -system.physmem.perBankRdBursts::1 139333 # Per bank write bursts -system.physmem.perBankRdBursts::2 140658 # Per bank write bursts -system.physmem.perBankRdBursts::3 133921 # Per bank write bursts -system.physmem.perBankRdBursts::4 130324 # Per bank write bursts -system.physmem.perBankRdBursts::5 134612 # Per bank write bursts -system.physmem.perBankRdBursts::6 126217 # Per bank write bursts -system.physmem.perBankRdBursts::7 133097 # Per bank write bursts -system.physmem.perBankRdBursts::8 129592 # Per bank write bursts -system.physmem.perBankRdBursts::9 157619 # Per bank write bursts -system.physmem.perBankRdBursts::10 133394 # Per bank write bursts -system.physmem.perBankRdBursts::11 133867 # Per bank write bursts -system.physmem.perBankRdBursts::12 132326 # Per bank write bursts -system.physmem.perBankRdBursts::13 132284 # Per bank write bursts -system.physmem.perBankRdBursts::14 133117 # Per bank write bursts -system.physmem.perBankRdBursts::15 128704 # Per bank write bursts -system.physmem.perBankWrBursts::0 201659 # Per bank write bursts -system.physmem.perBankWrBursts::1 203665 # Per bank write bursts -system.physmem.perBankWrBursts::2 231223 # Per bank write bursts -system.physmem.perBankWrBursts::3 188549 # Per bank write bursts -system.physmem.perBankWrBursts::4 224931 # Per bank write bursts -system.physmem.perBankWrBursts::5 188791 # Per bank write bursts -system.physmem.perBankWrBursts::6 176287 # Per bank write bursts -system.physmem.perBankWrBursts::7 226882 # Per bank write bursts -system.physmem.perBankWrBursts::8 203233 # Per bank write bursts -system.physmem.perBankWrBursts::9 233524 # Per bank write bursts -system.physmem.perBankWrBursts::10 253232 # Per bank write bursts -system.physmem.perBankWrBursts::11 198347 # Per bank write bursts -system.physmem.perBankWrBursts::12 181957 # Per bank write bursts -system.physmem.perBankWrBursts::13 175879 # Per bank write bursts -system.physmem.perBankWrBursts::14 180282 # Per bank write bursts -system.physmem.perBankWrBursts::15 175595 # Per bank write bursts +system.physmem.bytes_read::cpu.dtb.walker 227264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 206272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5756576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 43073416 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 400256 # Number of bytes read from this memory +system.physmem.bytes_read::total 49663784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5756576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5756576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69780544 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 69801124 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3551 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3223 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 105899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 673035 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6254 # Number of read requests responded to by this memory +system.physmem.num_reads::total 791962 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1090321 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1092894 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 112169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 839300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 967716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 112169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1359698 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1360099 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1359698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 112169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 839701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2327815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 791962 # Number of read requests accepted +system.physmem.writeReqs 1696531 # Number of write requests accepted +system.physmem.readBursts 791962 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1696531 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 50649920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35648 # Total number of bytes read from write queue +system.physmem.bytesWritten 108090368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 49663784 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 108433892 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 557 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7601 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 35291 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 50546 # Per bank write bursts +system.physmem.perBankRdBursts::1 51810 # Per bank write bursts +system.physmem.perBankRdBursts::2 46789 # Per bank write bursts +system.physmem.perBankRdBursts::3 46242 # Per bank write bursts +system.physmem.perBankRdBursts::4 46096 # Per bank write bursts +system.physmem.perBankRdBursts::5 52242 # Per bank write bursts +system.physmem.perBankRdBursts::6 46925 # Per bank write bursts +system.physmem.perBankRdBursts::7 49452 # Per bank write bursts +system.physmem.perBankRdBursts::8 44750 # Per bank write bursts +system.physmem.perBankRdBursts::9 73148 # Per bank write bursts +system.physmem.perBankRdBursts::10 48402 # Per bank write bursts +system.physmem.perBankRdBursts::11 51457 # Per bank write bursts +system.physmem.perBankRdBursts::12 45806 # Per bank write bursts +system.physmem.perBankRdBursts::13 48601 # Per bank write bursts +system.physmem.perBankRdBursts::14 42635 # Per bank write bursts +system.physmem.perBankRdBursts::15 46504 # Per bank write bursts +system.physmem.perBankWrBursts::0 106325 # Per bank write bursts +system.physmem.perBankWrBursts::1 106592 # Per bank write bursts +system.physmem.perBankWrBursts::2 106293 # Per bank write bursts +system.physmem.perBankWrBursts::3 105191 # Per bank write bursts +system.physmem.perBankWrBursts::4 106687 # Per bank write bursts +system.physmem.perBankWrBursts::5 109171 # Per bank write bursts +system.physmem.perBankWrBursts::6 103226 # Per bank write bursts +system.physmem.perBankWrBursts::7 105745 # Per bank write bursts +system.physmem.perBankWrBursts::8 103090 # Per bank write bursts +system.physmem.perBankWrBursts::9 109771 # Per bank write bursts +system.physmem.perBankWrBursts::10 107182 # Per bank write bursts +system.physmem.perBankWrBursts::11 108709 # Per bank write bursts +system.physmem.perBankWrBursts::12 102154 # Per bank write bursts +system.physmem.perBankWrBursts::13 106063 # Per bank write bursts +system.physmem.perBankWrBursts::14 100653 # Per bank write bursts +system.physmem.perBankWrBursts::15 102060 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 190 # Number of times write queue was full causing retry -system.physmem.totGap 51557113761500 # Total gap between requests +system.physmem.numWrRetry 63 # Number of times write queue was full causing retry +system.physmem.totGap 51320619748500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2141307 # Read request sizes (log2) +system.physmem.readPktSize::6 770677 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 3308906 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1296550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 764534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1693958 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 524690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 218670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11094 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -162,162 +159,159 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 55343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 88539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 132669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 172060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 179259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 199827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 201826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 215089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 217686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 234764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 216813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 209096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 190795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 202440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 157954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 153989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 157951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 145311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 3461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 2987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 474 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1034839 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 334.179783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.532509 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.014667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 392208 37.90% 37.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 234584 22.67% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 87901 8.49% 69.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 49413 4.77% 73.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 38348 3.71% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 26689 2.58% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21988 2.12% 82.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25501 2.46% 84.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 158207 15.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1034839 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 135592 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.925969 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 128.724301 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 135587 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-43007 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 135592 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 135592 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.924981 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.930688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.164557 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 101303 74.71% 74.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 7599 5.60% 80.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 12845 9.47% 89.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 3908 2.88% 92.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 2324 1.71% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 925 0.68% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 2932 2.16% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1250 0.92% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 889 0.66% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 249 0.18% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 327 0.24% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 193 0.14% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 473 0.35% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 16 0.01% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 22 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 28 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 17 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 31 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 89 0.07% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 56 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 42 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 15 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 15 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 35109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 66510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 80685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 95220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 95674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 107871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 105650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 115186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 109604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 123316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 110089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 98131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 89808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 90193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 76388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 75197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 74826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 71320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 2041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 151 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 519847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 305.358892 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.693203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.458813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 210597 40.51% 40.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 125304 24.10% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44434 8.55% 73.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23828 4.58% 77.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16026 3.08% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10297 1.98% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8038 1.55% 84.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7736 1.49% 85.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 73587 14.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 519847 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65806 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.026092 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 69.420005 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 65801 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 65806 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65806 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.665015 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 22.295407 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 18.784846 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 44130 67.06% 67.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 6726 10.22% 77.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 8110 12.32% 89.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 2086 3.17% 92.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 1158 1.76% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 536 0.81% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 588 0.89% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 530 0.81% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 479 0.73% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 220 0.33% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 383 0.58% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 149 0.23% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 276 0.42% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 79 0.12% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 128 0.19% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 41 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 35 0.05% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 20 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 44 0.07% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 20 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 23 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 10 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 10 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::216-223 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 6 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 5 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 5 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 135592 # Writes before turning the bus around for reads -system.physmem.totQLat 43990891280 # Total ticks spent queuing -system.physmem.totMemAccLat 84480522530 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10797235000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20371.37 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::224-231 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 65806 # Writes before turning the bus around for reads +system.physmem.totQLat 15790981009 # Total ticks spent queuing +system.physmem.totMemAccLat 30629824759 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3957025000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19953.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39121.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.68 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38703.10 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing -system.physmem.readRowHits 1747291 # Number of row buffer hits during reads -system.physmem.writeRowHits 2621349 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.91 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 9418422.55 # Average gap between requests -system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49290195125250 # Time in different power states -system.physmem.memoryStateTime::REF 1721605340000 # Time in different power states +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.05 # Average write queue length when enqueuing +system.physmem.readRowHits 603831 # Number of row buffer hits during reads +system.physmem.writeRowHits 1356638 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes +system.physmem.avgGap 20623172.24 # Average gap between requests +system.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49368372569000 # Time in different power states +system.physmem.memoryStateTime::REF 1713708100000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 545313634750 # Time in different power states +system.physmem.memoryStateTime::ACT 238539960500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3951453240 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3871929600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2156050875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2112660000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 8412588600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 8431020000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 10640075760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 10381277520 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3367460045040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3367460045040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1383947967870 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1368871606665 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29720278968750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29733503847000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34496847150135 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34494632385825 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.099654 # Core power per rank (mW) -system.physmem.averagePower::1 669.056696 # Core power per rank (mW) +system.physmem.actEnergy::0 1984348800 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 1945694520 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1082730000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1061638875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 3042748800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 3130163400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 5503010400 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 5441139360 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3352013043600 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3352013043600 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1228384903950 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1226638074825 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29714838054000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29716370360250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34306848839550 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34306600114830 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.480867 # Core power per rank (mW) +system.physmem.averagePower::1 668.476020 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory @@ -334,201 +328,22 @@ system.realview.nvmem.bw_inst_read::total 8 # I system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 657217 # Transaction distribution -system.membus.trans_dist::ReadResp 657217 # Transaction distribution -system.membus.trans_dist::WriteReq 33865 # Transaction distribution -system.membus.trans_dist::WriteResp 33865 # Transaction distribution -system.membus.trans_dist::Writeback 1596567 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1712339 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1712339 # Transaction distribution -system.membus.trans_dist::UpgradeReq 48473 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 48476 # Transaction distribution -system.membus.trans_dist::ReadExReq 1541174 # Transaction distribution -system.membus.trans_dist::ReadExResp 1541174 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9221519 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9351669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 229018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9580687 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341910604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 342081160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7264064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 349345224 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2022 # Total snoops (count) -system.membus.snoop_fanout::samples 5500895 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5500895 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 5500895 # Request fanout histogram -system.membus.reqLayer0.occupancy 109641999 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5450500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 32462148974 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 21571101815 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186532342 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 40379 # Transaction distribution -system.iobus.trans_dist::ReadResp 40379 # Transaction distribution -system.iobus.trans_dist::WriteReq 136716 # Transaction distribution -system.iobus.trans_dist::WriteResp 136733 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 17 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354224 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492654 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 981079506 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179002658 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 291488483 # Number of BP lookups -system.cpu.branchPred.condPredicted 200150149 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13608043 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 209143322 # Number of BTB lookups -system.cpu.branchPred.BTBHits 138326751 # Number of BTB hits +system.cpu.branchPred.lookups 226428976 # Number of BP lookups +system.cpu.branchPred.condPredicted 151471445 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12246087 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159886473 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104578062 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.139693 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37688944 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 403819 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.407698 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31061917 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 345275 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -552,25 +367,25 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 206311750 # DTB read hits -system.cpu.checker.dtb.read_misses 258027 # DTB read misses -system.cpu.checker.dtb.write_hits 190103200 # DTB write hits -system.cpu.checker.dtb.write_misses 94684 # DTB write misses -system.cpu.checker.dtb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.checker.dtb.read_hits 161215407 # DTB read hits +system.cpu.checker.dtb.read_misses 149229 # DTB read misses +system.cpu.checker.dtb.write_hits 146260364 # DTB write hits +system.cpu.checker.dtb.write_misses 51460 # DTB write misses +system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 89489 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 72721 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 10233 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 7177 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 24751 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 206569777 # DTB read accesses -system.cpu.checker.dtb.write_accesses 190197884 # DTB write accesses +system.cpu.checker.dtb.perms_faults 19208 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 161364636 # DTB read accesses +system.cpu.checker.dtb.write_accesses 146311824 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 396414950 # DTB hits -system.cpu.checker.dtb.misses 352711 # DTB misses -system.cpu.checker.dtb.accesses 396767661 # DTB accesses +system.cpu.checker.dtb.hits 307475771 # DTB hits +system.cpu.checker.dtb.misses 200689 # DTB misses +system.cpu.checker.dtb.accesses 307676460 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -592,28 +407,28 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 1114925280 # ITB inst hits -system.cpu.checker.itb.inst_misses 131008 # ITB inst misses +system.cpu.checker.itb.inst_hits 857529218 # ITB inst hits +system.cpu.checker.itb.inst_misses 120798 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 61860 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 52233 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 1115056288 # ITB inst accesses -system.cpu.checker.itb.hits 1114925280 # DTB hits -system.cpu.checker.itb.misses 131008 # DTB misses -system.cpu.checker.itb.accesses 1115056288 # DTB accesses -system.cpu.checker.numCycles 1310563748 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 857650016 # ITB inst accesses +system.cpu.checker.itb.hits 857529218 # DTB hits +system.cpu.checker.itb.misses 120798 # DTB misses +system.cpu.checker.itb.accesses 857650016 # DTB accesses +system.cpu.checker.numCycles 1007708571 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -639,25 +454,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 220000246 # DTB read hits -system.cpu.dtb.read_misses 1007031 # DTB read misses -system.cpu.dtb.write_hits 193886106 # DTB write hits -system.cpu.dtb.write_misses 416122 # DTB write misses -system.cpu.dtb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 171196432 # DTB read hits +system.cpu.dtb.read_misses 671544 # DTB read misses +system.cpu.dtb.write_hits 149025904 # DTB write hits +system.cpu.dtb.write_misses 258759 # DTB write misses +system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 89690 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 112 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15179 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72979 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 104 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10362 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 87251 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 221007277 # DTB read accesses -system.cpu.dtb.write_accesses 194302228 # DTB write accesses +system.cpu.dtb.perms_faults 68614 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 171867976 # DTB read accesses +system.cpu.dtb.write_accesses 149284663 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 413886352 # DTB hits -system.cpu.dtb.misses 1423153 # DTB misses -system.cpu.dtb.accesses 415309505 # DTB accesses +system.cpu.dtb.hits 320222336 # DTB hits +system.cpu.dtb.misses 930303 # DTB misses +system.cpu.dtb.accesses 321152639 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -679,639 +494,803 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 465588468 # ITB inst hits -system.cpu.itb.inst_misses 176797 # ITB inst misses +system.cpu.itb.inst_hits 360051885 # ITB inst hits +system.cpu.itb.inst_misses 161655 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 63536 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53701 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 462381 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 372863 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 465765265 # ITB inst accesses -system.cpu.itb.hits 465588468 # DTB hits -system.cpu.itb.misses 176797 # DTB misses -system.cpu.itb.accesses 465765265 # DTB accesses -system.cpu.numCycles 2146849645 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 360213540 # ITB inst accesses +system.cpu.itb.hits 360051885 # DTB hits +system.cpu.itb.misses 161655 # DTB misses +system.cpu.itb.accesses 360213540 # DTB accesses +system.cpu.numCycles 1576874693 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 791511347 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1301628389 # Number of instructions fetch has processed -system.cpu.fetch.Branches 291488483 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 176015695 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1268750537 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29307286 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4254748 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 12217982 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1219824 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 381 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 465107423 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6746831 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 53918 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2092636388 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.729302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.142136 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 648679854 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1010290403 # Number of instructions fetch has processed +system.cpu.fetch.Branches 226428976 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135639979 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 852655064 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26160452 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3389644 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9240220 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1021673 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 362 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 359662567 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6136086 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 47510 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1528093850 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.774691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.161324 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1367675983 65.36% 65.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 280886167 13.42% 78.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 86945610 4.15% 82.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 357128628 17.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 965958627 63.21% 63.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215893777 14.13% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70817340 4.63% 81.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 275424106 18.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2092636388 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.135775 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.606297 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 614820490 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 852644163 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 531180111 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 83391963 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10599661 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41490545 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4112846 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1415541998 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32718079 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10599661 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 678805488 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 83662136 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 556428904 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 549849830 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 213290369 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1391734034 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 7977079 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7435136 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 893230 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1023922 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 127479585 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 25199 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1342075875 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2217645602 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1652184740 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1639045 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1263873564 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78202308 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44203192 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39719264 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 172796539 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 223511224 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 198396121 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12647992 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11061331 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1338396177 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 44508712 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1370133902 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4153047 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65240654 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41320787 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 373617 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2092636388 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.654741 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.915536 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1528093850 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.143594 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.640692 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 527180052 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 504302107 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 436284853 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 51059674 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9267164 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33905862 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3872221 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1095429909 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29099398 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9267164 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 572442291 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46180186 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 363186865 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 441948285 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 95069059 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1075584704 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6788495 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4945824 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 318864 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 589123 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 42956715 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 21763 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1023437611 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1659121727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1272319582 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1685396 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 957674620 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65762988 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27435128 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23745394 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 104747763 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 175168030 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 152601618 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9963388 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9061948 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1040022976 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27737741 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1056135120 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3300763 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53598061 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33623556 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 314928 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1528093850 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.691145 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.927830 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1237717942 59.15% 59.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 455529583 21.77% 80.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 292996726 14.00% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96986296 4.63% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9377226 0.45% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 28615 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 873977548 57.19% 57.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 338098484 22.13% 79.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 236626258 15.49% 94.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72801252 4.76% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6571176 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19132 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2092636388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1528093850 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 74528454 34.28% 34.28% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90672 0.04% 34.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26772 0.01% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 287 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 58830485 27.06% 61.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83911289 38.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58371154 35.14% 35.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100885 0.06% 35.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26756 0.02% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 767 0.00% 35.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44544414 26.81% 62.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63075062 37.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 945793660 69.03% 69.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2946266 0.22% 69.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 129775 0.01% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 114397 0.01% 69.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 224851656 16.41% 85.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 196298100 14.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 727332382 68.87% 68.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2546997 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 123061 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 120668 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 175096796 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150915164 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1370133902 # Type of FU issued -system.cpu.iq.rate 0.638207 # Inst issue rate -system.cpu.iq.fu_busy_cnt 217387959 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.158662 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5052021388 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1447405501 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1347303683 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2423809 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 923681 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 885699 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1585997449 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1524411 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5766333 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1056135120 # Type of FU issued +system.cpu.iq.rate 0.669765 # Inst issue rate +system.cpu.iq.fu_busy_cnt 166119038 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157290 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3807304115 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1120557954 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1038099529 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2479775 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 941816 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 907592 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1220693938 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1560218 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4348848 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16996131 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24128 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 185382 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8259714 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13855252 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14404 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 142361 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6337064 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3623609 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3385962 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2552747 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1859122 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10599661 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11961718 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7304667 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1383179145 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9267164 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6379535 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3965873 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1067985048 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 223511224 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 198396121 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39177517 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 185228 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6936317 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 185382 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4274350 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5730421 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10004771 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1356817685 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 220004444 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11924579 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 175168030 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 152601618 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23314125 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 62024 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3832996 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 142361 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3691152 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5135953 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8827105 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1044930592 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 171186057 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10287379 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 274256 # number of nop insts executed -system.cpu.iew.exec_refs 413901554 # number of memory reference insts executed -system.cpu.iew.exec_branches 257473473 # Number of branches executed -system.cpu.iew.exec_stores 193897110 # Number of stores executed -system.cpu.iew.exec_rate 0.632004 # Inst execution rate -system.cpu.iew.wb_sent 1349182874 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1348189382 # cumulative count of insts written-back -system.cpu.iew.wb_producers 579023420 # num instructions producing a value -system.cpu.iew.wb_consumers 949767765 # num instructions consuming a value +system.cpu.iew.exec_nop 224331 # number of nop insts executed +system.cpu.iew.exec_refs 320208959 # number of memory reference insts executed +system.cpu.iew.exec_branches 198322451 # Number of branches executed +system.cpu.iew.exec_stores 149022902 # Number of stores executed +system.cpu.iew.exec_rate 0.662659 # Inst execution rate +system.cpu.iew.wb_sent 1039793819 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1039007121 # cumulative count of insts written-back +system.cpu.iew.wb_producers 442154878 # num instructions producing a value +system.cpu.iew.wb_consumers 715627882 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.627985 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.609647 # average fanout of values written-back +system.cpu.iew.wb_rate 0.658903 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.617856 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 62443917 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 44135095 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9554061 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2078483160 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.630193 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.269789 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51471265 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27422813 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8433025 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1516084212 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.664299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.291990 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1396354428 67.18% 67.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 397736022 19.14% 86.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 152396085 7.33% 93.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44287772 2.13% 95.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35996912 1.73% 97.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18656723 0.90% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10905184 0.52% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5449343 0.26% 99.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16700691 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 998537580 65.86% 65.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 291350566 19.22% 85.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 121957393 8.04% 93.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36696853 2.42% 95.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28610485 1.89% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14255849 0.94% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8557612 0.56% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4232636 0.28% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11885238 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2078483160 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1114380469 # Number of instructions committed -system.cpu.commit.committedOps 1309844804 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1516084212 # Number of insts commited each cycle +system.cpu.commit.committedInsts 857117694 # Number of instructions committed +system.cpu.commit.committedOps 1007133124 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 396651499 # Number of memory references committed -system.cpu.commit.loads 206515092 # Number of loads committed -system.cpu.commit.membars 9189565 # Number of memory barriers committed -system.cpu.commit.branches 249089949 # Number of branches committed -system.cpu.commit.fp_insts 873640 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1196978104 # Number of committed integer instructions. -system.cpu.commit.function_calls 31078874 # Number of function calls committed. +system.cpu.commit.refs 307577331 # Number of memory references committed +system.cpu.commit.loads 161312777 # Number of loads committed +system.cpu.commit.membars 7014752 # Number of memory barriers committed +system.cpu.commit.branches 191334741 # Number of branches committed +system.cpu.commit.fp_insts 896026 # Number of committed floating point instructions. +system.cpu.commit.int_insts 925144388 # Number of committed integer instructions. +system.cpu.commit.function_calls 25493443 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 910428363 69.51% 69.51% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2554988 0.20% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 104143 0.01% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 105769 0.01% 69.72% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.72% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.72% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.72% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 206515092 15.77% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 190136407 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 697181314 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2164633 0.21% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98281 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 161312777 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 146264554 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1309844804 # Class of committed instruction -system.cpu.commit.bw_lim_events 16700691 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 1007133124 # Class of committed instruction +system.cpu.commit.bw_lim_events 11885238 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3424556806 # The number of ROB reads -system.cpu.rob.rob_writes 2758622493 # The number of ROB writes -system.cpu.timesIdled 9031521 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 54213257 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100967380384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1114380469 # Number of Instructions Simulated -system.cpu.committedOps 1309844804 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.926496 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.926496 # CPI: Total CPI of All Threads -system.cpu.ipc 0.519077 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.519077 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1611998606 # number of integer regfile reads -system.cpu.int_regfile_writes 948639329 # number of integer regfile writes -system.cpu.fp_regfile_reads 1420015 # number of floating regfile reads -system.cpu.fp_regfile_writes 765124 # number of floating regfile writes -system.cpu.cc_regfile_reads 315259155 # number of cc regfile reads -system.cpu.cc_regfile_writes 316098925 # number of cc regfile writes -system.cpu.misc_regfile_reads 6952427793 # number of misc regfile reads -system.cpu.misc_regfile_writes 45059384 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 28539920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28531649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33865 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33865 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 9369509 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1712344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1605675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 61529 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 61535 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3074731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3074731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33703094 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37825776 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 810571 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3115869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 75455310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1077469744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1502191576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2724416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10868120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2593253856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 644632 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 42703026 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9.002705 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051942 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 42587504 99.73% 99.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 115522 0.27% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 42703026 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32333793873 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 871500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25296093441 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19876823538 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 472614279 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1760067316 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 16829629 # number of replacements -system.cpu.icache.tags.tagsinuse 511.959617 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 447510611 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16830141 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.589831 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 12236526000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.959617 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 2555181565 # The number of ROB reads +system.cpu.rob.rob_writes 2129123637 # The number of ROB writes +system.cpu.timesIdled 8137810 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 48780843 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101064367400 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 857117694 # Number of Instructions Simulated +system.cpu.committedOps 1007133124 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.839741 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.839741 # CPI: Total CPI of All Threads +system.cpu.ipc 0.543555 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.543555 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237020079 # number of integer regfile reads +system.cpu.int_regfile_writes 738429838 # number of integer regfile writes +system.cpu.fp_regfile_reads 1457787 # number of floating regfile reads +system.cpu.fp_regfile_writes 782552 # number of floating regfile writes +system.cpu.cc_regfile_reads 228125574 # number of cc regfile reads +system.cpu.cc_regfile_writes 228731881 # number of cc regfile writes +system.cpu.misc_regfile_reads 5247037954 # number of misc regfile reads +system.cpu.misc_regfile_writes 27486572 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9822538 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.985265 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 286045243 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9823050 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.119799 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1485814250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.985265 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1249214859 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1249214859 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 148712432 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 148712432 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 129479125 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 129479125 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 381594 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 381594 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324870 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 324870 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352883 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3352883 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3750315 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3750315 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 278191557 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 278191557 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 278573151 # number of overall hits +system.cpu.dcache.overall_hits::total 278573151 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9502058 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9502058 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11465174 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11465174 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1197022 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1197022 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233022 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1233022 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 449448 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 449448 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20967232 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20967232 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22164254 # number of overall misses +system.cpu.dcache.overall_misses::total 22164254 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 140935225401 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 140935225401 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 322991667568 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 322991667568 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 38675981880 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 38675981880 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6315194753 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6315194753 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 139001 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 139001 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 463926892969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 463926892969 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 463926892969 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 463926892969 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 158214490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 158214490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 140944299 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 140944299 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578616 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1578616 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557892 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1557892 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3802331 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3802331 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3750320 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3750320 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 299158789 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 299158789 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 300737405 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 300737405 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060058 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060058 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081345 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081345 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758273 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.758273 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791468 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791468 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118203 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118203 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.070087 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070087 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.073700 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.073700 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14832.073789 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14832.073789 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28171.545200 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28171.545200 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31366.822230 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31366.822230 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14051.002014 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14051.002014 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22126.282237 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22126.282237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20931.310973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20931.310973 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21466802 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1401851 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.313184 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 7593763 # number of writebacks +system.cpu.dcache.writebacks::total 7593763 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4321399 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.993939 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.993939 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041940 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041940 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041940 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.041940 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041940 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.041940 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11391.189693 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11391.189693 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2102 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5030 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54369 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.007568 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.942596 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 341864435 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 341864435 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1342854 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 321211 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 16739434 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 8950656 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 490.286692 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7518.567341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 19644.585230 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.569512 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004896 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007481 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.114724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.299753 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996366 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 285 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62575 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 285 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 565 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2655 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5044 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54243 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004349 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.954819 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 273181992 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 273181992 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 797530 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 297299 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1242745748 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1521537709 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6968907733 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 166557312481 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 176290503671 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1358515 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 340552 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16830142 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 9418266 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 27947475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 9369509 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 9369509 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 61526 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 61526 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 6 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3074731 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3074731 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1358515 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 340552 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 16830142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 12492997 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176184000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5289733251 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6393715501 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176071500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176071500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1103982250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465957250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11569939500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011528 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.056790 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005390 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049647 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021229 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.777590 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.777590 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.501443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.501443 # 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average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71012.621808 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71012.621808 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66214.178335 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64286.978734 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70545.291099 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70213.494723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66214.178335 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64286.978734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70545.291099 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70213.494723 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465804751 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11569787001 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004433 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010725 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005612 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.039032 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015316 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.405499 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.405499 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784600 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784600 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.208413 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.208413 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004433 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010725 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005612 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.078433 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030898 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004433 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010725 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005612 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.078433 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030898 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64684.412911 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70909.720754 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69340.102872 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39429.331460 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39429.331460 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10015.230943 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.230943 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70964.035146 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70964.035146 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.412911 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70943.293622 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70224.050007 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.412911 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70943.293622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70224.050007 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1436,336 +1416,384 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1609448196 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1609448196 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 188132338 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 188132338 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164232223 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164232223 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 465761 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 465761 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 1605675 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 1605675 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4847947 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4847947 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5335203 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5335203 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 352364561 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 352364561 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 352830322 # number of overall hits -system.cpu.dcache.overall_hits::total 352830322 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12712279 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12712279 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18968725 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18968725 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2072118 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2072118 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 550419 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 550419 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 31681004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 31681004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 33753122 # number of overall misses -system.cpu.dcache.overall_misses::total 33753122 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 203403538452 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 203403538452 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1021678237791 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1021678237791 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8626183252 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 8626183252 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 117003 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 117003 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1225081776243 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1225081776243 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1225081776243 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1225081776243 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 200844617 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 200844617 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 183200948 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 183200948 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2537879 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2537879 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1605675 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1605675 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5398366 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5398366 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5335209 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5335209 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 384045565 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 384045565 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 386583444 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 386583444 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063294 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.063294 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103541 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.103541 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816476 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.816476 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.101960 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.101960 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082493 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082493 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087311 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087311 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16000.556505 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16000.556505 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53861.197196 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53861.197196 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15672.030311 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15672.030311 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38669.285110 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38669.285110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36295.361841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36295.361841 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 38319499 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2284719 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.772084 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 1605675 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 9369509 # number of writebacks -system.cpu.dcache.writebacks::total 9369509 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5628309 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5628309 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15829986 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15829986 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265840 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 265840 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21458295 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21458295 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21458295 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21458295 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7083970 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7083970 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3120649 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3120649 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2065320 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 2065320 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 284579 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 284579 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 10204619 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 10204619 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 12269939 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 12269939 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 102477717871 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 102477717871 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 148263766896 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 148263766896 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 31611668497 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 31611668497 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 59007365277 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 59007365277 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3751055249 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3751055249 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 104997 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 104997 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250741484767 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 250741484767 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 282353153264 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 282353153264 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729434750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729434750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587276983 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587276983 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316711733 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316711733 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035271 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035271 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.017034 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.017034 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813798 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813798 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052716 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052716 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026571 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026571 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031739 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031739 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.142272 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.142272 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47510.555303 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47510.555303 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15305.942177 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15305.942177 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13181.068347 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13181.068347 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24571.371530 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24571.371530 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23011.781335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23011.781335 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 115458 # number of replacements -system.iocache.tags.tagsinuse 10.450727 # Cycle average of tags in use +system.cpu.toL2Bus.trans_dist::ReadReq 23341232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23333163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7593763 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1225967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43982 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1999866 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1999866 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30208899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27463876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 731462 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1967033 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 60371270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965659760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1114918084 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2404176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6408648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2089390668 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 611685 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 34508223 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9.003348 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.057762 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 34392703 99.67% 99.67% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 115520 0.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 34508223 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 26206492236 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 1177500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 22671590732 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13674088224 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 431886005 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 1166711358 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40382 # Transaction distribution +system.iobus.trans_dist::ReadResp 40382 # Transaction distribution +system.iobus.trans_dist::WriteReq 136733 # Transaction distribution +system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354230 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 1042360658 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179004169 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115462 # number of replacements +system.iocache.tags.tagsinuse 10.424613 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115478 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13090278324000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.528058 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.922669 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220504 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432667 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653170 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13092189065000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544618 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.879995 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039786 # Number of tag accesses -system.iocache.tags.data_accesses 1039786 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1039677 # Number of tag accesses +system.iocache.tags.data_accesses 1039677 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8816 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8853 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 17 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 17 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses -system.iocache.demand_misses::total 8853 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8816 # number of demand (read+write) misses +system.iocache.demand_misses::total 8856 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8813 # number of overall misses -system.iocache.overall_misses::total 8853 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5547000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1929395843 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1934942843 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8816 # number of overall misses +system.iocache.overall_misses::total 8856 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1927411613 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1932938613 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5886000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1929395843 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1935281843 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5886000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1929395843 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1935281843 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28910124876 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28910124876 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5866000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1927411613 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1933277613 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5866000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1927411613 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1933277613 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106681 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106681 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8816 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8856 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8816 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8856 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000159 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000159 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149918.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 218926.114036 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 218637.609379 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218626.544124 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 218337.130125 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 147150 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 218601.812154 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 147150 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 218601.812154 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 53350 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271039.196692 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271039.196692 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 218626.544124 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 218301.446816 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 218626.544124 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 218301.446816 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 226675 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27646 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.717668 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.199197 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8816 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8853 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8816 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8856 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3623000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1470987863 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1474610863 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8816 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8856 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1468863623 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1472466623 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6546677301 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6546677301 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3806000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1470987863 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1474793863 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3806000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1470987863 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1474793863 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23363269204 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23363269204 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1468863623 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1472649623 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1468863623 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1472649623 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166911.138432 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 166622.696384 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166613.387364 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 166324.028352 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219036.124691 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219036.124691 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 166613.387364 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 166288.349481 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 166613.387364 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 166288.349481 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 412825 # Transaction distribution +system.membus.trans_dist::ReadResp 412825 # Transaction distribution +system.membus.trans_dist::WriteReq 33858 # Transaction distribution +system.membus.trans_dist::WriteResp 33858 # Transaction distribution +system.membus.trans_dist::Writeback 1090321 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 603637 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 603637 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35296 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35298 # Transaction distribution +system.membus.trans_dist::ReadExReq 416163 # Transaction distribution +system.membus.trans_dist::ReadExResp 416163 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3625442 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3755550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4090619 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 144046540 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144217012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14051136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14051136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 158268148 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3264 # Total snoops (count) +system.membus.snoop_fanout::samples 2503253 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 2503253 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2503253 # Request fanout histogram +system.membus.reqLayer0.occupancy 109702500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5437999 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 16337638979 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 7836649146 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186565831 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 17164 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16179 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 6eaff03eb..e64b12ad0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,181 +1,178 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.379675 # Number of seconds simulated -sim_ticks 47379674621500 # Number of ticks simulated -final_tick 47379674621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.422278 # Number of seconds simulated +sim_ticks 47422277747000 # Number of ticks simulated +final_tick 47422277747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105231 # Simulator instruction rate (inst/s) -host_op_rate 123773 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5339286706 # Simulator tick rate (ticks/s) -host_mem_usage 910192 # Number of bytes of host memory used -host_seconds 8873.78 # Real time elapsed on the host -sim_insts 933798389 # Number of instructions simulated -sim_ops 1098335322 # Number of ops (including micro ops) simulated +host_inst_rate 91986 # Simulator instruction rate (inst/s) +host_op_rate 108182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4717167353 # Simulator tick rate (ticks/s) +host_mem_usage 870208 # Number of bytes of host memory used +host_seconds 10053.13 # Real time elapsed on the host +sim_insts 924745220 # Number of instructions simulated +sim_ops 1087564829 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 353088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 523648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1152800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 18354072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 38298624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 338240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 462784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 532064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 12967328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 29162240 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 472128 # Number of bytes read from this memory -system.physmem.bytes_read::total 102617016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1152800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 532064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1684864 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 56488832 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 66623564 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 34275268 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory -system.physmem.bytes_written::total 164218256 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 5517 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8182 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 33965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 286804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 598416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 5285 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 7231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 8357 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 202629 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 455660 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7377 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1619423 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 882638 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 1043270 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 535552 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2568188 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 7452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 11052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 24331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 387383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 808334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 7139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 9768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 11230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 273690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 615501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9965 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2165845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 24331 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 35561 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1192259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 1406163 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 723417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 144167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3466006 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1192259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 7452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 11052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 24331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1793546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 808334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 7139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 9768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 11230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 997107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 615501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 154132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5631851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1619423 # Number of read requests accepted -system.physmem.writeReqs 2568188 # Number of write requests accepted -system.physmem.readBursts 1619423 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2568188 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 103371328 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 271744 # Total number of bytes read from write queue -system.physmem.bytesWritten 158872640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 102617016 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 164218256 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 4246 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 85771 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 103144 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 111705 # Per bank write bursts -system.physmem.perBankRdBursts::1 107185 # Per bank write bursts -system.physmem.perBankRdBursts::2 95216 # Per bank write bursts -system.physmem.perBankRdBursts::3 93593 # Per bank write bursts -system.physmem.perBankRdBursts::4 97040 # Per bank write bursts -system.physmem.perBankRdBursts::5 109538 # Per bank write bursts -system.physmem.perBankRdBursts::6 103640 # Per bank write bursts -system.physmem.perBankRdBursts::7 104459 # Per bank write bursts -system.physmem.perBankRdBursts::8 87345 # Per bank write bursts -system.physmem.perBankRdBursts::9 119689 # Per bank write bursts -system.physmem.perBankRdBursts::10 87550 # Per bank write bursts -system.physmem.perBankRdBursts::11 102455 # Per bank write bursts -system.physmem.perBankRdBursts::12 98167 # Per bank write bursts -system.physmem.perBankRdBursts::13 96293 # Per bank write bursts -system.physmem.perBankRdBursts::14 97699 # Per bank write bursts -system.physmem.perBankRdBursts::15 103603 # Per bank write bursts -system.physmem.perBankWrBursts::0 151797 # Per bank write bursts -system.physmem.perBankWrBursts::1 157102 # Per bank write bursts -system.physmem.perBankWrBursts::2 173467 # Per bank write bursts -system.physmem.perBankWrBursts::3 129226 # Per bank write bursts -system.physmem.perBankWrBursts::4 217724 # Per bank write bursts -system.physmem.perBankWrBursts::5 151423 # Per bank write bursts -system.physmem.perBankWrBursts::6 153455 # Per bank write bursts -system.physmem.perBankWrBursts::7 181552 # Per bank write bursts -system.physmem.perBankWrBursts::8 127836 # Per bank write bursts -system.physmem.perBankWrBursts::9 166575 # Per bank write bursts -system.physmem.perBankWrBursts::10 140595 # Per bank write bursts -system.physmem.perBankWrBursts::11 139064 # Per bank write bursts -system.physmem.perBankWrBursts::12 135611 # Per bank write bursts -system.physmem.perBankWrBursts::13 129688 # Per bank write bursts -system.physmem.perBankWrBursts::14 173219 # Per bank write bursts -system.physmem.perBankWrBursts::15 154051 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 123008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 83392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1145824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 12461528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 54523392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 250240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 244864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 679904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 13804768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 35481280 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 451200 # Number of bytes read from this memory +system.physmem.bytes_read::total 119249400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1145824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 679904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1825728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 92428416 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory +system.physmem.bytes_written::total 92449232 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1922 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 33856 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 194733 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 851928 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3826 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10667 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 215714 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 554395 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7050 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1879304 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1444194 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1446797 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 24162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 262778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1149742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 5277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 5163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 291103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 748199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2514628 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 24162 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14337 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 38499 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1949051 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1949489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1949051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 24162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 263217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1149742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 5277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 5163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 291103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 748199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4464118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1879304 # Number of read requests accepted +system.physmem.writeReqs 1600997 # Number of write requests accepted +system.physmem.readBursts 1879304 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1600997 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 120227392 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 48064 # Total number of bytes read from write queue +system.physmem.bytesWritten 101998144 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 119249400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 102318032 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 751 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7249 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 97584 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 111371 # Per bank write bursts +system.physmem.perBankRdBursts::1 133364 # Per bank write bursts +system.physmem.perBankRdBursts::2 107237 # Per bank write bursts +system.physmem.perBankRdBursts::3 129396 # Per bank write bursts +system.physmem.perBankRdBursts::4 116369 # Per bank write bursts +system.physmem.perBankRdBursts::5 129089 # Per bank write bursts +system.physmem.perBankRdBursts::6 116664 # Per bank write bursts +system.physmem.perBankRdBursts::7 120571 # Per bank write bursts +system.physmem.perBankRdBursts::8 118226 # Per bank write bursts +system.physmem.perBankRdBursts::9 133705 # Per bank write bursts +system.physmem.perBankRdBursts::10 98234 # Per bank write bursts +system.physmem.perBankRdBursts::11 110272 # Per bank write bursts +system.physmem.perBankRdBursts::12 110364 # Per bank write bursts +system.physmem.perBankRdBursts::13 124983 # Per bank write bursts +system.physmem.perBankRdBursts::14 111960 # Per bank write bursts +system.physmem.perBankRdBursts::15 106748 # Per bank write bursts +system.physmem.perBankWrBursts::0 99185 # Per bank write bursts +system.physmem.perBankWrBursts::1 109011 # Per bank write bursts +system.physmem.perBankWrBursts::2 97054 # Per bank write bursts +system.physmem.perBankWrBursts::3 108172 # Per bank write bursts +system.physmem.perBankWrBursts::4 98286 # Per bank write bursts +system.physmem.perBankWrBursts::5 106076 # Per bank write bursts +system.physmem.perBankWrBursts::6 100140 # Per bank write bursts +system.physmem.perBankWrBursts::7 103851 # Per bank write bursts +system.physmem.perBankWrBursts::8 98795 # Per bank write bursts +system.physmem.perBankWrBursts::9 98239 # Per bank write bursts +system.physmem.perBankWrBursts::10 89198 # Per bank write bursts +system.physmem.perBankWrBursts::11 97505 # Per bank write bursts +system.physmem.perBankWrBursts::12 95822 # Per bank write bursts +system.physmem.perBankWrBursts::13 102116 # Per bank write bursts +system.physmem.perBankWrBursts::14 95043 # Per bank write bursts +system.physmem.perBankWrBursts::15 95228 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 280 # Number of times write queue was full causing retry -system.physmem.totGap 47379673169000 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 47422276363500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1598053 # Read request sizes (log2) +system.physmem.readPktSize::6 1857934 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2565585 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 575288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 378276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 198870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 124070 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 84552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 66107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 57559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 42131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 14414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 7965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 5242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1598394 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 506038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 360780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 256406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 156907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 129304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 95738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 81613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 74114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 66527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 41507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30519 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 23594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 21466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -191,159 +188,184 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 50077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 80336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 91349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 103691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 113552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 135687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 144994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 161556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 168861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 188844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 173768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 166459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 153274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 157126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 123678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 118188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 114281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 106686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 15195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 674 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 968355 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 270.813741 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.322670 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.242545 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 500729 51.71% 51.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 182951 18.89% 70.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 62910 6.50% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 30320 3.13% 80.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 27676 2.86% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 15651 1.62% 84.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 12433 1.28% 85.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 15606 1.61% 87.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 120079 12.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 968355 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 90300 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.886467 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 201.343157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 90297 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 90300 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 90300 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.490421 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 23.640759 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.748039 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 56859 62.97% 62.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 8057 8.92% 71.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 12273 13.59% 85.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 3990 4.42% 89.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1898 2.10% 92.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 944 1.05% 93.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 2681 2.97% 96.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1258 1.39% 97.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 729 0.81% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 233 0.26% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 328 0.36% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 174 0.19% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 473 0.52% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 16 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 44 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 33 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 16 0.02% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 34 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 77 0.09% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 57 0.06% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 40 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 6 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 21 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 22 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 7 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 90300 # Writes before turning the bus around for reads -system.physmem.totQLat 65880977516 # Total ticks spent queuing -system.physmem.totMemAccLat 96165546266 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8075885000 # Total ticks spent in databus transfers -system.physmem.avgQLat 40788.70 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 23051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 37353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 51054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 76742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 83422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 92810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 99100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 114191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 124207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 117512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 121939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 125600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 118087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 27656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 21524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 15466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 10008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 975956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.699905 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.562466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 280.517231 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 518192 53.10% 53.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 197775 20.26% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 73464 7.53% 80.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 39205 4.02% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 32875 3.37% 88.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 20645 2.12% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14690 1.51% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16974 1.74% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 62136 6.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 975956 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 85700 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.919883 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.914571 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 85693 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 85700 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 85700 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.596511 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.559355 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.221946 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 76419 89.17% 89.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4825 5.63% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 861 1.00% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 776 0.91% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 493 0.58% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 137 0.16% 97.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 117 0.14% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 137 0.16% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 585 0.68% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 72 0.08% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 76 0.09% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 72 0.08% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 110 0.13% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 48 0.06% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 42 0.05% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 81 0.09% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 124 0.14% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 28 0.03% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 35 0.04% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 50 0.06% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 194 0.23% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 14 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 23 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 54 0.06% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 16 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 21 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 26 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 106 0.12% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 28 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 8 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 9 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 15 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 15 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 11 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 4 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 85700 # Writes before turning the bus around for reads +system.physmem.totQLat 131185455773 # Total ticks spent queuing +system.physmem.totMemAccLat 166408324523 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9392765000 # Total ticks spent in databus transfers +system.physmem.avgQLat 69833.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 59538.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.47 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 88583.25 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 3.63 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing -system.physmem.readRowHits 1266207 # Number of row buffer hits during reads -system.physmem.writeRowHits 1862998 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.39 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.05 # Row buffer hit rate for writes -system.physmem.avgGap 11314248.90 # Average gap between requests -system.physmem.pageHitRate 76.37 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45458713155000 # Time in different power states -system.physmem.memoryStateTime::REF 1582111440000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing +system.physmem.readRowHits 1529879 # Number of row buffer hits during reads +system.physmem.writeRowHits 966437 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 60.64 # Row buffer hit rate for writes +system.physmem.avgGap 13625912.35 # Average gap between requests +system.physmem.pageHitRate 71.89 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 45568926392500 # Time in different power states +system.physmem.memoryStateTime::REF 1583533900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 338849669500 # Time in different power states +system.physmem.memoryStateTime::ACT 269814192000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3771472320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3549283920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2057847000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1936613250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 6414501600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 6183847800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 8526034080 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 7559820720 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3094609976640 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3094609976640 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1215510046335 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1201972779180 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27361567580250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27373442376000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31692457458225 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31689254697510 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.904083 # Core power per rank (mW) -system.physmem.averagePower::1 668.836485 # Core power per rank (mW) +system.physmem.actEnergy::0 3837713040 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3540506760 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2093990250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1931824125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 7519675800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 7132967400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 5325102000 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 5002210080 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3097392308400 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3097392308400 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1175879799405 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1172220553305 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 27421890099000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 27425099964000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 31713938687895 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 31712320334070 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.756196 # Core power per rank (mW) +system.physmem.averagePower::1 668.722070 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -376,15 +398,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 146587108 # Number of BP lookups -system.cpu0.branchPred.condPredicted 96932064 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7164901 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 103453764 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 67642054 # Number of BTB hits +system.cpu0.branchPred.lookups 136692903 # Number of BP lookups +system.cpu0.branchPred.condPredicted 91051024 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6675955 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 96641264 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 62499971 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.383850 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20270932 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 203679 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 64.672137 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 18343531 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 188881 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -409,25 +431,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 106134781 # DTB read hits -system.cpu0.dtb.read_misses 438400 # DTB read misses -system.cpu0.dtb.write_hits 87107060 # DTB write hits -system.cpu0.dtb.write_misses 166320 # DTB write misses -system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 98285730 # DTB read hits +system.cpu0.dtb.read_misses 371363 # DTB read misses +system.cpu0.dtb.write_hits 82429878 # DTB write hits +system.cpu0.dtb.write_misses 160428 # DTB write misses +system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 41289 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 449 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7213 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 34259 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 6211 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 39737 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 106573181 # DTB read accesses -system.cpu0.dtb.write_accesses 87273380 # DTB write accesses +system.cpu0.dtb.perms_faults 37781 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 98657093 # DTB read accesses +system.cpu0.dtb.write_accesses 82590306 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 193241841 # DTB hits -system.cpu0.dtb.misses 604720 # DTB misses -system.cpu0.dtb.accesses 193846561 # DTB accesses +system.cpu0.dtb.hits 180715608 # DTB hits +system.cpu0.dtb.misses 531791 # DTB misses +system.cpu0.dtb.accesses 181247399 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -449,519 +471,533 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 230537480 # ITB inst hits -system.cpu0.itb.inst_misses 86000 # ITB inst misses +system.cpu0.itb.inst_hits 214588445 # ITB inst hits +system.cpu0.itb.inst_misses 81035 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 29668 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24176 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 226388 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 217359 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 230623480 # ITB inst accesses -system.cpu0.itb.hits 230537480 # DTB hits -system.cpu0.itb.misses 86000 # DTB misses -system.cpu0.itb.accesses 230623480 # DTB accesses -system.cpu0.numCycles 786965482 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 214669480 # ITB inst accesses +system.cpu0.itb.hits 214588445 # DTB hits +system.cpu0.itb.misses 81035 # DTB misses +system.cpu0.itb.accesses 214669480 # DTB accesses +system.cpu0.numCycles 723605959 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 90387711 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 647691070 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 146587108 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 87912986 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 665690431 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15471710 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1846295 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 143165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6476529 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 786234 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 320116 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 230311190 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1742140 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 773386336 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.980975 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.219702 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 84128505 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 603958712 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 136692903 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 80843502 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 610845531 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14389096 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1590613 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 145998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6064926 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 691327 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 308415 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 214371554 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1629958 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 26989 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 710969863 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.995603 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.223531 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 409957196 53.01% 53.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 140998975 18.23% 71.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 49617031 6.42% 77.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 172813134 22.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 371943625 52.31% 52.31% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 132005479 18.57% 70.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 45223870 6.36% 77.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 161796889 22.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 773386336 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.186269 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.823023 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 108593313 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 378356513 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 240969730 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39977542 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5489238 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 21224089 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2292433 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 668689408 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 25030555 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5489238 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 146312922 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 57383456 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 250430469 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 242520551 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 71249700 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 650266707 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6336504 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 9477139 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 381865 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 840506 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 33815177 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 14484 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 619540415 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1001273329 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 768127423 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 806411 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 558016180 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 61524234 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16309942 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14158531 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 81487680 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 106551444 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90697387 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9851628 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8566406 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 626998472 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16435650 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 631073777 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2910747 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54340762 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 37568320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 303534 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 773386336 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.815988 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.066561 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 710969863 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.188905 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.834651 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 100859820 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 341670501 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 226894689 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 36450722 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5094131 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19684552 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2143149 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 625299942 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23465263 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5094131 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 135677386 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 49836875 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 228336608 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 227963533 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 64061330 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 608231586 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 5949574 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 8548374 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 231810 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 263882 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 30185355 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 12581 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 579905224 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 937754781 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 718843517 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 1013139 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 522903039 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 57002179 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15055979 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13152707 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 73956769 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 99026206 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 85770687 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 8763922 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 7686093 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 586686508 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15156086 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 590156830 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2681738 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 50409396 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 34542071 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 266225 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 710969863 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.830073 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.072195 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 429333552 55.51% 55.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 143479671 18.55% 74.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 122471651 15.84% 89.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 69760577 9.02% 98.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8335355 1.08% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5527 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 390297771 54.90% 54.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 132320625 18.61% 73.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 115120103 16.19% 89.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 65333726 9.19% 98.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7893369 1.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 4269 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 773386336 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 710969863 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 65856729 45.73% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 73447 0.05% 45.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 22232 0.02% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 47 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 37876967 26.30% 72.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 40192311 27.91% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 61459839 45.63% 45.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 50531 0.04% 45.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 24866 0.02% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 22 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 34471783 25.59% 71.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 38693635 28.73% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 431505224 68.38% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1606072 0.25% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 80666 0.01% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 12 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 46680 0.01% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 109370672 17.33% 85.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 88464450 14.02% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 403696370 68.40% 68.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1373917 0.23% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 72713 0.01% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 2 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 82685 0.01% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 101222055 17.15% 85.82% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 83709039 14.18% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 631073777 # Type of FU issued -system.cpu0.iq.rate 0.801908 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 144021733 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228217 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2181305203 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 697468177 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 613392938 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1161167 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 463347 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 426941 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 774373560 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 721950 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2923759 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 590156830 # Type of FU issued +system.cpu0.iq.rate 0.815578 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 134700676 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228246 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2027250728 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 651818194 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 574107974 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1415207 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 570288 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 525567 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 723981962 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 875543 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2649036 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13150556 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17424 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 157648 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6172607 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12005066 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 15997 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 137574 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5832630 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2931375 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4759724 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2633268 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 3783846 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5489238 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8266633 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 4717216 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 643560247 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5094131 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6289107 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 4809356 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 601961701 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 106551444 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90697387 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13867290 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 61805 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4582618 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 157648 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2155844 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3101202 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5257046 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 622852330 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 106129153 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7624905 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 99026206 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 85770687 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 12881584 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 63147 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4682481 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 137574 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 1984191 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2898838 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4883029 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 582493668 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 98279194 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7144205 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 126125 # number of nop insts executed -system.cpu0.iew.exec_refs 193235409 # number of memory reference insts executed -system.cpu0.iew.exec_branches 117777762 # Number of branches executed -system.cpu0.iew.exec_stores 87106256 # Number of stores executed -system.cpu0.iew.exec_rate 0.791461 # Inst execution rate -system.cpu0.iew.wb_sent 614619625 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 613819879 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 298670143 # num instructions producing a value -system.cpu0.iew.wb_consumers 489758313 # num instructions consuming a value +system.cpu0.iew.exec_nop 119107 # number of nop insts executed +system.cpu0.iew.exec_refs 180711366 # number of memory reference insts executed +system.cpu0.iew.exec_branches 110157991 # Number of branches executed +system.cpu0.iew.exec_stores 82432172 # Number of stores executed +system.cpu0.iew.exec_rate 0.804987 # Inst execution rate +system.cpu0.iew.wb_sent 575359382 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 574633541 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 278757047 # num instructions producing a value +system.cpu0.iew.wb_consumers 457962623 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.779983 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609832 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.794125 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.608690 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 50622338 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16132116 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4918284 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 763797135 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.766621 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.569865 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 46943290 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14889861 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4575538 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 702085405 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.780670 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.579297 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 508551807 66.58% 66.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 131505056 17.22% 83.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 56862924 7.44% 91.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18814885 2.46% 93.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13980697 1.83% 95.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9342143 1.22% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6309382 0.83% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 4063980 0.53% 98.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14366261 1.88% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 463334360 65.99% 65.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 122538358 17.45% 83.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 53278812 7.59% 91.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18006181 2.56% 93.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13261797 1.89% 95.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 8597155 1.22% 96.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5895517 0.84% 97.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3809437 0.54% 98.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 13363788 1.90% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 763797135 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 498729441 # Number of instructions committed -system.cpu0.commit.committedOps 585543302 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 702085405 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 466411686 # Number of instructions committed +system.cpu0.commit.committedOps 548096953 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 177925668 # Number of memory references committed -system.cpu0.commit.loads 93400888 # Number of loads committed -system.cpu0.commit.membars 4075726 # Number of memory barriers committed -system.cpu0.commit.branches 111746625 # Number of branches committed -system.cpu0.commit.fp_insts 417930 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 537600399 # Number of committed integer instructions. -system.cpu0.commit.function_calls 15117239 # Number of function calls committed. +system.cpu0.commit.refs 166959196 # Number of memory references committed +system.cpu0.commit.loads 87021139 # Number of loads committed +system.cpu0.commit.membars 3711025 # Number of memory barriers committed +system.cpu0.commit.branches 104496556 # Number of branches committed +system.cpu0.commit.fp_insts 513447 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 502627891 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13679873 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 406177320 69.37% 69.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1336444 0.23% 69.60% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 63141 0.01% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 40729 0.01% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 93400888 15.95% 85.56% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 84524780 14.44% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 379865208 69.31% 69.31% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1141082 0.21% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 57492 0.01% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 73933 0.01% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 87021139 15.88% 85.42% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 79938057 14.58% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 585543302 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14366261 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 548096953 # Class of committed instruction +system.cpu0.commit.bw_lim_events 13363788 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 1380974813 # The number of ROB reads -system.cpu0.rob.rob_writes 1281884282 # The number of ROB writes -system.cpu0.timesIdled 846185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 13579146 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93972383800 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 498729441 # Number of Instructions Simulated -system.cpu0.committedOps 585543302 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.577941 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.577941 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.633737 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.633737 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 735405419 # number of integer regfile reads -system.cpu0.int_regfile_writes 437369435 # number of integer regfile writes -system.cpu0.fp_regfile_reads 697220 # number of floating regfile reads -system.cpu0.fp_regfile_writes 340900 # number of floating regfile writes -system.cpu0.cc_regfile_reads 134840784 # number of cc regfile reads -system.cpu0.cc_regfile_writes 135500502 # number of cc regfile writes -system.cpu0.misc_regfile_reads 3071586051 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16203449 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6421778 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.783649 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 165065902 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6422290 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.702032 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 1279505618 # The number of ROB reads +system.cpu0.rob.rob_writes 1198929363 # The number of ROB writes +system.cpu0.timesIdled 780048 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 12636096 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 94120949562 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 466411686 # Number of Instructions Simulated +system.cpu0.committedOps 548096953 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.551432 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.551432 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.644566 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.644566 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 688144011 # number of integer regfile reads +system.cpu0.int_regfile_writes 408577767 # number of integer regfile writes +system.cpu0.fp_regfile_reads 842658 # number of floating regfile reads +system.cpu0.fp_regfile_writes 455584 # number of floating regfile writes +system.cpu0.cc_regfile_reads 127446024 # number of cc regfile reads +system.cpu0.cc_regfile_writes 128164594 # number of cc regfile writes +system.cpu0.misc_regfile_reads 2855519856 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15107964 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 5838402 # number of replacements +system.cpu0.dcache.tags.tagsinuse 504.465464 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155155227 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5838912 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.572626 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.783649 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983952 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.983952 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 369226254 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 369226254 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86280065 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86280065 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73574281 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73574281 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 230862 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 230862 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 1040668 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 1040668 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1948592 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1948592 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1987329 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1987329 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 159854346 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 159854346 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 160085208 # number of overall hits -system.cpu0.dcache.overall_hits::total 160085208 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7331765 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7331765 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7708797 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7708797 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 740087 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 740087 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 294779 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 294779 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 214098 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 214098 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 15040562 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15040562 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15780649 # number of overall misses -system.cpu0.dcache.overall_misses::total 15780649 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 115068880578 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 115068880578 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 135208359707 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 135208359707 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4223400082 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4223400082 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4534810216 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4534810216 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4219500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4219500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 250277240285 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 250277240285 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 250277240285 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 250277240285 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 93611830 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 93611830 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81283078 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81283078 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 970949 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 970949 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1040668 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1040668 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2243371 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2243371 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2201427 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2201427 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 174894908 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 174894908 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 175865857 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 175865857 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078321 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.078321 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.094839 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.094839 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.762231 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.762231 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131400 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131400 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097254 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097254 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085998 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.085998 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089731 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.089731 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15694.567485 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15694.567485 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17539.488938 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17539.488938 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14327.343814 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14327.343814 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21181.002233 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21181.002233 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 504.465464 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.985284 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.985284 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 346167633 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 346167633 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 80535549 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80535549 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69641264 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69641264 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 207056 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 207056 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 203093 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 203093 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877400 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1877400 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1900232 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1900232 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 150176813 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 150176813 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150383869 # number of overall hits +system.cpu0.dcache.overall_hits::total 150383869 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6642832 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6642832 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7191098 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7191098 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 692118 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 692118 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 798159 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 798159 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 243998 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 243998 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 184133 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 184133 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 13833930 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13833930 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 14526048 # number of overall misses +system.cpu0.dcache.overall_misses::total 14526048 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 99514286008 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 99514286008 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 115098035706 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 115098035706 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 53560236062 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 53560236062 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3359260407 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3359260407 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3823760481 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3823760481 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2172500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2172500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 214612321714 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 214612321714 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 214612321714 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 214612321714 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 87178381 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 87178381 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76832362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76832362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899174 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 899174 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1001252 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1001252 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2121398 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2121398 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2084365 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2084365 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 164010743 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 164010743 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 164909917 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 164909917 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076198 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.076198 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.093595 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.093595 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.769726 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.769726 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.797161 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.797161 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.115018 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.115018 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088340 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088340 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084348 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.084348 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088085 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088085 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14980.701907 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14980.701907 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16005.627472 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 16005.627472 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 67104.719814 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 67104.719814 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13767.573533 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13767.573533 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20766.296541 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20766.296541 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16640.152162 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16640.152162 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15859.755849 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15859.755849 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 17082084 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 19003690 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 950552 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 748671 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.970699 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 25.383232 # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 1040668 # number of fast writes performed +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15513.474603 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15513.474603 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14774.309001 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14774.309001 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 16118603 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 16176348 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 692801 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 696412 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.265848 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 23.228129 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3548346 # number of writebacks -system.cpu0.dcache.writebacks::total 3548346 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3808172 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3808172 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6155071 # 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number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 733570 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 143839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 143839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 214091 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 214091 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5055777 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5055777 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5789347 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5789347 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48006705459 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48006705459 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27570008615 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27570008615 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18661725527 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18661725527 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 57519686561 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 57519686561 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1764532424 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1764532424 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4095364784 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4095364784 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4027500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4027500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75576714074 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 75576714074 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94238439601 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 94238439601 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5807383412 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5807383412 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5600359921 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5600359921 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11407743333 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11407743333 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018850 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018850 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.755519 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755519 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064117 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064117 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097251 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097251 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028908 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028908 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032919 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032919 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13624.361684 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13624.361684 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17993.928024 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17993.928024 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25439.597485 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25439.597485 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12267.413038 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12267.413038 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19129.084287 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19129.084287 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3975125 # number of writebacks +system.cpu0.dcache.writebacks::total 3975125 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3497983 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3497983 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5763188 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 5763188 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4492 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4492 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 123982 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 123982 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9261171 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9261171 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9261171 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9261171 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3144849 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3144849 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1427910 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1427910 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 685927 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 685927 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 793667 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 793667 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120016 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120016 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 184129 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 184129 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4572759 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4572759 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5258686 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5258686 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40981205496 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40981205496 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22755476630 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22755476630 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17996613568 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17996613568 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 51855736982 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 51855736982 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1434297417 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1434297417 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3446370519 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3446370519 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2070500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2070500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 63736682126 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 63736682126 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81733295694 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 81733295694 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5581760391 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5581760391 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5277895398 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5277895398 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10859655789 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10859655789 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036074 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036074 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018585 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018585 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762841 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762841 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.792675 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.792675 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056574 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056574 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088338 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088338 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027881 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027881 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031888 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031888 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13031.215647 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13031.215647 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15936.212107 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15936.212107 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26236.922541 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26236.922541 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 65336.894418 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 65336.894418 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11950.885024 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11950.885024 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18717.152209 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18717.152209 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14948.585366 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14948.585366 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16277.904849 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16277.904849 # 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Cycle average of tags in use +system.cpu0.icache.tags.total_refs 208050611 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6043342 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.426417 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 11201042000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.967320 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999936 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999936 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 184 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 467078613 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 467078613 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 223511778 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 223511778 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 223511778 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 223511778 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 223511778 # number of overall hits -system.cpu0.icache.overall_hits::total 223511778 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6775226 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6775226 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6775226 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6775226 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6775226 # number of overall misses -system.cpu0.icache.overall_misses::total 6775226 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 58809305620 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 58809305620 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 58809305620 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 58809305620 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 58809305620 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 58809305620 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 230287004 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 230287004 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 230287004 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 230287004 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 230287004 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 230287004 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029421 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029421 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029421 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029421 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029421 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029421 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8680.050764 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8680.050764 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8680.050764 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8680.050764 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8680.050764 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8680.050764 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4711788 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 167 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 607280 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 434737408 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 434737408 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 208050611 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 208050611 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 208050611 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 208050611 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 208050611 # number of overall hits +system.cpu0.icache.overall_hits::total 208050611 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6296413 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6296413 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6296413 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6296413 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6296413 # number of overall misses +system.cpu0.icache.overall_misses::total 6296413 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55127710497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 55127710497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 55127710497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 55127710497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 55127710497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 55127710497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 214347024 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 214347024 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 214347024 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 214347024 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 214347024 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 214347024 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029375 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029375 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029375 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029375 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029375 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029375 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8755.415265 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8755.415265 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8755.415265 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8755.415265 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4477144 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 62 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 570538 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.758839 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 167 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.847232 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 62 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 270621 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 270621 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 270621 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 270621 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 270621 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 270621 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6504605 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6504605 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6504605 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6504605 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6504605 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6504605 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 47647231055 # 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number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6043360 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6043360 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6043360 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6043360 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6043360 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6043360 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 44707631164 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 44707631164 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 44707631164 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 44707631164 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 44707631164 # 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mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028194 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028194 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7397.810351 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 59245032 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2351166 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 52469358 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1249562 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 60184765 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4393414 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 48808124 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3087530 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 200789 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2974157 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4925432 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 452633 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3443064 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 5114963 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 3747306 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16276.136731 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 13593053 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3763332 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.611973 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 6997709500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4266.822439 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 59.073583 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 61.998615 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 875.814301 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3003.067946 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8009.359846 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.260426 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003606 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003784 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.053455 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.183293 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.488853 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.993417 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8909 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 95 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7022 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 203 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 252 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3635 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3246 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1573 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 72 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 759 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2892 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2491 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 768 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.543762 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005798 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.428589 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 294843936 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 294843936 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 600493 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 179726 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 6257574 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 3196043 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 10233836 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3548335 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3548335 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 119384 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 119384 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 38955 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 38955 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 985595 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 985595 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 600493 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 179726 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 6257574 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4181638 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 11219431 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 600493 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 179726 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 6257574 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4181638 # number of overall hits -system.cpu0.l2cache.overall_hits::total 11219431 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 16370 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12947 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 246684 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1202213 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1478214 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 9 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 9 # number of Writeback misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 131869 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 131869 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 175118 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 175118 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 18 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 18 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 304338 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 304338 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 16370 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12947 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 246684 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1506551 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1782552 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 16370 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12947 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 246684 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1506551 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1782552 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 782711292 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 885174343 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 6713721698 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 44470699734 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 52852307067 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2670586208 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2670586208 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3556484886 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3556484886 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3931499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3931499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15577643529 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 15577643529 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 782711292 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 885174343 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 6713721698 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 60048343263 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 68429950596 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 782711292 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 885174343 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 6713721698 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 60048343263 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 68429950596 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 616863 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 192673 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6504258 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4398256 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 11712050 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3548344 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3548344 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 251253 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 251253 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 214073 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 214073 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 18 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 18 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1289933 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1289933 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 616863 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 192673 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 6504258 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5688189 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 13001983 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 616863 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 192673 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 6504258 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5688189 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 13001983 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026537 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.067197 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037927 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.273339 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.126213 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000003 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000003 # miss rate for Writeback accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.524845 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.524845 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.818029 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.818029 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.replacements 4158550 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16214.275256 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 12594287 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 4174696 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.016815 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 9944532000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 3315.303513 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 38.862270 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.140550 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 967.067959 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2910.372119 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8960.528846 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.202350 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002372 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001351 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.059025 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.177635 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.546907 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989641 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8340 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7728 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 111 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 951 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3646 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 2631 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1001 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 51 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1103 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3816 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2122 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 566 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.509033 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.471680 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 280330704 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 280330704 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522125 # 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mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.251089 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.185504 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.185504 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128447 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.354862 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 30124.578689 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29676.550699 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 35601.440437 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.943421 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17421.943421 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13837.367604 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13837.367604 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 181083.277778 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 181083.277778 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40961.276755 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40961.276755 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32082.226080 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31451.797521 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32082.226080 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34126.366499 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.417806 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27642.980057 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27083.574890 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55593.563487 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32521.484628 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32521.484628 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17427.856472 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17427.856472 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13830.282341 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13830.282341 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 237500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 237500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 33377.085578 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 33377.085578 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27996.319261 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47109.300568 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1419,69 +1471,69 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 15637085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 12009481 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33046 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33046 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3548344 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 4365503 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1683195 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 1040668 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 461767 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 386684 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 535373 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1436156 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1297014 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 13051451 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18246800 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419537 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1341455 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 33059243 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 416613216 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 664873226 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1541384 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4934904 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1087962730 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 9586812 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 27467610 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.337349 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.472805 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 15173335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11005084 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31316 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31316 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3975122 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 5222365 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 963549 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 792291 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 491639 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 333223 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 494297 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1332515 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1202467 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12129286 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16997895 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390025 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1185916 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 30703122 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 387114336 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641181457 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1414144 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4287888 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1033997825 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 10518238 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 27441081 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.371527 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.483213 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 18201451 66.27% 66.27% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 9266159 33.73% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 17245975 62.85% 62.85% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 10195106 37.15% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 27467610 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 13754094390 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 27441081 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 13452656135 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 197445482 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 192867736 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9792438220 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9099601288 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9396795912 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8421572630 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 228193109 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 213967447 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 726243001 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 651243914 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 126883394 # Number of BP lookups -system.cpu1.branchPred.condPredicted 85166335 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6223569 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 90014178 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 58475937 # Number of BTB hits +system.cpu1.branchPred.lookups 133961841 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89061347 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6618163 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 94585757 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 62217505 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 64.963029 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16774062 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 171946 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.778936 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 18340774 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 186545 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1505,25 +1557,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 93423769 # DTB read hits -system.cpu1.dtb.read_misses 385141 # DTB read misses -system.cpu1.dtb.write_hits 77506370 # DTB write hits -system.cpu1.dtb.write_misses 166753 # DTB write misses -system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 98830623 # DTB read hits +system.cpu1.dtb.read_misses 443426 # DTB read misses +system.cpu1.dtb.write_hits 80619639 # DTB write hits +system.cpu1.dtb.write_misses 165440 # DTB write misses +system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 38053 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 411 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6413 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 44150 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 612 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6848 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 42956 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 93808910 # DTB read accesses -system.cpu1.dtb.write_accesses 77673123 # DTB write accesses +system.cpu1.dtb.perms_faults 42554 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 99274049 # DTB read accesses +system.cpu1.dtb.write_accesses 80785079 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 170930139 # DTB hits -system.cpu1.dtb.misses 551894 # DTB misses -system.cpu1.dtb.accesses 171482033 # DTB accesses +system.cpu1.dtb.hits 179450262 # DTB hits +system.cpu1.dtb.misses 608866 # DTB misses +system.cpu1.dtb.accesses 180059128 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1545,519 +1597,533 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 200532583 # ITB inst hits -system.cpu1.itb.inst_misses 85074 # ITB inst misses +system.cpu1.itb.inst_hits 211899162 # ITB inst hits +system.cpu1.itb.inst_misses 88988 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26827 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 32114 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 221691 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 230833 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 200617657 # ITB inst accesses -system.cpu1.itb.hits 200532583 # DTB hits -system.cpu1.itb.misses 85074 # DTB misses -system.cpu1.itb.accesses 200617657 # DTB accesses -system.cpu1.numCycles 671498045 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 211988150 # ITB inst accesses +system.cpu1.itb.hits 211899162 # DTB hits +system.cpu1.itb.misses 88988 # DTB misses +system.cpu1.itb.accesses 211988150 # DTB accesses +system.cpu1.numCycles 705261968 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 76057268 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 563958948 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 126883394 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 75249999 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 570112426 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13401984 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1796129 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 140886 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6366912 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 711415 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 284551 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 200289545 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1511940 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 28568 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 662170579 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.001134 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.225253 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 81258744 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 595261780 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 133961841 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 80558279 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 597026773 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 14270848 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1888771 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 137791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6543938 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 793820 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 311963 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 211646234 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1619349 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28847 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 695097224 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.005850 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.225976 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 344731960 52.06% 52.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 123888404 18.71% 70.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 41617512 6.29% 77.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 151932703 22.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 360486788 51.86% 51.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 129920524 18.69% 70.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 44826389 6.45% 77.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 159863523 23.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 662170579 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.188956 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.839852 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 93652150 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 319101856 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 208055943 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 36600277 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4760353 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17735520 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1981049 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 585316730 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21686226 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4760353 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 127273008 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 44978505 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 215016897 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 210494675 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 59647141 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 569572737 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5483527 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8310630 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 236317 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 296206 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 25698514 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 13591 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 543172602 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 884661173 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 673765883 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 933137 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 489609146 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 53563450 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15680851 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13859127 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 73666324 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 93680638 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 80687792 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8658535 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7660349 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 547737456 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15869030 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 553093233 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2542275 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 47705580 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 32628806 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 263861 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 662170579 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.835273 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.067651 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 695097224 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.189946 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.844029 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 99752260 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 332349824 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 219841712 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 38085588 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5067840 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 18995502 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2109796 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 616514692 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22877728 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5067840 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 135033848 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 48639647 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 225189127 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 222148294 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 59018468 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 599774214 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5804898 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8803158 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 361913 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 923044 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 23085631 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 14113 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 571116000 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 927515458 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 708750961 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 721490 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 514023695 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 57092304 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 16265387 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 14239236 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 76589893 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 99537313 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 83963206 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 9607701 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 8257946 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 576970515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 16478044 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 581773999 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2685793 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 50643585 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 34938077 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 295595 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 695097224 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.836968 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.068825 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 358036858 54.07% 54.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 130663379 19.73% 73.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 105371554 15.91% 89.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 60712008 9.17% 98.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7383178 1.11% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 3602 0.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 375720628 54.05% 54.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 136500819 19.64% 73.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 111041420 15.97% 89.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 64151608 9.23% 98.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7678235 1.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4508 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 6 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 662170579 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 695097224 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 55137578 43.73% 43.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 43337 0.03% 43.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 11462 0.01% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 21 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 33948572 26.92% 70.70% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 36949037 29.30% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 58467261 44.14% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 65736 0.05% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 8975 0.01% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 28 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 36077917 27.24% 71.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 37847209 28.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 376818141 68.13% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1181294 0.21% 68.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 70304 0.01% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 78003 0.01% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 96248927 17.40% 85.77% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 78696516 14.23% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 396486231 68.15% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1392625 0.24% 68.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 78812 0.01% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 42928 0.01% 68.41% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 101899765 17.52% 85.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 81873638 14.07% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 553093233 # Type of FU issued -system.cpu1.iq.rate 0.823671 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 126090007 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227972 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1895671563 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 610922154 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 537423673 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1317762 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 530370 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 489519 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 678367586 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 815653 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2464833 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 581773999 # Type of FU issued +system.cpu1.iq.rate 0.824905 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 132467126 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227695 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1992741902 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 643831652 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 565540483 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1056239 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 418449 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 388115 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 713583395 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 657730 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2682619 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11666973 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 15967 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 141534 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5620813 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 12570649 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16823 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 158978 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5834378 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2485085 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4066782 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2724944 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3729174 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4760353 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6088373 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2643428 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 563729528 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 5067840 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 8144414 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2028582 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 593577386 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 93680638 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 80687792 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13644540 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 61293 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2520664 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 141534 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1916152 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2651693 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4567845 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 545961284 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 93419699 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6590982 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 99537313 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 83963206 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 14010879 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 57965 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1901764 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 158978 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2040667 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2820650 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4861317 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 574179310 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 98827451 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6993764 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 123042 # number of nop insts executed -system.cpu1.iew.exec_refs 170926883 # number of memory reference insts executed -system.cpu1.iew.exec_branches 102016204 # Number of branches executed -system.cpu1.iew.exec_stores 77507184 # Number of stores executed -system.cpu1.iew.exec_rate 0.813050 # Inst execution rate -system.cpu1.iew.wb_sent 538581721 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 537913192 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 259879872 # num instructions producing a value -system.cpu1.iew.wb_consumers 425846883 # num instructions consuming a value +system.cpu1.iew.exec_nop 128827 # number of nop insts executed +system.cpu1.iew.exec_refs 179445358 # number of memory reference insts executed +system.cpu1.iew.exec_branches 107524158 # Number of branches executed +system.cpu1.iew.exec_stores 80617907 # Number of stores executed +system.cpu1.iew.exec_rate 0.814136 # Inst execution rate +system.cpu1.iew.wb_sent 566651750 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 565928598 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 274900610 # num instructions producing a value +system.cpu1.iew.wb_consumers 450009146 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.801064 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610266 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.802437 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610878 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 44555907 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15605169 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4282930 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 653744993 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.784392 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.576833 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 47337627 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 16182449 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4550579 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 686146419 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.786229 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.582193 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 427404365 65.38% 65.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 119117281 18.22% 83.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 49133324 7.52% 91.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16524443 2.53% 93.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11998035 1.84% 95.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8093886 1.24% 96.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5471403 0.84% 97.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3473274 0.53% 98.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12528982 1.92% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 448874592 65.42% 65.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 124520992 18.15% 83.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 51724584 7.54% 91.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 17115210 2.49% 93.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12441515 1.81% 95.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8692682 1.27% 96.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5812900 0.85% 97.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3666336 0.53% 98.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 13297608 1.94% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 653744993 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 435068948 # Number of instructions committed -system.cpu1.commit.committedOps 512792020 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 686146419 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 458333534 # Number of instructions committed +system.cpu1.commit.committedOps 539467876 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 157080643 # Number of memory references committed -system.cpu1.commit.loads 82013664 # Number of loads committed -system.cpu1.commit.membars 3580423 # Number of memory barriers committed -system.cpu1.commit.branches 96770677 # Number of branches committed -system.cpu1.commit.fp_insts 477739 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 470356347 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12430117 # Number of function calls committed. +system.cpu1.commit.refs 165095491 # Number of memory references committed +system.cpu1.commit.loads 86966664 # Number of loads committed +system.cpu1.commit.membars 3858042 # Number of memory barriers committed +system.cpu1.commit.branches 101991370 # Number of branches committed +system.cpu1.commit.fp_insts 379596 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 495494093 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13607824 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 354618766 69.15% 69.15% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 966577 0.19% 69.34% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 56200 0.01% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 69792 0.01% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 82013664 15.99% 85.36% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 75066979 14.64% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 373132612 69.17% 69.17% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1140635 0.21% 69.38% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 62088 0.01% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 37050 0.01% 69.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.40% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 86966664 16.12% 85.52% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 78128827 14.48% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 512792020 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12528982 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 539467876 # Class of committed instruction +system.cpu1.commit.bw_lim_events 13297608 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 1194813735 # The number of ROB reads -system.cpu1.rob.rob_writes 1123082959 # The number of ROB writes -system.cpu1.timesIdled 724798 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 9327466 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94087851225 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 435068948 # Number of Instructions Simulated -system.cpu1.committedOps 512792020 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.543429 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.543429 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.647908 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.647908 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 645605353 # number of integer regfile reads -system.cpu1.int_regfile_writes 381721004 # number of integer regfile writes -system.cpu1.fp_regfile_reads 775313 # number of floating regfile reads -system.cpu1.fp_regfile_writes 445860 # number of floating regfile writes -system.cpu1.cc_regfile_reads 118711593 # number of cc regfile reads -system.cpu1.cc_regfile_writes 119446570 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2680324661 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15740060 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5270583 # number of replacements -system.cpu1.dcache.tags.tagsinuse 418.735038 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 145844611 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5271093 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.668761 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8472891797000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 418.735038 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.817842 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.817842 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 326008687 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 326008687 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 76031229 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76031229 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 65289331 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 65289331 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171825 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 171825 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 535551 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 535551 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1744878 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1744878 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734724 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1734724 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 141320560 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 141320560 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 141492385 # number of overall hits -system.cpu1.dcache.overall_hits::total 141492385 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6360074 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6360074 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7315323 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7315323 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 690767 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 690767 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 239985 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 239985 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 206300 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 206300 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13675397 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13675397 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14366164 # number of overall misses -system.cpu1.dcache.overall_misses::total 14366164 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96502365280 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 96502365280 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 122289774326 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 122289774326 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3384586861 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3384586861 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4391846948 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4391846948 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4067000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4067000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 218792139606 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 218792139606 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 218792139606 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 218792139606 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82391303 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82391303 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72604654 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72604654 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 862592 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 862592 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 535551 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 535551 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1984863 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1984863 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1941024 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1941024 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 154995957 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 154995957 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 155858549 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 155858549 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077194 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.077194 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.100756 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.100756 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.800804 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.800804 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120908 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120908 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106284 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106284 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088231 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.088231 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092174 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.092174 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15173.151331 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15173.151331 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16716.934348 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16716.934348 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14103.326712 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14103.326712 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21288.642501 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21288.642501 # average StoreCondReq miss latency +system.cpu1.rob.rob_reads 1255653176 # The number of ROB reads +system.cpu1.rob.rob_writes 1182522736 # The number of ROB writes +system.cpu1.timesIdled 784634 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 10164744 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94139293558 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 458333534 # Number of Instructions Simulated +system.cpu1.committedOps 539467876 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.538753 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.538753 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.649877 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.649877 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 678371688 # number of integer regfile reads +system.cpu1.int_regfile_writes 402814905 # number of integer regfile writes +system.cpu1.fp_regfile_reads 627803 # number of floating regfile reads +system.cpu1.fp_regfile_writes 323588 # number of floating regfile writes +system.cpu1.cc_regfile_reads 123299886 # number of cc regfile reads +system.cpu1.cc_regfile_writes 123979632 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2817640596 # number of misc regfile reads +system.cpu1.misc_regfile_writes 16155257 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5719154 # number of replacements +system.cpu1.dcache.tags.tagsinuse 428.720007 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 153241322 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5719665 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 26.792010 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8515430590500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.720007 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837344 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.837344 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 342874086 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 342874086 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 80584085 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 80584085 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68058878 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68058878 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187635 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 187635 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 112453 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 112453 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1764554 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1764554 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1816897 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1816897 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 148642963 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 148642963 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 148830598 # number of overall hits +system.cpu1.dcache.overall_hits::total 148830598 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6869643 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6869643 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7494314 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7494314 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 706318 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 706318 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 458418 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 458418 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 288948 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 288948 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 190861 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 190861 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 14363957 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 14363957 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 15070275 # number of overall misses +system.cpu1.dcache.overall_misses::total 15070275 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 105402463849 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 105402463849 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 121649241613 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 121649241613 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 17403154350 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 17403154350 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4078869410 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 4078869410 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3937390159 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3937390159 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1956500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1956500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 227051705462 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 227051705462 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 227051705462 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 227051705462 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 87453728 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 87453728 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 75553192 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 75553192 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 893953 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 893953 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 570871 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 570871 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2053502 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2053502 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2007758 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2007758 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 163006920 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 163006920 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 163900873 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 163900873 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078552 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.078552 # 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miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.088119 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.091947 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.091947 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.222908 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.222908 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16232.205057 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16232.205057 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 37963.505687 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 37963.505687 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14116.274935 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14116.274935 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20629.621342 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20629.621342 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15998.960733 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15998.960733 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15229.684111 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15229.684111 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 8615413 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 17976416 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 462301 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 741969 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.635938 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 24.227988 # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 535551 # number of fast writes performed +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15807.044358 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15807.044358 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15066.195239 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15066.195239 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4622048 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18188306 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 368036 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 754235 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.558684 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 24.114906 # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3043634 # number of writebacks -system.cpu1.dcache.writebacks::total 3043634 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3366977 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3366977 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5934775 # 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number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23265516814 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23265516814 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16955467787 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16955467787 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 29882890933 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 29882890933 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1431846930 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1431846930 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3970245052 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3970245052 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3877000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3877000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62205669818 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 62205669818 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79161137605 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 79161137605 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 568928684 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 568928684 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 634602446 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 634602446 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1203531130 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1203531130 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036328 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036328 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018866 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018866 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800716 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800716 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058506 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058506 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106278 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106278 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028148 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028148 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032424 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032424 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13009.986981 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13009.986981 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16984.682963 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16984.682963 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24548.557585 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24548.557585 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.008783 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.008783 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.127026 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.127026 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3658567 # number of writebacks +system.cpu1.dcache.writebacks::total 3658567 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3579229 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3579229 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6058526 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 6058526 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3270 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3270 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 146042 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 146042 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9637755 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9637755 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9637755 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9637755 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3290414 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3290414 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1435788 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1435788 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 706224 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 706224 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 455148 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 455148 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 142906 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 142906 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 190858 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 190858 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4726202 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4726202 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5432426 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5432426 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44800014998 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44800014998 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23381887855 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23381887855 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16359112476 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16359112476 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 16414544257 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 16414544257 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1722097666 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1722097666 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3546227841 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3546227841 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1864500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1864500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68181902853 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 68181902853 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84541015329 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 84541015329 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 790979694 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 790979694 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 944680456 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 944680456 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1735660150 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1735660150 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037625 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037625 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019004 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019004 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790001 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790001 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.797287 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.797287 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069591 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069591 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095060 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095060 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028994 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028994 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033145 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033145 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13615.312541 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13615.312541 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16285.055910 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16285.055910 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23164.197869 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23164.197869 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 36064.190674 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 36064.190674 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12050.562370 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12050.562370 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18580.451650 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18580.451650 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14257.901428 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14257.901428 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15664.361953 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15664.361953 # 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Cycle average of tags in use +system.cpu1.icache.tags.total_refs 205507195 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5882198 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 34.937143 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8555135625500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.904324 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980282 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980282 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 371 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 406089111 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 406089111 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 194540892 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 194540892 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 194540892 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 194540892 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 194540892 # number of overall hits -system.cpu1.icache.overall_hits::total 194540892 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5745874 # 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number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 200286766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 200286766 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 200286766 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 200286766 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 200286766 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028688 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.028688 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028688 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.028688 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028688 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.028688 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8697.148756 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8697.148756 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8697.148756 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8697.148756 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 4058036 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 429168724 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 429168724 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 205507195 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 205507195 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 205507195 # 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miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028992 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.028992 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028992 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.028992 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8782.415946 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8782.415946 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8782.415946 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8782.415946 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8782.415946 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8782.415946 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 4496430 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 525950 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 574651 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.715631 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.824627 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 230295 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 230295 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 230295 # 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number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 40507461081 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 40507461081 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 40507461081 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 40507461081 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6176248 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6176248 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6176248 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6176248 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027538 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027538 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027538 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7344.190171 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7344.190171 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7344.190171 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 253840 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 253840 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 253840 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 253840 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 253840 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 253840 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5882218 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5882218 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5882218 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5882218 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5882218 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5882218 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 43727434357 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 43727434357 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 43727434357 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 43727434357 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 43727434357 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 43727434357 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6637997 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6637997 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6637997 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6637997 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027793 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027793 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027793 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7433.834373 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7433.834373 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7433.834373 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 50505684 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2064047 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 44628493 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 907161 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 56932742 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2823095 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 47812216 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2677811 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 133845 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2772138 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4283124 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 382726 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 3236886 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4916498 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 3436745 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13730.844001 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 11600969 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 3452900 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 3.359776 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9794240275500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4681.996556 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.505551 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 81.585621 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 599.676687 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2582.188700 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5714.890886 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.285766 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004303 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004980 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036601 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.157604 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.348809 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.838064 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9001 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7069 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 110 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 838 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3805 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2947 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1301 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 61 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 786 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3475 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2116 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 647 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.549377 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.431458 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 248779915 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 248779915 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 532626 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 172045 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5284751 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2703668 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 8693090 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3043623 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3043623 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 90999 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 90999 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33582 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 33582 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 896481 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 896481 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 532626 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 172045 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5284751 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3600149 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9589571 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 532626 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 172045 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5284751 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3600149 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9589571 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 15803 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 12743 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 230826 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1092537 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1351909 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 10 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 10 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 129352 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 129352 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 172689 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 172689 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 17 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 17 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 259572 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 259572 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 15803 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 12743 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 230826 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1352109 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1611481 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 15803 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 12743 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 230826 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1352109 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1611481 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 757783063 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 830879579 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 5925678894 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 36970844217 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 44485185753 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2628732175 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2628732175 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3477493272 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3477493272 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3782000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3782000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12238175338 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 12238175338 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 757783063 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 830879579 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 5925678894 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 49209019555 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 56723361091 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 757783063 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 830879579 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 5925678894 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 49209019555 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 56723361091 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 548429 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 184788 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5515577 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3796205 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 10044999 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3043633 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3043633 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 220351 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 220351 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 206271 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 206271 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 17 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 17 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1156053 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1156053 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 548429 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 184788 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5515577 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4952258 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 11201052 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 548429 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 184788 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5515577 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4952258 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 11201052 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028815 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.068960 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.041850 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.287797 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.134585 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000003 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000003 # miss rate for Writeback accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.587027 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.587027 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.837195 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.837195 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.replacements 4092617 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13780.930785 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 12621619 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 4108487 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 3.072084 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9637211064000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 3757.362843 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.809020 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 56.863279 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 599.057552 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3491.075179 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5813.762913 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.229331 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003834 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003471 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036564 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.213078 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.354844 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.841121 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8933 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6853 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 68 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 777 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3625 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2921 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1542 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3137 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2007 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 750 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.545227 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.418274 # 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mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030928 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.265165 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.180399 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.180399 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132931 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.382456 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26775.298889 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26588.275709 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 32053.702935 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17563.550939 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17563.550939 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13637.442900 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13637.442900 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183352.941176 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183352.941176 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36902.824973 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36902.824973 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28138.464180 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30671.695797 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.401623 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27705.527306 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27112.291240 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36830.440224 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31073.249872 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31073.249872 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17075.365387 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17075.365387 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13826.798875 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13826.798875 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213785.714286 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213785.714286 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33235.203246 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33235.203246 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27951.592092 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33891.685533 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2514,66 +2598,66 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 14195138 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10319504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5540 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5540 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3043633 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 4072942 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1683351 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 535551 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 440112 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 381311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 495883 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1326326 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1162072 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11031290 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15072798 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 408972 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1223990 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27737050 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352998000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 552975725 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1478304 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4387432 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 911839461 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 10107713 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 25138246 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.388398 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.487386 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 15325840 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 11081361 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 7210 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7210 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3658566 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 4807205 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 18 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 637593 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 454086 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 471082 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 336358 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 477965 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1352070 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1222067 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11764566 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16293479 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 431287 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1341589 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 29830921 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 376462768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 612089908 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1574800 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4897784 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 995025260 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 10166385 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 26584709 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.370632 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.482974 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15374612 61.16% 61.16% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 9763634 38.84% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 16731578 62.94% 62.94% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 9853131 37.06% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 25138246 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11278575992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 26584709 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12493291014 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 196968741 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 175961487 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8281966249 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8832336643 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7967439656 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8528127192 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 225433169 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 235484276 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 677266087 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 730977975 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40417 # Transaction distribution -system.iobus.trans_dist::ReadResp 40417 # Transaction distribution -system.iobus.trans_dist::WriteReq 136643 # Transaction distribution -system.iobus.trans_dist::WriteResp 136782 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 139 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40396 # Transaction distribution +system.iobus.trans_dist::ReadResp 40396 # Transaction distribution +system.iobus.trans_dist::WriteReq 136775 # Transaction distribution +system.iobus.trans_dist::WriteResp 30047 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2588,13 +2672,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354398 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48148 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2609,13 +2693,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156169 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497071 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36581000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2643,678 +2727,710 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 982013630 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1043032876 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93018000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179230570 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179190812 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115615 # number of replacements -system.iocache.tags.tagsinuse 11.386738 # Cycle average of tags in use +system.iocache.tags.replacements 115581 # number of replacements +system.iocache.tags.tagsinuse 11.295325 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115597 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9111214571000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.838966 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.547771 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239935 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.471736 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.711671 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9153631711000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.835501 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.459825 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239719 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466239 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705958 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042022 # Number of tag accesses -system.iocache.tags.data_accesses 1042022 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1040757 # Number of tag accesses +system.iocache.tags.data_accesses 1040757 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 139 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 139 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8889 # number of demand (read+write) misses -system.iocache.demand_misses::total 8929 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8872 # number of demand (read+write) misses +system.iocache.demand_misses::total 8912 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8889 # number of overall misses -system.iocache.overall_misses::total 8929 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5695000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1981823591 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1987518591 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8872 # number of overall misses +system.iocache.overall_misses::total 8912 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1960529318 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1966236318 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 365000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 365000 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6060000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1981823591 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1987883591 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6060000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1981823591 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1987883591 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28841569746 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28841569746 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6072000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1960529318 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1966601318 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6072000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1960529318 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1966601318 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106867 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106867 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8889 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8929 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8872 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8912 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8889 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8929 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8872 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8912 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001301 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.001301 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 153918.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 222952.367083 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 222666.210060 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 220979.409152 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 220702.246941 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 121666.666667 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 121666.666667 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 222952.367083 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 222632.275843 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 222952.367083 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 222632.275843 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55347 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270234.331628 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270234.331628 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151800 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 220668.909111 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151800 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 220668.909111 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 224453 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27297 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.081421 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.222625 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106728 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8872 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8909 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8889 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8929 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8872 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8912 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8889 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8929 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3771000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1519438621 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1523209621 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8872 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8912 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1499010380 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1502793380 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 209000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 209000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6630698579 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6630698579 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3980000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1519438621 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1523418621 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3980000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1519438621 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1523418621 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23291152308 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23291152308 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3992000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1499010380 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1503002380 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3992000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1499010380 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1503002380 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 101918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170934.708179 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 170648.624356 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168959.691163 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 168682.610843 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.071172 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.071172 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1387044 # number of replacements -system.l2c.tags.tagsinuse 64427.808632 # Cycle average of tags in use -system.l2c.tags.total_refs 7620997 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1449367 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.258155 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 10003.170740 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 188.441651 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 243.424548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 921.507825 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8419.959281 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24297.060802 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 189.151688 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 259.454485 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 442.813505 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5057.928398 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14404.895708 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.152636 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003714 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.014061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.128478 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370744 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002886 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003959 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.006757 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.077178 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.219801 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983090 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 33631 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 302 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 28390 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 18 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 86 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 2393 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1787 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29347 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 216 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2265 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4264 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 21604 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.513168 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004608 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.433197 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 91165244 # Number of tag accesses -system.l2c.tags.data_accesses 91165244 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 7553 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4301 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 170694 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 696092 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1825935 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 8223 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5157 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 162945 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 691200 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1816536 # number of ReadReq hits -system.l2c.ReadReq_hits::total 5388636 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2284318 # number of Writeback hits -system.l2c.Writeback_hits::total 2284318 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 28567 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 31425 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 59992 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 8944 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7440 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16384 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 53362 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53750 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107112 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 7553 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4301 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 170694 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 749454 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 1825935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 8223 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5157 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 162945 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 744950 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1816536 # number of demand (read+write) hits -system.l2c.demand_hits::total 5495748 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 7553 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4301 # number of overall hits -system.l2c.overall_hits::cpu0.inst 170694 # number of overall hits -system.l2c.overall_hits::cpu0.data 749454 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 1825935 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 8223 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5157 # number of overall hits -system.l2c.overall_hits::cpu1.inst 162945 # number of overall hits -system.l2c.overall_hits::cpu1.data 744950 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 1816536 # number of overall hits -system.l2c.overall_hits::total 5495748 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5517 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 8182 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 12718 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 197063 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 598730 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 5285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 7231 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 8328 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 136549 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 456002 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1435605 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 38751 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 39177 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 77928 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 11922 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 9604 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 21526 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 91592 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 67962 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 159554 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 5517 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 8182 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 12718 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 288655 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 598730 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 5285 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 7231 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 8328 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 204511 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 456002 # number of demand (read+write) misses -system.l2c.demand_misses::total 1595159 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 5517 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 8182 # number of overall misses -system.l2c.overall_misses::cpu0.inst 12718 # number of overall misses -system.l2c.overall_misses::cpu0.data 288655 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 598730 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 5285 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 7231 # number of overall misses -system.l2c.overall_misses::cpu1.inst 8328 # number of overall misses -system.l2c.overall_misses::cpu1.data 204511 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 456002 # number of overall misses -system.l2c.overall_misses::total 1595159 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 458859494 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 660185236 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1228334988 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 18297393453 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 440607992 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 598540979 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 788794491 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 12800911061 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 163963230205 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 163981726 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 172729371 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 336711097 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 59985022 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 52908784 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 112893806 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7434747873 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5448950117 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12883697990 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 458859494 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 660185236 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1228334988 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 25732141326 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 440607992 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 598540979 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 788794491 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 18249861178 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 176846928195 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 458859494 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 660185236 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1228334988 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 25732141326 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 440607992 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 598540979 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 788794491 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 18249861178 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of overall miss cycles -system.l2c.overall_miss_latency::total 176846928195 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 13070 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 12483 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 183412 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 893155 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2424665 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 13508 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 12388 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 171273 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 827749 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2272538 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 6824241 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2284318 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2284318 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 67318 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 70602 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 137920 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 20866 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 17044 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 37910 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 144954 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 121712 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 266666 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 13070 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 12483 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 183412 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1038109 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2424665 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 13508 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 12388 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 171273 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 949461 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2272538 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 7090907 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 13070 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 12483 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 183412 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1038109 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2424665 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 13508 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 12388 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 171273 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 949461 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2272538 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 7090907 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.422112 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.655451 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.069341 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.220637 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.246933 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.391250 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.583710 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.048624 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.164964 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.200658 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.210368 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.575641 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.554899 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.565023 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.571360 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.563483 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.567819 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.631869 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.558384 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.598329 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.422112 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.655451 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.069341 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.278058 # 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average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 94715.957133 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 89236.574942 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 110864.765327 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 23951 # number of cycles access was blocked +system.l2c.tags.replacements 1916125 # number of replacements +system.l2c.tags.tagsinuse 64884.880884 # Cycle average of tags in use +system.l2c.tags.total_refs 8755676 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1978999 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.424295 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 3437261500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 8337.656958 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.346754 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 14.129416 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 627.039592 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3445.654069 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15412.309931 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 351.392171 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 435.207962 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 621.389971 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11403.863316 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 24218.890744 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.127223 # 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Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 38428 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 201 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 24245 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 143 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 2926 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6291 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29058 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 187 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1447 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2670 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 19923 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.586365 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003067 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.369949 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 93004482 # Number of tag accesses +system.l2c.tags.data_accesses 93004482 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9030 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6306 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 171973 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 713080 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1991967 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 8819 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.215360 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.224847 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.278016 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.215360 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.224847 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80451.468412 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 81359.470904 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 101975.362824 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10304.809373 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10376.553947 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10340.877759 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10367.861265 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10379.670762 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10373.130168 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68715.351155 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67723.577249 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 68292.905223 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9253526493 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4753250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1380792752 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11742279495 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.175477 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.171245 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.068189 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.168066 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.299552 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.307173 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.394840 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.053766 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.181431 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.206057 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.226536 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.384707 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.291075 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.341951 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.524241 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.552613 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.537838 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.553898 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.558488 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.556222 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.464945 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.475672 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.470280 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.175477 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.171245 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.068189 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.202855 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.299552 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.307173 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.394840 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.214002 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.206057 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.233479 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.175477 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.171245 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.068189 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.202855 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.299552 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.307173 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.394840 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.214002 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.206057 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.233479 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 83613.975559 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78300.094379 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 138960.075245 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 26965.564241 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27931.878814 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 27341.166584 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10302.647357 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.691394 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10275.094224 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10301.097202 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10284.711472 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10292.768070 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71179.305627 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69289.702936 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70228.797041 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80274.212183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76083.115009 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 135016.780662 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80274.212183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76083.115009 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 135016.780662 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3329,57 +3445,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1503713 # Transaction distribution -system.membus.trans_dist::ReadResp 1503713 # Transaction distribution -system.membus.trans_dist::WriteReq 38586 # Transaction distribution -system.membus.trans_dist::WriteResp 38586 # Transaction distribution -system.membus.trans_dist::Writeback 882638 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1682947 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1682947 # Transaction distribution -system.membus.trans_dist::UpgradeReq 373970 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 331267 # Transaction distribution -system.membus.trans_dist::UpgradeResp 103150 # Transaction distribution -system.membus.trans_dist::ReadExReq 170539 # Transaction distribution -system.membus.trans_dist::ReadExResp 155861 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123084 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1817706 # Transaction distribution +system.membus.trans_dist::ReadResp 1817706 # Transaction distribution +system.membus.trans_dist::WriteReq 38526 # Transaction distribution +system.membus.trans_dist::WriteResp 38526 # Transaction distribution +system.membus.trans_dist::Writeback 1444194 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 154200 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 154200 # Transaction distribution +system.membus.trans_dist::UpgradeReq 434662 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 279066 # Transaction distribution +system.membus.trans_dist::UpgradeResp 97607 # Transaction distribution +system.membus.trans_dist::ReadExReq 117028 # Transaction distribution +system.membus.trans_dist::ReadExResp 102726 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123062 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26002 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 8087433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 8236597 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 229762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 8466359 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156191 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6008493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6157429 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336112 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336112 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6493541 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156169 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52004 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 259532552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 259741319 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7302720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 267044039 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 618323 # Total snoops (count) -system.membus.snoop_fanout::samples 4885385 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 207457224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 207665557 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14110208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 221775765 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 633029 # Total snoops (count) +system.membus.snoop_fanout::samples 4186947 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4885385 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4186947 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4885385 # Request fanout histogram -system.membus.reqLayer0.occupancy 98770920 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4186947 # Request fanout histogram +system.membus.reqLayer0.occupancy 98514469 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21644945 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21244987 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 25191464236 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 16556458898 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 16738053981 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 17312327015 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187451430 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187280188 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3423,49 +3539,49 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 7757807 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7750243 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38586 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38586 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2284318 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1682954 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1576219 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 430271 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 347651 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 777922 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 191 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 316482 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 316482 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11788342 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9897130 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 21685472 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 381410986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320139805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 701550791 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1633796 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 12761522 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.009063 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.094770 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 8653355 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 8646086 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38526 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38526 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3063024 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 248029 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 141301 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 493306 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 294608 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 787914 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 273153 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 273153 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10956928 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10351144 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 21308072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 369780529 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 344544100 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 714324629 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1644746 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 12968411 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.008917 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.094008 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 12645858 99.09% 99.09% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115664 0.91% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 12852771 99.11% 99.11% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115640 0.89% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 12761522 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 21862906503 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 12968411 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 19352517195 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 6130500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7381500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 19509958221 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20456793572 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 17925237290 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 20083133002 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 14096 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 13518 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4921 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5604 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index d5d5bafb9..5bc8e2e71 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,158 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.557115 # Number of seconds simulated -sim_ticks 51557114994500 # Number of ticks simulated -final_tick 51557114994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.320621 # Number of seconds simulated +sim_ticks 51320620981500 # Number of ticks simulated +final_tick 51320620981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111994 # Simulator instruction rate (inst/s) -host_op_rate 131638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5181426993 # Simulator tick rate (ticks/s) -host_mem_usage 668412 # Number of bytes of host memory used -host_seconds 9950.37 # Real time elapsed on the host -sim_insts 1114380469 # Number of instructions simulated -sim_ops 1309844804 # Number of ops (including micro ops) simulated +host_inst_rate 107709 # Simulator instruction rate (inst/s) +host_op_rate 126560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6449160479 # Simulator tick rate (ticks/s) +host_mem_usage 667684 # Number of bytes of host memory used +host_seconds 7957.72 # Real time elapsed on the host +sim_insts 857117694 # Number of instructions simulated +sim_ops 1007133124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.ide 437568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1002304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 1237760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6145632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 128560840 # Number of bytes read from this memory -system.physmem.bytes_read::total 137384104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6145632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6145632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 102180288 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 102783780 # Number of bytes written to this memory -system.physmem.bytes_written::total 211790564 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 6837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 15661 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 19340 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 111978 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2008776 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2162592 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1596567 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 1608248 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3311479 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 8487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 19441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 24008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 119200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2493562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2664697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 119200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 119200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1981885 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 132406 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1993591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4107882 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1981885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 140894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 19441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 24008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 119200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4487152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6772580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2162592 # Number of read requests accepted -system.physmem.writeReqs 3311479 # Number of write requests accepted -system.physmem.readBursts 2162592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 3311479 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 138204608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 201280 # Total number of bytes read from write queue -system.physmem.bytesWritten 207618304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 137384104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 211790564 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 3145 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 67428 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48470 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 140382 # Per bank write bursts -system.physmem.perBankRdBursts::1 139333 # Per bank write bursts -system.physmem.perBankRdBursts::2 140658 # Per bank write bursts -system.physmem.perBankRdBursts::3 133921 # Per bank write bursts -system.physmem.perBankRdBursts::4 130324 # Per bank write bursts -system.physmem.perBankRdBursts::5 134612 # Per bank write bursts -system.physmem.perBankRdBursts::6 126217 # Per bank write bursts -system.physmem.perBankRdBursts::7 133097 # Per bank write bursts -system.physmem.perBankRdBursts::8 129592 # Per bank write bursts -system.physmem.perBankRdBursts::9 157619 # Per bank write bursts -system.physmem.perBankRdBursts::10 133394 # Per bank write bursts -system.physmem.perBankRdBursts::11 133867 # Per bank write bursts -system.physmem.perBankRdBursts::12 132326 # Per bank write bursts -system.physmem.perBankRdBursts::13 132284 # Per bank write bursts -system.physmem.perBankRdBursts::14 133117 # Per bank write bursts -system.physmem.perBankRdBursts::15 128704 # Per bank write bursts -system.physmem.perBankWrBursts::0 201659 # Per bank write bursts -system.physmem.perBankWrBursts::1 203665 # Per bank write bursts -system.physmem.perBankWrBursts::2 231223 # Per bank write bursts -system.physmem.perBankWrBursts::3 188549 # Per bank write bursts -system.physmem.perBankWrBursts::4 224931 # Per bank write bursts -system.physmem.perBankWrBursts::5 188791 # Per bank write bursts -system.physmem.perBankWrBursts::6 176287 # Per bank write bursts -system.physmem.perBankWrBursts::7 226882 # Per bank write bursts -system.physmem.perBankWrBursts::8 203233 # Per bank write bursts -system.physmem.perBankWrBursts::9 233524 # Per bank write bursts -system.physmem.perBankWrBursts::10 253232 # Per bank write bursts -system.physmem.perBankWrBursts::11 198347 # Per bank write bursts -system.physmem.perBankWrBursts::12 181957 # Per bank write bursts -system.physmem.perBankWrBursts::13 175879 # Per bank write bursts -system.physmem.perBankWrBursts::14 180282 # Per bank write bursts -system.physmem.perBankWrBursts::15 175595 # Per bank write bursts +system.physmem.bytes_read::cpu.dtb.walker 227264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 206272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5756576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 43073416 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 400256 # Number of bytes read from this memory +system.physmem.bytes_read::total 49663784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5756576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5756576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69780544 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 69801124 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3551 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3223 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 105899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 673035 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6254 # Number of read requests responded to by this memory +system.physmem.num_reads::total 791962 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1090321 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1092894 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 112169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 839300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 967716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 112169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1359698 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1360099 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1359698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 112169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 839701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2327815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 791962 # Number of read requests accepted +system.physmem.writeReqs 1696531 # Number of write requests accepted +system.physmem.readBursts 791962 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1696531 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 50649920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35648 # Total number of bytes read from write queue +system.physmem.bytesWritten 108090368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 49663784 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 108433892 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 557 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7601 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 35291 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 50546 # Per bank write bursts +system.physmem.perBankRdBursts::1 51810 # Per bank write bursts +system.physmem.perBankRdBursts::2 46789 # Per bank write bursts +system.physmem.perBankRdBursts::3 46242 # Per bank write bursts +system.physmem.perBankRdBursts::4 46096 # Per bank write bursts +system.physmem.perBankRdBursts::5 52242 # Per bank write bursts +system.physmem.perBankRdBursts::6 46925 # Per bank write bursts +system.physmem.perBankRdBursts::7 49452 # Per bank write bursts +system.physmem.perBankRdBursts::8 44750 # Per bank write bursts +system.physmem.perBankRdBursts::9 73148 # Per bank write bursts +system.physmem.perBankRdBursts::10 48402 # Per bank write bursts +system.physmem.perBankRdBursts::11 51457 # Per bank write bursts +system.physmem.perBankRdBursts::12 45806 # Per bank write bursts +system.physmem.perBankRdBursts::13 48601 # Per bank write bursts +system.physmem.perBankRdBursts::14 42635 # Per bank write bursts +system.physmem.perBankRdBursts::15 46504 # Per bank write bursts +system.physmem.perBankWrBursts::0 106325 # Per bank write bursts +system.physmem.perBankWrBursts::1 106592 # Per bank write bursts +system.physmem.perBankWrBursts::2 106293 # Per bank write bursts +system.physmem.perBankWrBursts::3 105191 # Per bank write bursts +system.physmem.perBankWrBursts::4 106687 # Per bank write bursts +system.physmem.perBankWrBursts::5 109171 # Per bank write bursts +system.physmem.perBankWrBursts::6 103226 # Per bank write bursts +system.physmem.perBankWrBursts::7 105745 # Per bank write bursts +system.physmem.perBankWrBursts::8 103090 # Per bank write bursts +system.physmem.perBankWrBursts::9 109771 # Per bank write bursts +system.physmem.perBankWrBursts::10 107182 # Per bank write bursts +system.physmem.perBankWrBursts::11 108709 # Per bank write bursts +system.physmem.perBankWrBursts::12 102154 # Per bank write bursts +system.physmem.perBankWrBursts::13 106063 # Per bank write bursts +system.physmem.perBankWrBursts::14 100653 # Per bank write bursts +system.physmem.perBankWrBursts::15 102060 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 190 # Number of times write queue was full causing retry -system.physmem.totGap 51557113761500 # Total gap between requests +system.physmem.numWrRetry 63 # Number of times write queue was full causing retry +system.physmem.totGap 51320619748500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2141307 # Read request sizes (log2) +system.physmem.readPktSize::6 770677 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 3308906 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1296550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 764534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1693958 # 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What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -178,357 +159,191 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 55343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 88539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 132669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 172060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 179259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 199827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 201826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 215089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 217686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 234764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 216813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 209096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 190795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 202440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 157954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 153989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 157951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 145311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 3461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 2987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 474 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1034839 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 334.179783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.532509 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.014667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 392208 37.90% 37.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 234584 22.67% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 87901 8.49% 69.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 49413 4.77% 73.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 38348 3.71% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 26689 2.58% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21988 2.12% 82.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25501 2.46% 84.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 158207 15.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1034839 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 135592 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.925969 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 128.724301 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 135587 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-43007 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 135592 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 135592 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.924981 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.930688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.164557 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 101303 74.71% 74.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 7599 5.60% 80.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 12845 9.47% 89.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 3908 2.88% 92.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 2324 1.71% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 925 0.68% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 2932 2.16% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1250 0.92% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 889 0.66% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 249 0.18% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 327 0.24% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 193 0.14% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 473 0.35% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 16 0.01% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 22 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 28 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 17 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 31 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 89 0.07% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 56 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 42 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 15 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 15 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 35109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 66510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 80685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 95220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 95674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 107871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 105650 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 2041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 151 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 519847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 305.358892 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.693203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.458813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 210597 40.51% 40.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 125304 24.10% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44434 8.55% 73.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23828 4.58% 77.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16026 3.08% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10297 1.98% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8038 1.55% 84.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7736 1.49% 85.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 73587 14.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 519847 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65806 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.026092 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 69.420005 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 65801 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 65806 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65806 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.665015 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 22.295407 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 18.784846 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 44130 67.06% 67.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 6726 10.22% 77.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 8110 12.32% 89.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 2086 3.17% 92.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 1158 1.76% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 536 0.81% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 588 0.89% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 530 0.81% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 479 0.73% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 220 0.33% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 383 0.58% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 149 0.23% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 276 0.42% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 79 0.12% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 128 0.19% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 41 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 35 0.05% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 20 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 44 0.07% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 20 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 23 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 10 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 10 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::216-223 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 6 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 5 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 5 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 135592 # Writes before turning the bus around for reads -system.physmem.totQLat 43990891280 # Total ticks spent queuing -system.physmem.totMemAccLat 84480522530 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10797235000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20371.37 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::224-231 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 65806 # Writes before turning the bus around for reads +system.physmem.totQLat 15790981009 # Total ticks spent queuing +system.physmem.totMemAccLat 30629824759 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3957025000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19953.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39121.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.68 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38703.10 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing -system.physmem.readRowHits 1747291 # Number of row buffer hits during reads -system.physmem.writeRowHits 2621349 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.91 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 9418422.55 # Average gap between requests -system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49290195125250 # Time in different power states -system.physmem.memoryStateTime::REF 1721605340000 # Time in different power states +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.05 # Average write queue length when enqueuing +system.physmem.readRowHits 603831 # Number of row buffer hits during reads +system.physmem.writeRowHits 1356638 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes +system.physmem.avgGap 20623172.24 # Average gap between requests +system.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49368372569000 # Time in different power states +system.physmem.memoryStateTime::REF 1713708100000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 545313634750 # Time in different power states +system.physmem.memoryStateTime::ACT 238539960500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3951453240 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3871929600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2156050875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2112660000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 8412588600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 8431020000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 10640075760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 10381277520 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3367460045040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3367460045040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1383947967870 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1368871606665 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29720278968750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29733503847000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34496847150135 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34494632385825 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.099654 # Core power per rank (mW) -system.physmem.averagePower::1 669.056696 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 657217 # Transaction distribution -system.membus.trans_dist::ReadResp 657217 # Transaction distribution -system.membus.trans_dist::WriteReq 33865 # Transaction distribution -system.membus.trans_dist::WriteResp 33865 # Transaction distribution -system.membus.trans_dist::Writeback 1596567 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1712339 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1712339 # Transaction distribution -system.membus.trans_dist::UpgradeReq 48473 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 48476 # Transaction distribution -system.membus.trans_dist::ReadExReq 1541174 # Transaction distribution -system.membus.trans_dist::ReadExResp 1541174 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9221519 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9351669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 229018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9580687 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341910604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 342081160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7264064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 349345224 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2022 # Total snoops (count) -system.membus.snoop_fanout::samples 5500895 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5500895 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 5500895 # Request fanout histogram -system.membus.reqLayer0.occupancy 109641999 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5450500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 32462148974 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 21571101815 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186532342 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.physmem.actEnergy::0 1984348800 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 1945694520 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1082730000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1061638875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 3042748800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 3130163400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 5503010400 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 5441139360 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3352013043600 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3352013043600 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1228384903950 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1226638074825 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29714838054000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29716370360250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34306848839550 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34306600114830 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.480867 # Core power per rank (mW) +system.physmem.averagePower::1 668.476020 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 40379 # Transaction distribution -system.iobus.trans_dist::ReadResp 40379 # Transaction distribution -system.iobus.trans_dist::WriteReq 136716 # Transaction distribution -system.iobus.trans_dist::WriteResp 136733 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 17 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354224 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492654 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 981079506 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179002658 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 291488483 # Number of BP lookups -system.cpu.branchPred.condPredicted 200150149 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13608043 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 209143322 # Number of BTB lookups -system.cpu.branchPred.BTBHits 138326751 # Number of BTB hits +system.cpu.branchPred.lookups 226428976 # Number of BP lookups +system.cpu.branchPred.condPredicted 151471445 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12246087 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159886473 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104578062 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.139693 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37688944 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 403819 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.407698 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31061917 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 345275 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -552,25 +367,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 220000246 # DTB read hits -system.cpu.dtb.read_misses 1007031 # DTB read misses -system.cpu.dtb.write_hits 193886106 # DTB write hits -system.cpu.dtb.write_misses 416122 # DTB write misses -system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 171196432 # DTB read hits +system.cpu.dtb.read_misses 671544 # DTB read misses +system.cpu.dtb.write_hits 149025904 # DTB write hits +system.cpu.dtb.write_misses 258759 # DTB write misses +system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 63968 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 89690 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 112 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15179 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72979 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 104 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10362 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 87251 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 221007277 # DTB read accesses -system.cpu.dtb.write_accesses 194302228 # DTB write accesses +system.cpu.dtb.perms_faults 68614 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 171867976 # DTB read accesses +system.cpu.dtb.write_accesses 149284663 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 413886352 # DTB hits -system.cpu.dtb.misses 1423153 # DTB misses -system.cpu.dtb.accesses 415309505 # DTB accesses +system.cpu.dtb.hits 320222336 # DTB hits +system.cpu.dtb.misses 930303 # DTB misses +system.cpu.dtb.accesses 321152639 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -592,635 +407,803 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 465588468 # ITB inst hits -system.cpu.itb.inst_misses 176797 # ITB inst misses +system.cpu.itb.inst_hits 360051885 # ITB inst hits +system.cpu.itb.inst_misses 161655 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 63968 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 63536 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53701 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 462381 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 372863 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 465765265 # ITB inst accesses -system.cpu.itb.hits 465588468 # DTB hits -system.cpu.itb.misses 176797 # DTB misses -system.cpu.itb.accesses 465765265 # DTB accesses -system.cpu.numCycles 2146849645 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 360213540 # ITB inst accesses +system.cpu.itb.hits 360051885 # DTB hits +system.cpu.itb.misses 161655 # DTB misses +system.cpu.itb.accesses 360213540 # DTB accesses +system.cpu.numCycles 1576874693 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 791511347 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1301628389 # Number of instructions fetch has processed -system.cpu.fetch.Branches 291488483 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 176015695 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1268750537 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29307286 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4254748 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 12217982 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1219824 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 381 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 465107423 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6746831 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 53918 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2092636388 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.729302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.142136 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 648679854 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1010290403 # Number of instructions fetch has processed +system.cpu.fetch.Branches 226428976 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135639979 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 852655064 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26160452 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3389644 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9240220 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1021673 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 362 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 359662567 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6136086 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 47510 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1528093850 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.774691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.161324 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1367675983 65.36% 65.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 280886167 13.42% 78.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 86945610 4.15% 82.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 357128628 17.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 965958627 63.21% 63.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215893777 14.13% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70817340 4.63% 81.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 275424106 18.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2092636388 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.135775 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.606297 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 614820490 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 852644163 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 531180111 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 83391963 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10599661 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41490545 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4112846 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1415541998 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32718079 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10599661 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 678805488 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 83662136 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 556428904 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 549849830 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 213290369 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1391734034 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 7977079 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7435136 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 893230 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1023922 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 127479585 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 25199 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1342075875 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2217645602 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1652184740 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1639045 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1263873564 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78202308 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44203192 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39719264 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 172796539 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 223511224 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 198396121 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12647992 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11061331 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1338396177 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 44508712 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1370133902 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4153047 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65240654 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41320787 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 373617 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2092636388 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.654741 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.915536 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1528093850 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.143594 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.640692 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 527180052 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 504302107 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 436284853 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 51059674 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9267164 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33905862 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3872221 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1095429909 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29099398 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9267164 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 572442291 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46180186 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 363186865 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 441948285 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 95069059 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1075584704 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6788495 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4945824 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 318864 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 589123 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 42956715 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 21763 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1023437611 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1659121727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1272319582 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1685396 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 957674620 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65762988 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27435128 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23745394 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 104747763 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 175168030 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 152601618 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9963388 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9061948 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1040022976 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27737741 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1056135120 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3300763 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53598061 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33623556 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 314928 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1528093850 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.691145 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.927830 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1237717942 59.15% 59.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 455529583 21.77% 80.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 292996726 14.00% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96986296 4.63% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9377226 0.45% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 28615 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 873977548 57.19% 57.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 338098484 22.13% 79.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 236626258 15.49% 94.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72801252 4.76% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6571176 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19132 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2092636388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1528093850 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 74528454 34.28% 34.28% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90672 0.04% 34.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26772 0.01% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 287 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 58830485 27.06% 61.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83911289 38.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58371154 35.14% 35.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100885 0.06% 35.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26756 0.02% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 767 0.00% 35.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44544414 26.81% 62.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63075062 37.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 945793660 69.03% 69.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2946266 0.22% 69.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 129775 0.01% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 114397 0.01% 69.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 224851656 16.41% 85.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 196298100 14.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 727332382 68.87% 68.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2546997 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 123061 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 120668 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 175096796 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150915164 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1370133902 # Type of FU issued -system.cpu.iq.rate 0.638207 # Inst issue rate -system.cpu.iq.fu_busy_cnt 217387959 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.158662 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5052021388 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1447405501 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1347303683 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2423809 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 923681 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 885699 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1585997449 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1524411 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5766333 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1056135120 # Type of FU issued +system.cpu.iq.rate 0.669765 # Inst issue rate +system.cpu.iq.fu_busy_cnt 166119038 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157290 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3807304115 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1120557954 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1038099529 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2479775 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 941816 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 907592 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1220693938 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1560218 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4348848 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16996131 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24128 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 185382 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8259714 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13855252 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14404 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 142361 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6337064 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3623609 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3385962 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2552747 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1859122 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10599661 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11961718 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7304667 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1383179145 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9267164 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6379535 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3965873 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1067985048 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 223511224 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 198396121 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39177517 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 185228 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6936317 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 185382 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4274350 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5730421 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10004771 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1356817685 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 220004444 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11924579 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 175168030 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 152601618 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23314125 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 62024 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3832996 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 142361 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3691152 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5135953 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8827105 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1044930592 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 171186057 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10287379 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 274256 # number of nop insts executed -system.cpu.iew.exec_refs 413901554 # number of memory reference insts executed -system.cpu.iew.exec_branches 257473473 # Number of branches executed -system.cpu.iew.exec_stores 193897110 # Number of stores executed -system.cpu.iew.exec_rate 0.632004 # Inst execution rate -system.cpu.iew.wb_sent 1349182874 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1348189382 # cumulative count of insts written-back -system.cpu.iew.wb_producers 579023420 # num instructions producing a value -system.cpu.iew.wb_consumers 949767765 # num instructions consuming a value +system.cpu.iew.exec_nop 224331 # number of nop insts executed +system.cpu.iew.exec_refs 320208959 # number of memory reference insts executed +system.cpu.iew.exec_branches 198322451 # Number of branches executed +system.cpu.iew.exec_stores 149022902 # Number of stores executed +system.cpu.iew.exec_rate 0.662659 # Inst execution rate +system.cpu.iew.wb_sent 1039793819 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1039007121 # cumulative count of insts written-back +system.cpu.iew.wb_producers 442154878 # num instructions producing a value +system.cpu.iew.wb_consumers 715627882 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.627985 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.609647 # average fanout of values written-back +system.cpu.iew.wb_rate 0.658903 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.617856 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 62443917 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 44135095 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9554061 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2078483160 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.630193 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.269789 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51471265 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27422813 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8433025 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1516084212 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.664299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.291990 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1396354428 67.18% 67.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 397736022 19.14% 86.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 152396085 7.33% 93.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44287772 2.13% 95.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35996912 1.73% 97.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18656723 0.90% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10905184 0.52% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5449343 0.26% 99.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16700691 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 998537580 65.86% 65.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 291350566 19.22% 85.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 121957393 8.04% 93.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36696853 2.42% 95.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28610485 1.89% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14255849 0.94% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8557612 0.56% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4232636 0.28% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11885238 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2078483160 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1114380469 # Number of instructions committed -system.cpu.commit.committedOps 1309844804 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1516084212 # Number of insts commited each cycle +system.cpu.commit.committedInsts 857117694 # Number of instructions committed +system.cpu.commit.committedOps 1007133124 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 396651499 # Number of memory references committed -system.cpu.commit.loads 206515092 # Number of loads committed -system.cpu.commit.membars 9189565 # Number of memory barriers committed -system.cpu.commit.branches 249089949 # Number of branches committed -system.cpu.commit.fp_insts 873640 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1196978104 # Number of committed integer instructions. -system.cpu.commit.function_calls 31078874 # Number of function calls committed. +system.cpu.commit.refs 307577331 # Number of memory references committed +system.cpu.commit.loads 161312777 # Number of loads committed +system.cpu.commit.membars 7014752 # Number of memory barriers committed +system.cpu.commit.branches 191334741 # Number of branches committed +system.cpu.commit.fp_insts 896026 # Number of committed floating point instructions. +system.cpu.commit.int_insts 925144388 # Number of committed integer instructions. +system.cpu.commit.function_calls 25493443 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 910428363 69.51% 69.51% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2554988 0.20% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 104143 0.01% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 105769 0.01% 69.72% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.72% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.72% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.72% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 206515092 15.77% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 190136407 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 697181314 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2164633 0.21% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98281 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 161312777 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 146264554 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1309844804 # Class of committed instruction -system.cpu.commit.bw_lim_events 16700691 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 1007133124 # Class of committed instruction +system.cpu.commit.bw_lim_events 11885238 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3424556806 # The number of ROB reads -system.cpu.rob.rob_writes 2758622493 # The number of ROB writes -system.cpu.timesIdled 9031521 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 54213257 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100967380384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1114380469 # Number of Instructions Simulated -system.cpu.committedOps 1309844804 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.926496 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.926496 # CPI: Total CPI of All Threads -system.cpu.ipc 0.519077 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.519077 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1611998606 # number of integer regfile reads -system.cpu.int_regfile_writes 948639021 # number of integer regfile writes -system.cpu.fp_regfile_reads 1420015 # number of floating regfile reads -system.cpu.fp_regfile_writes 765124 # number of floating regfile writes -system.cpu.cc_regfile_reads 315259155 # number of cc regfile reads -system.cpu.cc_regfile_writes 316098925 # number of cc regfile writes -system.cpu.misc_regfile_reads 6952427793 # number of misc regfile reads -system.cpu.misc_regfile_writes 45059384 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 28539920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28531649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33865 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33865 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 9369509 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1712344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1605675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 61529 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 61535 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3074731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3074731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33703094 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37825776 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 810571 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3115869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 75455310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1077469744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1502191576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2724416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10868120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2593253856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 644632 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 42703026 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.002705 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051942 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 42587504 99.73% 99.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115522 0.27% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 42703026 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32333793873 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 871500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25296093441 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19876823538 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 472614279 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1760067316 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 16829629 # number of replacements -system.cpu.icache.tags.tagsinuse 511.959617 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 447510611 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16830141 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.589831 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 12236526000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.959617 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 2555181565 # The number of ROB reads +system.cpu.rob.rob_writes 2129123637 # The number of ROB writes +system.cpu.timesIdled 8137810 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 48780843 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101064367400 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 857117694 # Number of Instructions Simulated +system.cpu.committedOps 1007133124 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.839741 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.839741 # CPI: Total CPI of All Threads +system.cpu.ipc 0.543555 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.543555 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237020079 # number of integer regfile reads +system.cpu.int_regfile_writes 738429626 # number of integer regfile writes +system.cpu.fp_regfile_reads 1457787 # number of floating regfile reads +system.cpu.fp_regfile_writes 782552 # number of floating regfile writes +system.cpu.cc_regfile_reads 228125574 # number of cc regfile reads +system.cpu.cc_regfile_writes 228731881 # number of cc regfile writes +system.cpu.misc_regfile_reads 5247037954 # number of misc regfile reads +system.cpu.misc_regfile_writes 27486572 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9822538 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.985265 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 286045243 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9823050 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.119799 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1485814250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.985265 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1249214859 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1249214859 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 148712432 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 148712432 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 129479125 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 129479125 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 381594 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 381594 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324870 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 324870 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352883 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3352883 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3750315 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3750315 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 278191557 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 278191557 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 278573151 # number of overall hits +system.cpu.dcache.overall_hits::total 278573151 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9502058 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9502058 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11465174 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11465174 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1197022 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1197022 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233022 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1233022 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 449448 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 449448 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20967232 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20967232 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22164254 # number of overall misses +system.cpu.dcache.overall_misses::total 22164254 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 140935225401 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 140935225401 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 322991667568 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 322991667568 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 38675981880 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 38675981880 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6315194753 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6315194753 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 139001 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 139001 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 463926892969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 463926892969 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 463926892969 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 463926892969 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 158214490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 158214490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 140944299 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 140944299 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578616 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1578616 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557892 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1557892 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3802331 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3802331 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3750320 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3750320 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 299158789 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 299158789 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 300737405 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 300737405 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060058 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060058 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081345 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081345 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758273 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.758273 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791468 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791468 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118203 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118203 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.070087 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070087 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.073700 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.073700 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14832.073789 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14832.073789 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28171.545200 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28171.545200 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31366.822230 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31366.822230 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14051.002014 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14051.002014 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22126.282237 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22126.282237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20931.310973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20931.310973 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21466802 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1401851 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.313184 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 7593763 # number of writebacks +system.cpu.dcache.writebacks::total 7593763 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4321399 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4321399 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9425025 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9425025 # number of WriteReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7055 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7055 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219414 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 219414 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13746424 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13746424 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13746424 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13746424 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5180659 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5180659 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2040149 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2040149 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1190231 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1190231 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1225967 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1225967 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230034 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 230034 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7220808 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7220808 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8411039 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8411039 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70208074682 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 70208074682 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53752252884 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53752252884 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 18853760746 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 18853760746 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 35977742828 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 35977742828 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2809792248 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2809792248 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 128999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 128999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123960327566 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 123960327566 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142814088312 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 142814088312 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729213249 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729213249 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587099983 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587099983 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316313232 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316313232 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032745 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032745 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014475 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014475 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753971 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753971 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786940 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786940 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060498 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060498 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024137 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024137 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027968 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027968 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13551.958290 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13551.958290 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26347.219190 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26347.219190 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15840.421520 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15840.421520 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29346.420277 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29346.420277 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12214.682386 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12214.682386 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17167.099245 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17167.099245 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16979.363467 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16979.363467 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 15082585 # number of replacements +system.cpu.icache.tags.tagsinuse 511.954216 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 343840613 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15083097 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.796420 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 14175734000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.954216 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999911 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 92 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 481916487 # Number of tag accesses -system.cpu.icache.tags.data_accesses 481916487 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 447510611 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 447510611 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 447510611 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 447510611 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 447510611 # number of overall hits -system.cpu.icache.overall_hits::total 447510611 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17575514 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17575514 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17575514 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17575514 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17575514 # number of overall misses -system.cpu.icache.overall_misses::total 17575514 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 231527181766 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 231527181766 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 231527181766 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 231527181766 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 231527181766 # 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number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15083199 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15083199 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15083199 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15083199 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15083199 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15083199 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171815580989 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 171815580989 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171815580989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 171815580989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171815580989 # 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Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61774 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 485 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2102 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5030 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54369 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.007568 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.942596 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 341864435 # 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Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1230222 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.626040 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2430272000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37323.559826 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 320.853018 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 490.286692 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7518.567341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 19644.585230 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.569512 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004896 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007481 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70964.035146 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.412911 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70943.293622 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70224.050007 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.412911 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70943.293622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70224.050007 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1345,336 +1329,380 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 13756884 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.985330 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 363427258 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13757396 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.416864 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1485814250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.985330 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1609448196 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1609448196 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 188132338 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 188132338 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164232223 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164232223 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 465761 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 465761 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 1605675 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 1605675 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4847947 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4847947 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5335203 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5335203 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 352364561 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 352364561 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 352830322 # number of overall hits -system.cpu.dcache.overall_hits::total 352830322 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12712279 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12712279 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18968725 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18968725 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2072118 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2072118 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 550419 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 550419 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 31681004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 31681004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 33753122 # number of overall misses -system.cpu.dcache.overall_misses::total 33753122 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 203403538452 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 203403538452 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1021678237791 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1021678237791 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8626183252 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 8626183252 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 117003 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 117003 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1225081776243 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1225081776243 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1225081776243 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1225081776243 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 200844617 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 200844617 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 183200948 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 183200948 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2537879 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2537879 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1605675 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1605675 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5398366 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5398366 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5335209 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5335209 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 384045565 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 384045565 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 386583444 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 386583444 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063294 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.063294 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103541 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.103541 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816476 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.816476 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.101960 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.101960 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082493 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082493 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087311 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087311 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16000.556505 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16000.556505 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53861.197196 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53861.197196 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15672.030311 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15672.030311 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38669.285110 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38669.285110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36295.361841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36295.361841 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 38319499 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2284719 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.772084 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 1605675 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 9369509 # number of writebacks -system.cpu.dcache.writebacks::total 9369509 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5628309 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5628309 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15829986 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15829986 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265840 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 265840 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21458295 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21458295 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21458295 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21458295 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7083970 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7083970 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3120649 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3120649 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2065320 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 2065320 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 284579 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 284579 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 10204619 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 10204619 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 12269939 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 12269939 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 102477717871 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 102477717871 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 148263766896 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 148263766896 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 31611668497 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 31611668497 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 59007365277 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 59007365277 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3751055249 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3751055249 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 104997 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 104997 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250741484767 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 250741484767 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 282353153264 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 282353153264 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729434750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729434750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587276983 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587276983 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316711733 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316711733 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035271 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035271 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.017034 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.017034 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813798 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813798 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052716 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052716 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026571 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026571 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031739 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031739 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.142272 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.142272 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47510.555303 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47510.555303 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15305.942177 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15305.942177 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13181.068347 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13181.068347 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24571.371530 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24571.371530 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23011.781335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23011.781335 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 115458 # number of replacements -system.iocache.tags.tagsinuse 10.450727 # Cycle average of tags in use +system.cpu.toL2Bus.trans_dist::ReadReq 23341232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23333163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7593763 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1225967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43982 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1999866 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1999866 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30208899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27463876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 731462 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1967033 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 60371270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965659760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1114918084 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2404176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6408648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2089390668 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 611685 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 34508223 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.003348 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.057762 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 34392703 99.67% 99.67% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115520 0.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 34508223 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 26206492236 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 1177500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 22671590732 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13674088224 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 431886005 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 1166711358 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40382 # Transaction distribution +system.iobus.trans_dist::ReadResp 40382 # Transaction distribution +system.iobus.trans_dist::WriteReq 136733 # Transaction distribution +system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354230 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 1042360658 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179004169 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115462 # number of replacements +system.iocache.tags.tagsinuse 10.424613 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115478 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13090278324000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.528058 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.922669 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220504 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432667 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653170 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13092189065000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544618 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.879995 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039786 # Number of tag accesses -system.iocache.tags.data_accesses 1039786 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1039677 # Number of tag accesses +system.iocache.tags.data_accesses 1039677 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8816 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8853 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 17 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 17 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses -system.iocache.demand_misses::total 8853 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8816 # number of demand (read+write) misses +system.iocache.demand_misses::total 8856 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8813 # number of overall misses -system.iocache.overall_misses::total 8853 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5547000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1929395843 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1934942843 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8816 # number of overall misses +system.iocache.overall_misses::total 8856 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1927411613 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1932938613 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5886000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1929395843 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1935281843 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5886000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1929395843 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1935281843 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28910124876 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28910124876 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5866000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1927411613 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1933277613 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5866000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1927411613 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1933277613 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106681 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106681 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8816 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8856 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8816 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8856 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000159 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000159 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149918.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 218926.114036 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 218637.609379 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218626.544124 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 218337.130125 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 147150 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 218601.812154 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 147150 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 218601.812154 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 53350 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271039.196692 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271039.196692 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 218626.544124 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 218301.446816 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 218626.544124 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 218301.446816 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 226675 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27646 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.717668 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.199197 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8816 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8853 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8816 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8856 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3623000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1470987863 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1474610863 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8816 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8856 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1468863623 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1472466623 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6546677301 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6546677301 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3806000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1470987863 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1474793863 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3806000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1470987863 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1474793863 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23363269204 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23363269204 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1468863623 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1472649623 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1468863623 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1472649623 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166911.138432 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 166622.696384 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166613.387364 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 166324.028352 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219036.124691 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219036.124691 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 166613.387364 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 166288.349481 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 166613.387364 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 166288.349481 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 412825 # Transaction distribution +system.membus.trans_dist::ReadResp 412825 # Transaction distribution +system.membus.trans_dist::WriteReq 33858 # Transaction distribution +system.membus.trans_dist::WriteResp 33858 # Transaction distribution +system.membus.trans_dist::Writeback 1090321 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 603637 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 603637 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35296 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35298 # Transaction distribution +system.membus.trans_dist::ReadExReq 416163 # Transaction distribution +system.membus.trans_dist::ReadExResp 416163 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3625442 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3755550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4090619 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 144046540 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144217012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14051136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14051136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 158268148 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3264 # Total snoops (count) +system.membus.snoop_fanout::samples 2503253 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 2503253 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2503253 # Request fanout histogram +system.membus.reqLayer0.occupancy 109702500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5437999 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 16337638979 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 7836649146 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186565831 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 17164 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16179 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index dc447388d..a91165258 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,185 +1,176 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.274675 # Number of seconds simulated -sim_ticks 51274674635500 # Number of ticks simulated -final_tick 51274674635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.234988 # Number of seconds simulated +sim_ticks 51234988037500 # Number of ticks simulated +final_tick 51234988037500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 308954 # Simulator instruction rate (inst/s) -host_op_rate 363040 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18009090527 # Simulator tick rate (ticks/s) -host_mem_usage 661116 # Number of bytes of host memory used -host_seconds 2847.16 # Real time elapsed on the host -sim_insts 879639951 # Number of instructions simulated -sim_ops 1033631621 # Number of ops (including micro ops) simulated +host_inst_rate 253332 # Simulator instruction rate (inst/s) +host_op_rate 297695 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14683650995 # Simulator tick rate (ticks/s) +host_mem_usage 666424 # Number of bytes of host memory used +host_seconds 3489.25 # Real time elapsed on the host +sim_insts 883939374 # Number of instructions simulated +sim_ops 1038732312 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 391104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 245504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 412480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2683060 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 32648008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 82560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 137216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 615744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 8957184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 211392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 332480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 2079744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 22931008 # Number of bytes read from this memory -system.physmem.bytes_read::total 71727484 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2683060 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 615744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 2079744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5378548 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 40940416 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 59033572 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 12553152 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 28525952 # Number of bytes written to this memory -system.physmem.bytes_written::total 147879588 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 6111 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 3836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 6445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 82330 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 510138 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2144 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9621 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 139956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 3303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 5195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 32496 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 358297 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1161162 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 639694 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 924651 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 196143 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 445718 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2312870 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 7628 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 4788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 8045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 52327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 636728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2676 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 12009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 174690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 4123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 6484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 40561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 447219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1398887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 52327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 12009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 40561 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 104897 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 798453 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 133136 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 1151320 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 244822 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 556336 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2884067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 798453 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 140763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 8045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 52327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1788048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 12009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 419512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 4123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 6484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 40561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1003555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4282954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 556099 # Number of read requests accepted -system.physmem.writeReqs 996967 # Number of write requests accepted -system.physmem.readBursts 556099 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 996967 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 35500160 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 90176 # Total number of bytes read from write queue -system.physmem.bytesWritten 61170112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 35590336 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 63805888 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1409 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 41184 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18778 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 32891 # Per bank write bursts -system.physmem.perBankRdBursts::1 34922 # Per bank write bursts -system.physmem.perBankRdBursts::2 33947 # Per bank write bursts -system.physmem.perBankRdBursts::3 34663 # Per bank write bursts -system.physmem.perBankRdBursts::4 34185 # Per bank write bursts -system.physmem.perBankRdBursts::5 37826 # Per bank write bursts -system.physmem.perBankRdBursts::6 34767 # Per bank write bursts -system.physmem.perBankRdBursts::7 37084 # Per bank write bursts -system.physmem.perBankRdBursts::8 34802 # Per bank write bursts -system.physmem.perBankRdBursts::9 37662 # Per bank write bursts -system.physmem.perBankRdBursts::10 34607 # Per bank write bursts -system.physmem.perBankRdBursts::11 34013 # Per bank write bursts -system.physmem.perBankRdBursts::12 33947 # Per bank write bursts -system.physmem.perBankRdBursts::13 34396 # Per bank write bursts -system.physmem.perBankRdBursts::14 33124 # Per bank write bursts -system.physmem.perBankRdBursts::15 31854 # Per bank write bursts -system.physmem.perBankWrBursts::0 51538 # Per bank write bursts -system.physmem.perBankWrBursts::1 50883 # Per bank write bursts -system.physmem.perBankWrBursts::2 55756 # Per bank write bursts -system.physmem.perBankWrBursts::3 53410 # Per bank write bursts -system.physmem.perBankWrBursts::4 72819 # Per bank write bursts -system.physmem.perBankWrBursts::5 60009 # Per bank write bursts -system.physmem.perBankWrBursts::6 50793 # Per bank write bursts -system.physmem.perBankWrBursts::7 81282 # Per bank write bursts -system.physmem.perBankWrBursts::8 66815 # Per bank write bursts -system.physmem.perBankWrBursts::9 79578 # Per bank write bursts -system.physmem.perBankWrBursts::10 79171 # Per bank write bursts -system.physmem.perBankWrBursts::11 57649 # Per bank write bursts -system.physmem.perBankWrBursts::12 53518 # Per bank write bursts -system.physmem.perBankWrBursts::13 50714 # Per bank write bursts -system.physmem.perBankWrBursts::14 46719 # Per bank write bursts -system.physmem.perBankWrBursts::15 45129 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 127040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 124736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3010420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25072712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 36992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 30656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 716608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7359168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 93568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 90944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 2126784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 17729152 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 417856 # Number of bytes read from this memory +system.physmem.bytes_read::total 56936636 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3010420 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 716608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 2126784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5853812 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77081408 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 77101988 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1949 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 87445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 391774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 479 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 11197 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 114987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 1462 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1421 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 33231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 277018 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6529 # Number of read requests responded to by this memory +system.physmem.num_reads::total 930055 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1204397 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1206970 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 58757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 489367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 13987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 143636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 1826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 1775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 41510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 346036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1111284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 58757 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 13987 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 41510 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 114254 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1504468 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1504870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1504468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 58757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 489769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 13987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 143636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 1826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 1775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 41510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 346036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2616154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 440433 # Number of read requests accepted +system.physmem.writeReqs 603232 # Number of write requests accepted +system.physmem.readBursts 440433 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 603232 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28170752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16960 # Total number of bytes read from write queue +system.physmem.bytesWritten 38511488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28187712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 38606848 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 265 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1490 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 18504 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25157 # Per bank write bursts +system.physmem.perBankRdBursts::1 28496 # Per bank write bursts +system.physmem.perBankRdBursts::2 28335 # Per bank write bursts +system.physmem.perBankRdBursts::3 27633 # Per bank write bursts +system.physmem.perBankRdBursts::4 27808 # Per bank write bursts +system.physmem.perBankRdBursts::5 30320 # Per bank write bursts +system.physmem.perBankRdBursts::6 26148 # Per bank write bursts +system.physmem.perBankRdBursts::7 26657 # Per bank write bursts +system.physmem.perBankRdBursts::8 26790 # Per bank write bursts +system.physmem.perBankRdBursts::9 29797 # Per bank write bursts +system.physmem.perBankRdBursts::10 28841 # Per bank write bursts +system.physmem.perBankRdBursts::11 30668 # Per bank write bursts +system.physmem.perBankRdBursts::12 26625 # Per bank write bursts +system.physmem.perBankRdBursts::13 26518 # Per bank write bursts +system.physmem.perBankRdBursts::14 25131 # Per bank write bursts +system.physmem.perBankRdBursts::15 25244 # Per bank write bursts +system.physmem.perBankWrBursts::0 36236 # Per bank write bursts +system.physmem.perBankWrBursts::1 36759 # Per bank write bursts +system.physmem.perBankWrBursts::2 37480 # Per bank write bursts +system.physmem.perBankWrBursts::3 39199 # Per bank write bursts +system.physmem.perBankWrBursts::4 39135 # Per bank write bursts +system.physmem.perBankWrBursts::5 41156 # Per bank write bursts +system.physmem.perBankWrBursts::6 37007 # Per bank write bursts +system.physmem.perBankWrBursts::7 36943 # Per bank write bursts +system.physmem.perBankWrBursts::8 37618 # Per bank write bursts +system.physmem.perBankWrBursts::9 39787 # Per bank write bursts +system.physmem.perBankWrBursts::10 38447 # Per bank write bursts +system.physmem.perBankWrBursts::11 38818 # Per bank write bursts +system.physmem.perBankWrBursts::12 34864 # Per bank write bursts +system.physmem.perBankWrBursts::13 36482 # Per bank write bursts +system.physmem.perBankWrBursts::14 35714 # Per bank write bursts +system.physmem.perBankWrBursts::15 36097 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 45 # Number of times write queue was full causing retry -system.physmem.totGap 51273477930500 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 51233791781500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 556099 # Read request sizes (log2) +system.physmem.readPktSize::6 440433 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 996967 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 389698 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 112133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 603232 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 309302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -189,927 +180,227 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 479 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 42662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 45878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 50737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 55571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 55063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 67007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 56729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 57939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 47309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 45594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 44878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 43071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 114 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 313965 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 307.901429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.041097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.087880 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 132720 42.27% 42.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 70601 22.49% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25843 8.23% 72.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12745 4.06% 77.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9334 2.97% 80.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6247 1.99% 82.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5388 1.72% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6641 2.12% 85.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 44446 14.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 313965 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 40272 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.773590 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 142.393884 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 40271 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 40272 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 40272 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.733189 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.769670 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.088668 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 6 0.01% 0.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.00% 0.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 4 0.01% 0.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 68 0.17% 0.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 21743 53.99% 54.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 7529 18.70% 72.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 844 2.10% 74.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 2202 5.47% 80.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3572 8.87% 89.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 961 2.39% 91.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 568 1.41% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 548 1.36% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 664 1.65% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 107 0.27% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 86 0.21% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 131 0.33% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 645 1.60% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 191 0.47% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 148 0.37% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 110 0.27% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 71 0.18% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 17 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 8 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 9 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 6 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 40272 # Writes before turning the bus around for reads -system.physmem.totQLat 10784853014 # Total ticks spent queuing -system.physmem.totMemAccLat 21185290514 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2773450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19443.03 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::2 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 24225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 27652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 32938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 36604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 38132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 38614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 39680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 39064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 37806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 36835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 37288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 31145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 270943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 246.111691 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.841271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 289.814348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 123351 45.53% 45.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 67798 25.02% 70.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24089 8.89% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12477 4.61% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8623 3.18% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5501 2.03% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4269 1.58% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3914 1.44% 92.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20921 7.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 270943 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 29531 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.905286 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10.293446 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-15 12117 41.03% 41.03% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16-31 16080 54.45% 95.48% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-47 1080 3.66% 99.14% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::48-63 183 0.62% 99.76% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-79 43 0.15% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::80-95 13 0.04% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-111 6 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::112-127 3 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-143 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::176-191 2 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::320-335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 29531 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 29531 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.376621 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.754514 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.014003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 5 0.02% 0.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 10 0.03% 0.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 10 0.03% 0.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 38 0.13% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 24052 81.45% 81.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2161 7.32% 88.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 399 1.35% 90.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 574 1.94% 92.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 563 1.91% 94.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 287 0.97% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 195 0.66% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 150 0.51% 96.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 203 0.69% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 86 0.29% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 51 0.17% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 59 0.20% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 110 0.37% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 84 0.28% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 56 0.19% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 59 0.20% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 85 0.29% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 34 0.12% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 26 0.09% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 18 0.06% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 70 0.24% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 10 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 9 0.03% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 9 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 14 0.05% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 8 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 6 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 7 0.02% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 32 0.11% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 9 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 8 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 2 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 29531 # Writes before turning the bus around for reads +system.physmem.totQLat 10316676500 # Total ticks spent queuing +system.physmem.totMemAccLat 18569826500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2200840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23438.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38193.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.69 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.69 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.24 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42188.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.55 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.75 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.80 # Average write queue length when enqueuing -system.physmem.readRowHits 423817 # Number of row buffer hits during reads -system.physmem.writeRowHits 772691 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.41 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.84 # Row buffer hit rate for writes -system.physmem.avgGap 33014358.65 # Average gap between requests -system.physmem.pageHitRate 79.21 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49344562776500 # Time in different power states -system.physmem.memoryStateTime::REF 1712173840000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing +system.physmem.readRowHits 332271 # Number of row buffer hits during reads +system.physmem.writeRowHits 438696 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.90 # Row buffer hit rate for writes +system.physmem.avgGap 49090265.35 # Average gap between requests +system.physmem.pageHitRate 74.00 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49384314860250 # Time in different power states +system.physmem.memoryStateTime::REF 1710848620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 217931188500 # Time in different power states +system.physmem.memoryStateTime::ACT 139817808500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 1214869320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 1158706080 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 662875125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 632230500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2186223000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2140359000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3087655200 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3105818640 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3349012031040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3349012031040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1215657712530 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1211135236200 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29698434260250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29702401344750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34270255626465 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34269585726210 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.366215 # Core power per rank (mW) -system.physmem.averagePower::1 668.353150 # Core power per rank (mW) +system.physmem.actEnergy::0 1046447640 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 1001881440 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 570978375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 546661500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1720321200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1712989200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 1969369200 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 1929918960 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3346419900720 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3346419900720 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1177540520625 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1174853241090 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29708058483750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29710415746500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34237326021510 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34236880339410 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.241213 # Core power per rank (mW) +system.physmem.averagePower::1 668.232514 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 512200 # Transaction distribution -system.membus.trans_dist::ReadResp 512200 # Transaction distribution -system.membus.trans_dist::WriteReq 33772 # Transaction distribution -system.membus.trans_dist::WriteResp 33772 # Transaction distribution -system.membus.trans_dist::Writeback 639694 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1670603 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1670603 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36363 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36366 # Transaction distribution -system.membus.trans_dist::ReadExReq 685391 # Transaction distribution -system.membus.trans_dist::ReadExResp 685391 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6155552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6285312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229159 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 229159 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6514471 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156082 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212389664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 212559378 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7272512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 219831890 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1887 # Total snoops (count) -system.membus.snoop_fanout::samples 3467502 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3467502 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3467502 # Request fanout histogram -system.membus.reqLayer0.occupancy 48925999 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1640000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9861261476 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6001066379 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 87450398 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 829792 # number of replacements -system.l2c.tags.tagsinuse 64538.969055 # Cycle average of tags in use -system.l2c.tags.total_refs 28099922 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 891020 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 31.536803 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 13806560382000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35856.169681 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 191.429036 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 290.837170 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3857.675402 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9456.283942 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 48.759094 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 73.219747 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 709.055197 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2692.383155 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 111.816270 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 164.499208 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2725.095268 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 8361.745885 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.547122 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002921 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004438 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.058863 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.144291 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000744 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001117 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.010819 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.041083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001706 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.002510 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.041582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.127590 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.984787 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 502 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60726 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 489 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2207 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4867 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53302 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.007660 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.926605 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 265686556 # Number of tag accesses -system.l2c.tags.data_accesses 265686556 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 200882 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 128104 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 6599762 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3104423 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 71894 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 47918 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 2040254 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 973662 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 383209 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 140169 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 5756088 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 2406989 # number of ReadReq hits -system.l2c.ReadReq_hits::total 21853354 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 6807908 # number of Writeback hits -system.l2c.Writeback_hits::total 6807908 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 5076 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1634 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 4357 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11067 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 707211 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 212100 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 483663 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1402974 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 200882 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 128104 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6599762 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3811634 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 71894 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 47918 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 2040254 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 1185762 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 383209 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 140169 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 5756088 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 2890652 # number of demand (read+write) hits -system.l2c.demand_hits::total 23256328 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 200882 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 128104 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6599762 # number of overall hits -system.l2c.overall_hits::cpu0.data 3811634 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 71894 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 47918 # number of overall hits -system.l2c.overall_hits::cpu1.inst 2040254 # number of overall hits -system.l2c.overall_hits::cpu1.data 1185762 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 383209 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 140169 # number of overall hits -system.l2c.overall_hits::cpu2.inst 5756088 # number of overall hits -system.l2c.overall_hits::cpu2.data 2890652 # number of overall hits -system.l2c.overall_hits::total 23256328 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3836 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 6445 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 39229 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 153846 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1290 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2144 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9621 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 42836 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 3311 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 5220 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 32496 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 126310 # number of ReadReq misses -system.l2c.ReadReq_misses::total 426584 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17268 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5409 # 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number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.itb.walker 5195 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 32496 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 358478 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 552565 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 82180750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 139178500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 588487750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 2634900000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 218871226 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 341311238 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2138403529 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 8858602217 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15001935210 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3923029000 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu2.data 10580910001 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 14503939001 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 54095409 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 131333088 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 185428497 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 20002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5718766582 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 17592121130 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 23310887712 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 82180750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 139178500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 588487750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 8353666582 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 218871226 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 341311238 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 2138403529 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 26450723347 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 38312822922 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 82180750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 139178500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 588487750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 8353666582 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 218871226 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 341311238 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 2138403529 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 26450723347 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 38312822922 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 884253000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1618942500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 2503195500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 835101000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1639869500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2474970500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1719354000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 3258812000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4978166000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.017627 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.042827 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004693 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.042141 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.008545 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.035732 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005614 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.049858 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.010018 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767997 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.750458 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.395159 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.314262 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.324337 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.157675 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.017627 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.042827 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004693 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.105625 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.008545 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.035732 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005614 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.110330 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.022675 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.017627 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.042827 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004693 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.105625 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.008545 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.035732 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005614 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.110330 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.022675 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61167.004469 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61511.345597 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65805.130755 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70136.036427 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 67215.681681 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10023.131191 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10016.664704 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58833.836567 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75771.932576 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70773.308494 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61167.004469 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59652.855525 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65805.130755 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73786.183105 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69336.318663 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61167.004469 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59652.855525 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65805.130755 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73786.183105 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69336.318663 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 18 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 22792948 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 22787515 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33772 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33772 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 6807908 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1600102 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1563939 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 46847 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46853 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2088945 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2088945 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29041280 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27958653 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 843900 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1753644 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 59597477 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 926729300 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1105413310 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3095064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6286720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2041524394 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 368391 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 33333670 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003466 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.058768 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 33218144 99.65% 99.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115526 0.35% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 33333670 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 25204206978 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1129500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 35295410102 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 21026275011 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 267100118 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 646797339 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40334 # Transaction distribution -system.iobus.trans_dist::ReadResp 40334 # Transaction distribution -system.iobus.trans_dist::WriteReq 136600 # Transaction distribution -system.iobus.trans_dist::WriteResp 66161 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 65 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 70504 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48070 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230966 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230966 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353998 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48090 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156082 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334296 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334296 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492464 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 17794000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 9530000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 91000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 16563000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 71000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 339092871 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 44416000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 84714602 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 144000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1133,25 +424,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 79163453 # DTB read hits -system.cpu0.dtb.read_misses 85617 # DTB read misses -system.cpu0.dtb.write_hits 72660708 # DTB write hits -system.cpu0.dtb.write_misses 28291 # DTB write misses -system.cpu0.dtb.flush_tlb 1291 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 78485873 # DTB read hits +system.cpu0.dtb.read_misses 85123 # DTB read misses +system.cpu0.dtb.write_hits 72027961 # DTB write hits +system.cpu0.dtb.write_misses 28205 # DTB write misses +system.cpu0.dtb.flush_tlb 1285 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21000 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 522 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 52340 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 21048 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 51602 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3792 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4002 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9968 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 79249070 # DTB read accesses -system.cpu0.dtb.write_accesses 72688999 # DTB write accesses +system.cpu0.dtb.perms_faults 9811 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 78570996 # DTB read accesses +system.cpu0.dtb.write_accesses 72056166 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 151824161 # DTB hits -system.cpu0.dtb.misses 113908 # DTB misses -system.cpu0.dtb.accesses 151938069 # DTB accesses +system.cpu0.dtb.hits 150513834 # DTB hits +system.cpu0.dtb.misses 113328 # DTB misses +system.cpu0.dtb.accesses 150627162 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1173,524 +464,411 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 424925918 # ITB inst hits -system.cpu0.itb.inst_misses 64800 # ITB inst misses +system.cpu0.itb.inst_hits 421004293 # ITB inst hits +system.cpu0.itb.inst_misses 63363 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1291 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1285 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21000 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 522 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 37053 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21048 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 36267 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 424990718 # ITB inst accesses -system.cpu0.itb.hits 424925918 # DTB hits -system.cpu0.itb.misses 64800 # DTB misses -system.cpu0.itb.accesses 424990718 # DTB accesses -system.cpu0.numCycles 511314689 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 421067656 # ITB inst accesses +system.cpu0.itb.hits 421004293 # DTB hits +system.cpu0.itb.misses 63363 # DTB misses +system.cpu0.itb.accesses 421067656 # DTB accesses +system.cpu0.numCycles 506516508 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 424739937 # Number of instructions committed -system.cpu0.committedOps 499770936 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 458702697 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 419703 # Number of float alu accesses -system.cpu0.num_func_calls 25504192 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 64716286 # number of instructions that are conditional controls -system.cpu0.num_int_insts 458702697 # number of integer instructions -system.cpu0.num_fp_insts 419703 # number of float instructions -system.cpu0.num_int_register_reads 675611920 # number of times the integer registers were read -system.cpu0.num_int_register_writes 364415309 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 677474 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 352628 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 112049346 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 111774000 # number of times the CC registers were written -system.cpu0.num_mem_refs 151917751 # number of memory refs -system.cpu0.num_load_insts 79236622 # Number of load instructions -system.cpu0.num_store_insts 72681129 # Number of store instructions -system.cpu0.num_idle_cycles 499253695.584872 # Number of idle cycles -system.cpu0.num_busy_cycles 12060993.415128 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023588 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976412 # Percentage of idle cycles -system.cpu0.Branches 94879530 # Number of branches fetched +system.cpu0.committedInsts 420811760 # Number of instructions committed +system.cpu0.committedOps 495213745 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 454628715 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 411957 # Number of float alu accesses +system.cpu0.num_func_calls 25378118 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 63987651 # number of instructions that are conditional controls +system.cpu0.num_int_insts 454628715 # number of integer instructions +system.cpu0.num_fp_insts 411957 # number of float instructions +system.cpu0.num_int_register_reads 670075882 # number of times the integer registers were read +system.cpu0.num_int_register_writes 361231436 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 665979 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 343448 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 110680974 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 110422200 # number of times the CC registers were written +system.cpu0.num_mem_refs 150607491 # number of memory refs +system.cpu0.num_load_insts 78559078 # Number of load instructions +system.cpu0.num_store_insts 72048413 # Number of store instructions +system.cpu0.num_idle_cycles 494422986.191521 # Number of idle cycles +system.cpu0.num_busy_cycles 12093521.808479 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023876 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976124 # Percentage of idle cycles +system.cpu0.Branches 93934421 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 346985072 69.39% 69.39% # Class of executed instruction -system.cpu0.op_class::IntMult 1058214 0.21% 69.60% # Class of executed instruction -system.cpu0.op_class::IntDiv 47254 0.01% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 51204 0.01% 69.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.62% # Class of executed instruction -system.cpu0.op_class::MemRead 79236622 15.85% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 72681129 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 343753597 69.37% 69.37% # Class of executed instruction +system.cpu0.op_class::IntMult 1048568 0.21% 69.59% # Class of executed instruction +system.cpu0.op_class::IntDiv 47671 0.01% 69.60% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 50027 0.01% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::MemRead 78559078 15.85% 85.46% # Class of executed instruction +system.cpu0.op_class::MemWrite 72048413 14.54% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 500059496 # Class of executed instruction +system.cpu0.op_class::total 495507356 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16293 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 14476947 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.977197 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 610391871 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14477459 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.161533 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8950087250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 497.229242 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 6.558404 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 8.189551 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.971151 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.012809 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.015995 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 639762187 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 639762187 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 418346381 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 129402990 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 62642500 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 610391871 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 418346381 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 129402990 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 62642500 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 610391871 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 418346381 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 129402990 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 62642500 # number of overall hits -system.cpu0.icache.overall_hits::total 610391871 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6638991 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 2049875 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 6203870 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 14892736 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6638991 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 2049875 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 6203870 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 14892736 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6638991 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 2049875 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 6203870 # number of overall misses -system.cpu0.icache.overall_misses::total 14892736 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 27332922248 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 82496329525 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 109829251773 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 27332922248 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 82496329525 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 109829251773 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 27332922248 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 82496329525 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 109829251773 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 424985372 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 131452865 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 68846370 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 625284607 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 424985372 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 131452865 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 68846370 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 625284607 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 424985372 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 131452865 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 68846370 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 625284607 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015622 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015594 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.090112 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023818 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015622 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015594 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.090112 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023818 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015622 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015594 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.090112 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023818 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13333.945849 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13297.559350 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7374.686006 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13333.945849 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13297.559350 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7374.686006 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13333.945849 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13297.559350 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7374.686006 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 37721 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 3310 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.396073 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 415156 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 415156 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 415156 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 415156 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 415156 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 415156 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2049875 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 5788714 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 7838589 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 2049875 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 5788714 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 7838589 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 2049875 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 5788714 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 7838589 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 23229700752 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 67401467898 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 90631168650 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 23229700752 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 67401467898 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 90631168650 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 23229700752 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 67401467898 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 90631168650 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015594 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.084082 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012536 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015594 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.084082 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012536 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015594 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.084082 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012536 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11332.252333 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11643.599580 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11562.178939 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11332.252333 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11643.599580 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11562.178939 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11332.252333 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11643.599580 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11562.178939 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 10128409 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999720 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 303013393 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10128921 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.915664 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 16313 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 10203749 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999717 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 304434614 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10204261 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.834068 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.552561 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 7.756281 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.690878 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971782 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015149 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013068 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.228127 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.974365 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 10.797225 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969196 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009716 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.021088 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 210 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1287987504 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1287987504 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 73967004 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 23189496 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 58636674 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 155793174 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68735212 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 21073027 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 49137576 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 138945815 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 193443 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 57150 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 141238 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 391831 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 922078 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 196143 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data 445718 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 1563939 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1801315 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 562780 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1217494 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3581589 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1914885 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 606233 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 1395393 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3916511 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 142702216 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 44262523 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 107774250 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 294738989 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 142895659 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 44319673 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 107915488 # number of overall hits -system.cpu0.dcache.overall_hits::total 295130820 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2516282 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 796205 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 4618007 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7930494 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1086152 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 320705 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 4288284 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5695141 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 627582 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 187561 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 448945 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1264088 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 114405 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 43721 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 223929 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 382055 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3602434 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1116910 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 8906291 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13625635 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 3159923284 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3772450034 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 26501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 90002 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 116503 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 23015231491 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 260041813232 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 283057044723 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 23015231491 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 260041813232 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 283057044723 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 76483286 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 23985701 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 63254681 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 163723668 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 69821364 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 21393732 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 53425860 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 144640956 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 821025 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 244711 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 590183 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1655919 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 922078 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 196143 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data 445718 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1563939 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1915720 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 606501 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 1441423 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3963644 # 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number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 117270724 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 310020543 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032900 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033195 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.073007 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.048438 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015556 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014991 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.080266 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.039374 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764388 # 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Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 73268923 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 23739594 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 59414779 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156423296 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 68111490 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 21735522 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 49847350 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 139694362 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 193034 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58570 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 140375 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 391979 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 149338 # 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number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 9505378 # number of overall misses +system.cpu0.dcache.overall_misses::total 15067967 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 12089122250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 81775203412 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 93864325662 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9781004455 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 158074758437 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 167855762892 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 2453110503 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu2.data 10603203705 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 13056314208 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 651998250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 3227061036 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3879059286 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 150500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 64001 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 214501 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 21870126705 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 239849961849 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 261720088554 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 21870126705 # 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number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 253600 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 595759 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1669359 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 904400 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 191188 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data 469061 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1564649 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1923033 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 610017 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 1461076 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 3994126 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1922190 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 609753 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 1411608 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 3943551 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 144993450 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 46602672 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 118312123 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 309908245 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 145813450 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 46856272 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 118907882 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 311577604 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033348 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032325 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.074312 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.049178 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015685 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015158 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.079078 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.039205 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764593 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.769046 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.764376 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.765192 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.834876 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.726609 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu2.data 0.724582 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.788582 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059283 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.073965 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.157421 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.097425 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000003 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000003 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024623 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024613 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.076331 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.044187 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028751 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028592 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.079775 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048028 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15634.153265 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17928.852925 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12009.788963 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32950.033492 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 41332.674077 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 32977.846451 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14009.897990 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14111.273145 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9874.101985 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26501 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 18000.400000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19417.166667 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20606.164768 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 29197.542864 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20773.860794 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17643.344690 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27796.392655 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19010.229050 # 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miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028226 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.079939 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.048360 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.256508 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17144.719610 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11601.927327 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29238.223572 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36930.835195 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29447.454701 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 17658.567244 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu2.data 31197.546451 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38222185199 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2771251250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 9108575422 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 11879826672 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 6372956000 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data 16470207883 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 22843163883 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 406720000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1117052111 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 91825619964 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 959248000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1745955500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2705203500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 898794000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1756075958 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2654869958 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1858042000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3502031458 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5360073458 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033155 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031740 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017120 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014787 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013648 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007228 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.766157 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.748749 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.380083 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055654 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060930 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.030674 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 1123344 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 2773158 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 3896502 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 1318320 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 3221462 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4539782 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10425295500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 30694668987 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41119964487 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 8981852045 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 24997038072 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33978890117 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2907550500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 9282645690 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12190196190 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2175272497 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data 9841405614 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 12016678111 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 423668250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1137848378 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1561516628 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 146500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 55999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 202499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 19407147545 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 55691707059 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 75098854604 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22314698045 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 64974352749 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 87289050794 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 887936500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1414128501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2302065001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 802092250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1441281461 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2243373711 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1690028750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2855409962 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4545438712 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032284 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031796 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017219 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015013 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013530 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007316 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.768833 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.752492 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.385346 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.726609 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.719371 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.304444 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056805 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.061626 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031219 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024496 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023456 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.012480 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028474 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027106 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.014444 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13564.597042 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15408.779055 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14885.547139 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30927.175264 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 39001.498893 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36558.411875 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14781.031485 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20612.346762 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18875.263625 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12049.534870 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12718.922768 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12533.082012 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 24499 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15999.600000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17416.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18505.722380 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21694.423549 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20773.391119 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17968.167892 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21543.997771 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20506.599466 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024105 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023439 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.012573 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028135 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027092 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.014570 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13163.135553 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15040.390210 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14515.543148 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27107.905380 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34133.011724 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31944.684550 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14912.350751 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20706.140677 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18950.062477 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15658.567201 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 29165.855970 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25226.679048 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12226.372215 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12637.002899 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12522.889240 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73250 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13999.750000 # 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average ReadReq mshr uncacheable latency @@ -1701,6 +879,143 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 14506041 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.977027 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 610832898 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14506553 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 42.107377 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9058180500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 497.195368 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.341031 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.440628 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.971085 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.008479 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020392 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 73 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 640265260 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 640265260 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 414440150 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 132748322 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 63644426 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 610832898 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 414440150 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 132748322 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 63644426 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 610832898 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 414440150 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 132748322 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 63644426 # 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number of overall misses +system.cpu0.icache.overall_misses::total 14925692 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 27633797750 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 83140755110 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 110774552860 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 27633797750 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 83140755110 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 110774552860 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 27633797750 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 83140755110 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 110774552860 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 421062246 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 134812630 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 69883714 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 625758590 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 421062246 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 134812630 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 69883714 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 625758590 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 421062246 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 134812630 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 69883714 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 625758590 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015727 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015312 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.089281 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023852 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015727 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015312 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089281 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023852 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015727 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015312 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089281 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023852 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13386.470309 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13325.359418 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7421.736484 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13386.470309 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13325.359418 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7421.736484 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13386.470309 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13325.359418 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7421.736484 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 42469 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 3518 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.071916 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 419022 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 419022 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 419022 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 419022 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 419022 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 419022 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2064308 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 5820266 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 7884574 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 2064308 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 5820266 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 7884574 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 2064308 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 5820266 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 7884574 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 23501092750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 67935136085 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 91436228835 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 23501092750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 67935136085 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 91436228835 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 23501092750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 67935136085 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 91436228835 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015312 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083285 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012600 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015312 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083285 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012600 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015312 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083285 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012600 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11384.489500 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11672.170324 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.850868 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11384.489500 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11672.170324 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.850868 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11384.489500 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11672.170324 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.850868 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1724,25 +1039,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 24842678 # DTB read hits -system.cpu1.dtb.read_misses 30288 # DTB read misses -system.cpu1.dtb.write_hits 22204387 # DTB write hits -system.cpu1.dtb.write_misses 9453 # DTB write misses -system.cpu1.dtb.flush_tlb 1282 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25401715 # DTB read hits +system.cpu1.dtb.read_misses 30145 # DTB read misses +system.cpu1.dtb.write_hits 22878884 # DTB write hits +system.cpu1.dtb.write_misses 9290 # DTB write misses +system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 6426 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 22120 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 6765 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 155 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 21663 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1240 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1295 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2953 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 24872966 # DTB read accesses -system.cpu1.dtb.write_accesses 22213840 # DTB write accesses +system.cpu1.dtb.perms_faults 3011 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25431860 # DTB read accesses +system.cpu1.dtb.write_accesses 22888174 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 47047065 # DTB hits -system.cpu1.dtb.misses 39741 # DTB misses -system.cpu1.dtb.accesses 47086806 # DTB accesses +system.cpu1.dtb.hits 48280599 # DTB hits +system.cpu1.dtb.misses 39435 # DTB misses +system.cpu1.dtb.accesses 48320034 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1764,56 +1079,56 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 131452865 # ITB inst hits -system.cpu1.itb.inst_misses 23431 # ITB inst misses +system.cpu1.itb.inst_hits 134812630 # ITB inst hits +system.cpu1.itb.inst_misses 23831 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1282 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 6426 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 16167 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 6765 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 155 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 16095 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 131476296 # ITB inst accesses -system.cpu1.itb.hits 131452865 # DTB hits -system.cpu1.itb.misses 23431 # DTB misses -system.cpu1.itb.accesses 131476296 # DTB accesses -system.cpu1.numCycles 1282114185 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 134836461 # ITB inst accesses +system.cpu1.itb.hits 134812630 # DTB hits +system.cpu1.itb.misses 23831 # DTB misses +system.cpu1.itb.accesses 134836461 # DTB accesses +system.cpu1.numCycles 1276129163 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 131358204 # Number of instructions committed -system.cpu1.committedOps 154205938 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 141499337 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 128756 # Number of float alu accesses -system.cpu1.num_func_calls 7727196 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 20146536 # number of instructions that are conditional controls -system.cpu1.num_int_insts 141499337 # number of integer instructions -system.cpu1.num_fp_insts 128756 # number of float instructions -system.cpu1.num_int_register_reads 205950168 # number of times the integer registers were read -system.cpu1.num_int_register_writes 112374883 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 204901 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 115300 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 34581843 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 34518712 # number of times the CC registers were written -system.cpu1.num_mem_refs 47044288 # number of memory refs -system.cpu1.num_load_insts 24842081 # Number of load instructions -system.cpu1.num_store_insts 22202207 # Number of store instructions -system.cpu1.num_idle_cycles 1255604442.364680 # Number of idle cycles -system.cpu1.num_busy_cycles 26509742.635320 # Number of busy cycles -system.cpu1.not_idle_fraction 0.020677 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.979323 # Percentage of idle cycles -system.cpu1.Branches 29364446 # Number of branches fetched +system.cpu1.committedInsts 134717323 # Number of instructions committed +system.cpu1.committedOps 158229449 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 145215192 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 135383 # Number of float alu accesses +system.cpu1.num_func_calls 7898602 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 20639469 # number of instructions that are conditional controls +system.cpu1.num_int_insts 145215192 # number of integer instructions +system.cpu1.num_fp_insts 135383 # number of float instructions +system.cpu1.num_int_register_reads 211626069 # number of times the integer registers were read +system.cpu1.num_int_register_writes 115298933 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 217457 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 117636 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 35416182 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 35358802 # number of times the CC registers were written +system.cpu1.num_mem_refs 48278390 # number of memory refs +system.cpu1.num_load_insts 25401257 # Number of load instructions +system.cpu1.num_store_insts 22877133 # Number of store instructions +system.cpu1.num_idle_cycles 1248602360.762588 # Number of idle cycles +system.cpu1.num_busy_cycles 27526802.237412 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021571 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978429 # Percentage of idle cycles +system.cpu1.Branches 30073331 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 106871098 69.26% 69.26% # Class of executed instruction -system.cpu1.op_class::IntMult 352774 0.23% 69.49% # Class of executed instruction -system.cpu1.op_class::IntDiv 14834 0.01% 69.50% # Class of executed instruction +system.cpu1.op_class::IntAlu 109658909 69.26% 69.26% # Class of executed instruction +system.cpu1.op_class::IntMult 355788 0.22% 69.49% # Class of executed instruction +system.cpu1.op_class::IntDiv 13920 0.01% 69.50% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction @@ -1834,28 +1149,28 @@ system.cpu1.op_class::SimdSqrt 0 0.00% 69.50% # Cl system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.50% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 17563 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 17708 0.01% 69.51% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::MemRead 24842081 16.10% 85.61% # Class of executed instruction -system.cpu1.op_class::MemWrite 22202207 14.39% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 25401257 16.04% 85.55% # Class of executed instruction +system.cpu1.op_class::MemWrite 22877133 14.45% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 154300599 # Class of executed instruction +system.cpu1.op_class::total 158324756 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 95476448 # Number of BP lookups -system.cpu2.branchPred.condPredicted 64928073 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 4299413 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 64784895 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 46332623 # Number of BTB hits +system.cpu2.branchPred.lookups 96972708 # Number of BP lookups +system.cpu2.branchPred.condPredicted 66097998 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 4361259 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 65994487 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 47080178 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.517632 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 12285804 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 131917 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.339562 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 12396082 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 131444 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1879,25 +1194,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 77077341 # DTB read hits -system.cpu2.dtb.read_misses 441139 # DTB read misses -system.cpu2.dtb.write_hits 58693711 # DTB write hits -system.cpu2.dtb.write_misses 191612 # DTB write misses -system.cpu2.dtb.flush_tlb 1283 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 77639620 # DTB read hits +system.cpu2.dtb.read_misses 447330 # DTB read misses +system.cpu2.dtb.write_hits 59480935 # DTB write hits +system.cpu2.dtb.write_misses 199454 # DTB write misses +system.cpu2.dtb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 14423 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 383 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 37244 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 88 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 5986 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 14382 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 391 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 38430 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 78 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 6154 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 37589 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 77518480 # DTB read accesses -system.cpu2.dtb.write_accesses 58885323 # DTB write accesses +system.cpu2.dtb.perms_faults 38837 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 78086950 # DTB read accesses +system.cpu2.dtb.write_accesses 59680389 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 135771052 # DTB hits -system.cpu2.dtb.misses 632751 # DTB misses -system.cpu2.dtb.accesses 136403803 # DTB accesses +system.cpu2.dtb.hits 137120555 # DTB hits +system.cpu2.dtb.misses 646784 # DTB misses +system.cpu2.dtb.accesses 137767339 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1919,390 +1234,459 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 69012170 # ITB inst hits -system.cpu2.itb.inst_misses 76652 # ITB inst misses +system.cpu2.itb.inst_hits 70053409 # ITB inst hits +system.cpu2.itb.inst_misses 78615 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1283 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 14423 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 383 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 28880 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 14382 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 391 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 29938 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 143189 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 146701 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 69088822 # ITB inst accesses -system.cpu2.itb.hits 69012170 # DTB hits -system.cpu2.itb.misses 76652 # DTB misses -system.cpu2.itb.accesses 69088822 # DTB accesses -system.cpu2.numCycles 465978411 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 70132024 # ITB inst accesses +system.cpu2.itb.hits 70053409 # DTB hits +system.cpu2.itb.misses 78615 # DTB misses +system.cpu2.itb.accesses 70132024 # DTB accesses +system.cpu2.numCycles 464363800 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 177853142 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 424737263 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 95476448 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 58618427 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 260785808 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 9691059 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 1879827 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 8981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 2007 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 3759830 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 120446 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 3389 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 68846411 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 2635973 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 29904 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 449258797 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.104850 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.350365 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 179489584 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 430854602 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 96972708 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 59476260 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 257591256 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 9826419 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 1844126 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 7503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 2868 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 3763568 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 118840 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 3975 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 69883749 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 2672352 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 30337 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 447734787 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.124399 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.366335 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 344689329 76.72% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 13175573 2.93% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 13441142 2.99% 82.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 9727641 2.17% 84.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 19687409 4.38% 89.20% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 6520571 1.45% 90.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 7057131 1.57% 92.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 6252659 1.39% 93.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 28707342 6.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 341635028 76.30% 76.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 13406310 2.99% 79.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 13636635 3.05% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 9872032 2.20% 84.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 19981367 4.46% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 6599798 1.47% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 7144304 1.60% 92.08% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 6328128 1.41% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 29131185 6.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 449258797 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.204895 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.911496 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 145040906 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 213951941 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 77038080 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 9368936 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 3856816 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 14196524 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 1002861 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 463271274 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 3090116 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 3856816 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 150407499 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 19371841 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 168106415 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 80889236 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 26624521 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 452059055 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 70033 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 1786376 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 1304038 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 13315771 # Number of times rename has blocked due to SQ full -system.cpu2.rename.FullRegisterEvents 3626 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 431846627 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 688168989 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 533483946 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 696961 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 360553438 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 71293189 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 9871202 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 8455912 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 51921554 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 73490892 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 61773042 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 9381483 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 10099562 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 429589038 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 9855415 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 428971223 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 602179 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 55645947 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 38557670 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 233014 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 449258797 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.954842 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.673453 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 447734787 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.208829 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.927838 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 146627317 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 209331987 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 78382912 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 9473245 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 3917341 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 14361500 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 1009950 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 470418171 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 3106090 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 3917341 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 152067726 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 18239112 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 166025180 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 82266415 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 25216691 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 459074168 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 65027 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 1852942 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 1258209 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 11783264 # Number of times rename has blocked due to SQ full +system.cpu2.rename.FullRegisterEvents 3675 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 439034296 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 699577887 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 541505861 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 695779 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 366271083 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 72763213 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 10011965 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 8575733 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 52414102 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 74518711 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 62619461 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 9405778 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 10283621 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 436211457 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 9985811 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 434881060 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 606856 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 56709441 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 39627449 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 236091 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 447734787 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.971292 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.683506 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 283324312 63.06% 63.06% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 67630078 15.05% 78.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 31491211 7.01% 85.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 22481401 5.00% 90.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 17057859 3.80% 93.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 11702074 2.60% 96.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 7876083 1.75% 98.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 4650016 1.04% 99.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 3045763 0.68% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 279611354 62.45% 62.45% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 68418670 15.28% 77.73% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 31957007 7.14% 84.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 22824194 5.10% 89.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 17260103 3.85% 93.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 11876528 2.65% 96.47% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 7949958 1.78% 98.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 4742790 1.06% 99.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 3094183 0.69% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 449258797 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 447734787 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 2154851 25.07% 25.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 17173 0.20% 25.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 1684 0.02% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 3571205 41.55% 66.84% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 2850152 33.16% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2194515 25.29% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 17472 0.20% 25.49% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 1369 0.02% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 1 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 3568581 41.12% 66.62% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 2897037 33.38% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 289729991 67.54% 67.54% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 1034875 0.24% 67.78% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 48976 0.01% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 286 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 48552 0.01% 67.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 78627004 18.33% 86.13% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 59481539 13.87% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 294218561 67.65% 67.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 1060208 0.24% 67.90% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 49487 0.01% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 203 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 49890 0.01% 67.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 79213886 18.22% 86.14% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 60288825 13.86% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 428971223 # Type of FU issued -system.cpu2.iq.rate 0.920582 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 8595065 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.020036 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 1315569237 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 495173501 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 412035990 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 829250 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 394091 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 358547 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 437122606 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 443682 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 3384290 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 434881060 # Type of FU issued +system.cpu2.iq.rate 0.936509 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 8678975 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.019957 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 1325952907 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 503003259 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 418204813 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 829831 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 395434 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 359511 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 443116084 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 443951 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 3398365 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 12185839 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 16415 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 485486 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 6512236 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 12383710 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 15996 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 500564 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 6611339 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 2660066 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 6807125 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 2691934 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 6258076 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 3856816 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10978406 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 6986714 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 439540206 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 1332617 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 73490892 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 61773042 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 8263038 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 174452 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 6729882 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 485486 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 1971342 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1708494 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3679836 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 423953682 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 77064700 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 4393197 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 3917341 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10960428 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 5883186 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 446296417 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 1350381 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 74518711 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 62619461 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 8384922 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 176072 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 5630257 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 500564 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 2018361 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1727301 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3745662 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 429773841 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 77626990 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 4469356 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 95753 # number of nop insts executed -system.cpu2.iew.exec_refs 135758319 # number of memory reference insts executed -system.cpu2.iew.exec_branches 78468818 # Number of branches executed -system.cpu2.iew.exec_stores 58693619 # Number of stores executed -system.cpu2.iew.exec_rate 0.909814 # Inst execution rate -system.cpu2.iew.wb_sent 413267935 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 412394537 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 203830371 # num instructions producing a value -system.cpu2.iew.wb_consumers 353623803 # num instructions consuming a value +system.cpu2.iew.exec_nop 99149 # number of nop insts executed +system.cpu2.iew.exec_refs 137107534 # number of memory reference insts executed +system.cpu2.iew.exec_branches 79765421 # Number of branches executed +system.cpu2.iew.exec_stores 59480544 # Number of stores executed +system.cpu2.iew.exec_rate 0.925511 # Inst execution rate +system.cpu2.iew.wb_sent 419443427 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 418564324 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 206922501 # num instructions producing a value +system.cpu2.iew.wb_consumers 359375214 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.885008 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.576405 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.901372 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575784 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 59831265 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 9622401 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 3310537 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 439132239 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.864557 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.865641 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 60955622 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 9749720 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 3365248 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 437429844 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.880802 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.877626 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 302394835 68.86% 68.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 65341940 14.88% 83.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 24189817 5.51% 89.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 10943430 2.49% 91.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 7703754 1.75% 93.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 4855013 1.11% 94.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 4328620 0.99% 95.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 2957558 0.67% 96.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 16417272 3.74% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 298552711 68.25% 68.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 66327454 15.16% 83.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 24603217 5.62% 89.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 11085486 2.53% 91.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 7951378 1.82% 93.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 4924801 1.13% 94.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 4385642 1.00% 95.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 3037837 0.69% 96.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 16561318 3.79% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 439132239 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 323541810 # Number of instructions committed -system.cpu2.commit.committedOps 379654747 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 437429844 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 328410291 # Number of instructions committed +system.cpu2.commit.committedOps 385289118 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 116565859 # Number of memory references committed -system.cpu2.commit.loads 61305053 # Number of loads committed -system.cpu2.commit.membars 2541238 # Number of memory barriers committed -system.cpu2.commit.branches 72175443 # Number of branches committed -system.cpu2.commit.fp_insts 344817 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 348881889 # Number of committed integer instructions. -system.cpu2.commit.function_calls 9429592 # Number of function calls committed. +system.cpu2.commit.refs 118143123 # Number of memory references committed +system.cpu2.commit.loads 62135001 # Number of loads committed +system.cpu2.commit.membars 2566531 # Number of memory barriers committed +system.cpu2.commit.branches 73369628 # Number of branches committed +system.cpu2.commit.fp_insts 345769 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 353907438 # Number of committed integer instructions. +system.cpu2.commit.function_calls 9528374 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 262221519 69.07% 69.07% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 789172 0.21% 69.28% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 36211 0.01% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 41986 0.01% 69.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 61305053 16.15% 85.44% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 55260806 14.56% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 266264239 69.11% 69.11% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 801904 0.21% 69.32% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 36966 0.01% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 42886 0.01% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 62135001 16.13% 85.46% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 56008122 14.54% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 379654747 # Class of committed instruction -system.cpu2.commit.bw_lim_events 16417272 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 385289118 # Class of committed instruction +system.cpu2.commit.bw_lim_events 16561318 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 859553355 # The number of ROB reads -system.cpu2.rob.rob_writes 889110894 # The number of ROB writes -system.cpu2.timesIdled 2948522 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 16719614 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 99518769709 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 323541810 # Number of Instructions Simulated -system.cpu2.committedOps 379654747 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.440242 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.440242 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.694328 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.694328 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 498743361 # number of integer regfile reads -system.cpu2.int_regfile_writes 295064264 # number of integer regfile writes -system.cpu2.fp_regfile_reads 684469 # number of floating regfile reads -system.cpu2.fp_regfile_writes 420852 # number of floating regfile writes -system.cpu2.cc_regfile_reads 90009576 # number of cc regfile reads -system.cpu2.cc_regfile_writes 90769749 # number of cc regfile writes -system.cpu2.misc_regfile_reads 1656723881 # number of misc regfile reads -system.cpu2.misc_regfile_writes 9715045 # number of misc regfile writes -system.iocache.tags.replacements 115464 # number of replacements -system.iocache.tags.tagsinuse 10.421560 # Cycle average of tags in use +system.cpu2.rob.rob_reads 864512984 # The number of ROB reads +system.cpu2.rob.rob_writes 902807617 # The number of ROB writes +system.cpu2.timesIdled 2960923 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 16629013 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 99452987332 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 328410291 # Number of Instructions Simulated +system.cpu2.committedOps 385289118 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.413975 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.413975 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.707226 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.707226 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 505452117 # number of integer regfile reads +system.cpu2.int_regfile_writes 299365113 # number of integer regfile writes +system.cpu2.fp_regfile_reads 681432 # number of floating regfile reads +system.cpu2.fp_regfile_writes 426556 # number of floating regfile writes +system.cpu2.cc_regfile_reads 91860984 # number of cc regfile reads +system.cpu2.cc_regfile_writes 92633679 # number of cc regfile writes +system.cpu2.misc_regfile_reads 1668736685 # number of misc regfile reads +system.cpu2.misc_regfile_writes 9854923 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40323 # Transaction distribution +system.iobus.trans_dist::ReadResp 40323 # Transaction distribution +system.iobus.trans_dist::WriteReq 136665 # Transaction distribution +system.iobus.trans_dist::WriteResp 30001 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48070 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48090 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156082 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13663000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 7273000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 33000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 16992000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 330247943 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 38409000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36054619 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 144000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115453 # number of replacements +system.iocache.tags.tagsinuse 10.417239 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115480 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13085874574509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.547265 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.874295 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221704 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429643 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651348 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13085938891009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.549977 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.867262 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221874 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429204 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651077 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040224 # Number of tag accesses -system.iocache.tags.data_accesses 1040224 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1039605 # Number of tag accesses +system.iocache.tags.data_accesses 1039605 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8819 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8856 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 65 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 65 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8819 # number of demand (read+write) misses -system.iocache.demand_misses::total 8859 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8808 # number of demand (read+write) misses +system.iocache.demand_misses::total 8848 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8819 # number of overall misses -system.iocache.overall_misses::total 8859 # number of overall misses +system.iocache.overall_misses::realview.ide 8808 # number of overall misses +system.iocache.overall_misses::total 8848 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 2752000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1272471430 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1275223430 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 58617716 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 61369716 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9336377608 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9336377608 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 2752000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1272471430 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1275223430 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 58617716 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 61369716 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 2752000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1272471430 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1275223430 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 58617716 # number of overall miss cycles +system.iocache.overall_miss_latency::total 61369716 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8819 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8856 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106729 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106729 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8819 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8859 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8808 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8848 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8819 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8859 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8808 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8848 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000609 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000609 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -2310,63 +1694,755 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 74378.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 144287.496315 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 143995.418925 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 6655.054042 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 6938.351159 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 87530.728343 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 87530.728343 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 68800 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 144287.496315 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 143946.656508 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 6655.054042 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 6935.998644 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 68800 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 144287.496315 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 143946.656508 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 36080 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 6655.054042 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 6935.998644 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56930 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3735 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7229 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.659973 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.875225 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 16 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 5668 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 5684 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 391 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 407 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 34376 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 34376 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 16 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 5668 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 5684 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 391 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 407 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 16 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 5668 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 5684 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 391 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 407 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1920000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 977655446 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 979575446 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2261356027 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2261356027 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 38284716 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 40204716 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7548587846 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7548587846 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 1920000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 977655446 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 979575446 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 38284716 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 40204716 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 1920000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 977655446 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 979575446 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 38284716 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 40204716 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 0.432432 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.642703 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.641825 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.044391 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.046015 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.322283 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.322283 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.642703 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.641607 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.044391 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.045999 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.642703 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.641607 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.044391 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.045999 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 120000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 172486.846507 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 172339.100281 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 97914.874680 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 98783.085995 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219588.894752 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219588.894752 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 172486.846507 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 172339.100281 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 97914.874680 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 98783.085995 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 172486.846507 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 172339.100281 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 97914.874680 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 98783.085995 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 1295349 # number of replacements +system.l2c.tags.tagsinuse 65279.372199 # Cycle average of tags in use +system.l2c.tags.total_refs 28812912 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1358291 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.212621 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37161.709727 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 165.709328 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 242.089797 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3863.683177 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8425.677492 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 52.724328 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 79.048207 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 858.449063 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3027.055416 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 115.755562 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 187.843721 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2139.828130 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 8959.798251 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.567043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003694 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.058955 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.128566 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000805 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001206 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.013099 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.046189 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001766 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.002866 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032651 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.136716 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996084 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 299 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62643 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 299 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 576 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2774 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4979 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54179 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004562 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.955856 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 273263421 # Number of tag accesses +system.l2c.tags.data_accesses 273263421 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 201117 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 129157 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 6577739 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3133333 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 70837 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 49793 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 2053111 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 984012 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 392546 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 149888 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 5786914 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 2465786 # number of ReadReq hits +system.l2c.ReadReq_hits::total 21994233 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 7869277 # number of Writeback hits +system.l2c.Writeback_hits::total 7869277 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 350049 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 108782 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu2.data 265889 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 724720 # 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average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 464434 # Transaction distribution +system.membus.trans_dist::ReadResp 464434 # Transaction distribution +system.membus.trans_dist::WriteReq 33772 # Transaction distribution +system.membus.trans_dist::WriteResp 33772 # Transaction distribution +system.membus.trans_dist::Writeback 1204397 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 613284 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 613284 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36382 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36386 # Transaction distribution +system.membus.trans_dist::ReadExReq 502275 # Transaction distribution +system.membus.trans_dist::ReadExResp 502275 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122952 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4037051 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4166813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337307 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337307 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4504120 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156082 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159247392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 159417170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14194688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14194688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173611858 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 579 # Total snoops (count) +system.membus.snoop_fanout::samples 2743991 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 2743991 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2743991 # Request fanout histogram +system.membus.reqLayer0.occupancy 42257500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 1290500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 6097591000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 4309666748 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 38158381 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 18 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 22879889 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 22879700 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33772 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33772 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7869277 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1265786 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1231410 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45609 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45616 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2107606 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2107606 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29099470 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28504181 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 848529 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1761011 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 60213191 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 928591700 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1156912126 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3110208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6320128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2094934162 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 368424 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 34177702 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003380 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.058037 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 34062190 99.66% 99.66% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115512 0.34% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 34177702 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 26362663917 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 981000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 35502866905 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 21222039348 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 273701566 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 651522269 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index b5546b4d2..cd3f04231 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,164 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.316753 # Number of seconds simulated -sim_ticks 51316753294500 # Number of ticks simulated -final_tick 51316753294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.358466 # Number of seconds simulated +sim_ticks 51358465585500 # Number of ticks simulated +final_tick 51358465585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136598 # Simulator instruction rate (inst/s) -host_op_rate 160520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7792719388 # Simulator tick rate (ticks/s) -host_mem_usage 670460 # Number of bytes of host memory used -host_seconds 6585.22 # Real time elapsed on the host -sim_insts 899526584 # Number of instructions simulated -sim_ops 1057057755 # Number of ops (including micro ops) simulated +host_inst_rate 124397 # Simulator instruction rate (inst/s) +host_op_rate 146176 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7088870517 # Simulator tick rate (ticks/s) +host_mem_usage 677952 # Number of bytes of host memory used +host_seconds 7244.94 # Real time elapsed on the host +sim_insts 901249371 # Number of instructions simulated +sim_ops 1059038863 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 436032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 324288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 511488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3575488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35714136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 305664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 479488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3431104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 34340592 # Number of bytes read from this memory -system.physmem.bytes_read::total 79118280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3575488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3431104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7006592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 46041344 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 50417380 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 49769472 # Number of bytes written to this memory -system.physmem.bytes_written::total 153054692 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 6813 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 5067 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 7992 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 55867 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 558041 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4776 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 7492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 53611 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 536577 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1236236 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 719396 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 790023 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 777648 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2393731 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 8497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 6319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 9967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 69675 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 695955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 5956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 9344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 66861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 669189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1541763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69675 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 66861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 136536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 897199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 133027 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 982474 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 969848 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2982548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 897199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 141524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 6319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 9967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69675 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1678429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 5956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 9344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 66861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1639037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4524311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1236236 # Number of read requests accepted -system.physmem.writeReqs 2393731 # Number of write requests accepted -system.physmem.readBursts 1236236 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2393731 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 78915968 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 203136 # Total number of bytes read from write queue -system.physmem.bytesWritten 148972800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 79118280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 153054692 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 3174 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 66016 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 38473 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 78969 # Per bank write bursts -system.physmem.perBankRdBursts::1 76054 # Per bank write bursts -system.physmem.perBankRdBursts::2 70113 # Per bank write bursts -system.physmem.perBankRdBursts::3 71416 # Per bank write bursts -system.physmem.perBankRdBursts::4 73251 # Per bank write bursts -system.physmem.perBankRdBursts::5 79391 # Per bank write bursts -system.physmem.perBankRdBursts::6 70957 # Per bank write bursts -system.physmem.perBankRdBursts::7 70585 # Per bank write bursts -system.physmem.perBankRdBursts::8 72320 # Per bank write bursts -system.physmem.perBankRdBursts::9 103108 # Per bank write bursts -system.physmem.perBankRdBursts::10 75527 # Per bank write bursts -system.physmem.perBankRdBursts::11 73923 # Per bank write bursts -system.physmem.perBankRdBursts::12 74067 # Per bank write bursts -system.physmem.perBankRdBursts::13 84199 # Per bank write bursts -system.physmem.perBankRdBursts::14 79405 # Per bank write bursts -system.physmem.perBankRdBursts::15 79777 # Per bank write bursts -system.physmem.perBankWrBursts::0 143281 # Per bank write bursts -system.physmem.perBankWrBursts::1 127790 # Per bank write bursts -system.physmem.perBankWrBursts::2 148899 # Per bank write bursts -system.physmem.perBankWrBursts::3 137605 # Per bank write bursts -system.physmem.perBankWrBursts::4 197374 # Per bank write bursts -system.physmem.perBankWrBursts::5 124383 # Per bank write bursts -system.physmem.perBankWrBursts::6 109194 # Per bank write bursts -system.physmem.perBankWrBursts::7 129383 # Per bank write bursts -system.physmem.perBankWrBursts::8 151210 # Per bank write bursts -system.physmem.perBankWrBursts::9 186118 # Per bank write bursts -system.physmem.perBankWrBursts::10 208778 # Per bank write bursts -system.physmem.perBankWrBursts::11 141342 # Per bank write bursts -system.physmem.perBankWrBursts::12 123729 # Per bank write bursts -system.physmem.perBankWrBursts::13 141617 # Per bank write bursts -system.physmem.perBankWrBursts::14 124170 # Per bank write bursts -system.physmem.perBankWrBursts::15 132827 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 144192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 134400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3960256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 28248856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 172736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 160128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3375488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 26920496 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 423040 # Number of bytes read from this memory +system.physmem.bytes_read::total 63539592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3960256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3375488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7335744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 82068736 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 82089316 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2253 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2100 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 61879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 441396 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2502 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 52742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 420638 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6610 # Number of read requests responded to by this memory +system.physmem.num_reads::total 992819 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1282324 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1284897 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 77110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 550033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 65724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 524169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1237179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 77110 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 65724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 142834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1597959 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1598360 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1597959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 77110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 550434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 65724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 524169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2835539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 992819 # Number of read requests accepted +system.physmem.writeReqs 1909642 # Number of write requests accepted +system.physmem.readBursts 992819 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1909642 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 63506944 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue +system.physmem.bytesWritten 121761344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 63539592 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 122072996 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7111 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 37069 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 60948 # Per bank write bursts +system.physmem.perBankRdBursts::1 60211 # Per bank write bursts +system.physmem.perBankRdBursts::2 58469 # Per bank write bursts +system.physmem.perBankRdBursts::3 57182 # Per bank write bursts +system.physmem.perBankRdBursts::4 59427 # Per bank write bursts +system.physmem.perBankRdBursts::5 69894 # Per bank write bursts +system.physmem.perBankRdBursts::6 60719 # Per bank write bursts +system.physmem.perBankRdBursts::7 60135 # Per bank write bursts +system.physmem.perBankRdBursts::8 57063 # Per bank write bursts +system.physmem.perBankRdBursts::9 84498 # Per bank write bursts +system.physmem.perBankRdBursts::10 60252 # Per bank write bursts +system.physmem.perBankRdBursts::11 64911 # Per bank write bursts +system.physmem.perBankRdBursts::12 58664 # Per bank write bursts +system.physmem.perBankRdBursts::13 62105 # Per bank write bursts +system.physmem.perBankRdBursts::14 58293 # Per bank write bursts +system.physmem.perBankRdBursts::15 59525 # Per bank write bursts +system.physmem.perBankWrBursts::0 119395 # Per bank write bursts +system.physmem.perBankWrBursts::1 117730 # Per bank write bursts +system.physmem.perBankWrBursts::2 117506 # Per bank write bursts +system.physmem.perBankWrBursts::3 117615 # Per bank write bursts +system.physmem.perBankWrBursts::4 116969 # Per bank write bursts +system.physmem.perBankWrBursts::5 124824 # Per bank write bursts +system.physmem.perBankWrBursts::6 116994 # Per bank write bursts +system.physmem.perBankWrBursts::7 119672 # Per bank write bursts +system.physmem.perBankWrBursts::8 117205 # Per bank write bursts +system.physmem.perBankWrBursts::9 123532 # Per bank write bursts +system.physmem.perBankWrBursts::10 118074 # Per bank write bursts +system.physmem.perBankWrBursts::11 121555 # Per bank write bursts +system.physmem.perBankWrBursts::12 115761 # Per bank write bursts +system.physmem.perBankWrBursts::13 122535 # Per bank write bursts +system.physmem.perBankWrBursts::14 116498 # Per bank write bursts +system.physmem.perBankWrBursts::15 116656 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 128 # Number of times write queue was full causing retry -system.physmem.totGap 51316752176000 # Total gap between requests +system.physmem.numWrRetry 94 # Number of times write queue was full causing retry +system.physmem.totGap 51358464467000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1236221 # Read request sizes (log2) +system.physmem.readPktSize::6 992804 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2391158 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 748020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 328495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 109863 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 42754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 432 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1907069 # 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What read queue length does an incoming req see @@ -168,177 +162,207 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 729 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 3111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 2716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 336 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 678102 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 336.067624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.620268 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 366.767956 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 271362 40.02% 40.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 148250 21.86% 61.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55753 8.22% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26626 3.93% 74.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20429 3.01% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13236 1.95% 78.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10909 1.61% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 14852 2.19% 82.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 116685 17.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 678102 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 81261 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.173946 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 173.903253 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 81255 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 3 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 81261 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 81261 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 28.644737 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 24.485973 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.407420 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 56 0.07% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 139 0.17% 0.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 47231 58.12% 58.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 7834 9.64% 68.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 13023 16.03% 84.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 3682 4.53% 88.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 2148 2.64% 91.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 950 1.17% 92.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 2747 3.38% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1058 1.30% 97.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 767 0.94% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 240 0.30% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 341 0.42% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 185 0.23% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 486 0.60% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 8 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 31 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 23 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 18 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 31 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 73 0.09% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 62 0.08% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 51 0.06% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 8 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 17 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 17 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 9 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 7 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 81261 # Writes before turning the bus around for reads -system.physmem.totQLat 27538646010 # Total ticks spent queuing -system.physmem.totMemAccLat 50658558510 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6165310000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22333.55 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 824 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 126686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 112871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 105936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 106364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 92202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 90503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 89684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 85602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4024 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 225 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 619163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 299.223151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 170.216009 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.259099 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 254617 41.12% 41.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146485 23.66% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55354 8.94% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28104 4.54% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20475 3.31% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12983 2.10% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10576 1.71% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9506 1.54% 86.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 81063 13.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 619163 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 77925 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.733693 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 58.402560 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 77917 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 77925 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 77925 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.414771 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.404795 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.389828 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 83 0.11% 0.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 12 0.02% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 10 0.01% 0.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 84 0.11% 0.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 52239 67.04% 67.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2830 3.63% 70.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 709 0.91% 71.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 6561 8.42% 80.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 7338 9.42% 89.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 1031 1.32% 90.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1085 1.39% 92.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1174 1.51% 93.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 800 1.03% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 285 0.37% 95.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 381 0.49% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 214 0.27% 96.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 366 0.47% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 298 0.38% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 251 0.32% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 217 0.28% 97.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 385 0.49% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 175 0.22% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 111 0.14% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 109 0.14% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 293 0.38% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 79 0.10% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 56 0.07% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 98 0.13% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 168 0.22% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 47 0.06% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 31 0.04% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 43 0.06% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 108 0.14% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 28 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 23 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 23 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 29 0.04% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 14 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 15 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 12 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 14 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 22 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 10 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 7 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 16 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 7 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::236-239 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 77925 # Writes before turning the bus around for reads +system.physmem.totQLat 27174725250 # Total ticks spent queuing +system.physmem.totMemAccLat 45780275250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4961480000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27385.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41083.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.54 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46135.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.37 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.42 # Average write queue length when enqueuing -system.physmem.readRowHits 964323 # Number of row buffer hits during reads -system.physmem.writeRowHits 1918333 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.41 # Row buffer hit rate for writes -system.physmem.avgGap 14136974.85 # Average gap between requests -system.physmem.pageHitRate 80.96 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49243370940756 # Time in different power states -system.physmem.memoryStateTime::REF 1713579140000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.84 # Average write queue length when enqueuing +system.physmem.readRowHits 765740 # Number of row buffer hits during reads +system.physmem.writeRowHits 1509913 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.36 # Row buffer hit rate for writes +system.physmem.avgGap 17694799.16 # Average gap between requests +system.physmem.pageHitRate 78.61 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49399135941008 # Time in different power states +system.physmem.memoryStateTime::REF 1714971960000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 359802419244 # Time in different power states +system.physmem.memoryStateTime::ACT 244357347492 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2507478120 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2618973000 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1368167625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1429003125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 4607662800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 5010142800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 7244050320 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 7839445680 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3351760797840 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3351760797840 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1283842483380 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1294175764575 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29663873874750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29654809593000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34315204514835 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34317643720020 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.694001 # Core power per rank (mW) -system.physmem.averagePower::1 668.741533 # Core power per rank (mW) +system.physmem.actEnergy::0 2363029200 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2317843080 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1289351250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1264696125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 3798436200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 3941425800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 6160568400 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 6167767680 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3354485153760 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3354485153760 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1233743623290 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1233089726130 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29732846799750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29733420393750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34334686961850 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34334687006325 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.530261 # Core power per rank (mW) +system.physmem.averagePower::1 668.530262 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory @@ -361,722 +385,22 @@ system.realview.nvmem.bw_total::cpu0.inst 15 # T system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 532705 # Transaction distribution -system.membus.trans_dist::ReadResp 532705 # Transaction distribution -system.membus.trans_dist::WriteReq 33859 # Transaction distribution -system.membus.trans_dist::WriteResp 33859 # Transaction distribution -system.membus.trans_dist::Writeback 719396 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1671762 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1671762 # Transaction distribution -system.membus.trans_dist::UpgradeReq 38473 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 38479 # Transaction distribution -system.membus.trans_dist::ReadExReq 739347 # Transaction distribution -system.membus.trans_dist::ReadExResp 739347 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6390536 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6520668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 228990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6749658 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 224910444 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 225082704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7262528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7262528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 232345232 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2042 # Total snoops (count) -system.membus.snoop_fanout::samples 3647418 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3647418 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3647418 # Request fanout histogram -system.membus.reqLayer0.occupancy 99715500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 54328 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5596000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 23226177977 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 13225855665 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186556779 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 929985 # number of replacements -system.l2c.tags.tagsinuse 64575.668438 # Cycle average of tags in use -system.l2c.tags.total_refs 30861842 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 992077 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 31.108313 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 13810399676500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 34297.192611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 188.067974 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 294.738587 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4135.506905 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 11979.022995 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 180.539676 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 275.280153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3419.385027 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9805.934509 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.523334 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002870 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004497 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063103 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.182785 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002755 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004200 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.052176 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.149627 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.985347 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 456 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 61636 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 436 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2227 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5080 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54047 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.006958 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.940491 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 289012546 # Number of tag accesses -system.l2c.tags.data_accesses 289012546 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 544051 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 184997 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 8073705 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3475971 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 537537 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 184939 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 7954467 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3403637 # number of ReadReq hits -system.l2c.ReadReq_hits::total 24359304 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7101304 # number of Writeback hits -system.l2c.Writeback_hits::total 7101304 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 6521 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 6161 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12682 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 714827 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 684126 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1398953 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 544051 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 184997 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 8073705 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4190798 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 537537 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 184939 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7954467 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4087763 # number of demand (read+write) hits -system.l2c.demand_hits::total 25758257 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 544051 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 184997 # number of overall hits -system.l2c.overall_hits::cpu0.inst 8073705 # number of overall hits -system.l2c.overall_hits::cpu0.data 4190798 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 537537 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 184939 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7954467 # number of overall hits -system.l2c.overall_hits::cpu1.data 4087763 # number of overall hits -system.l2c.overall_hits::total 25758257 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5086 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 8033 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 43375 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 182199 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4792 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 7524 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 45500 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 173082 # number of ReadReq misses -system.l2c.ReadReq_misses::total 469591 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 19389 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18469 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 37858 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 3 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 3 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 376161 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 363798 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 739959 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 5086 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 8033 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 43375 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 558360 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4792 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 7524 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 45500 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 536880 # number of demand (read+write) misses -system.l2c.demand_misses::total 1209550 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 5086 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 8033 # number of overall misses -system.l2c.overall_misses::cpu0.inst 43375 # number of overall misses -system.l2c.overall_misses::cpu0.data 558360 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4792 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 7524 # number of overall misses -system.l2c.overall_misses::cpu1.inst 45500 # number of overall misses -system.l2c.overall_misses::cpu1.data 536880 # number of overall misses -system.l2c.overall_misses::total 1209550 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 402067961 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 620871486 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 3358802499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14928489876 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 371387969 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 584303733 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3543805470 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 14055803105 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 37865532099 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 215945240 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 206928138 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 422873378 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 45998 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 45998 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 91996 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 33150632854 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 32508892128 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 65659524982 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 402067961 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 620871486 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 3358802499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 48079122730 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 371387969 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 584303733 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3543805470 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 46564695233 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 103525057081 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 402067961 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 620871486 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 3358802499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 48079122730 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 371387969 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 584303733 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3543805470 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 46564695233 # number of overall miss cycles -system.l2c.overall_miss_latency::total 103525057081 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 549137 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 193030 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 8117080 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 3658170 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 542329 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 192463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 7999967 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 3576719 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 24828895 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 7101304 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 7101304 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 25910 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 24630 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 50540 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 5 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1090988 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1047924 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2138912 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 549137 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 193030 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 8117080 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 4749158 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 542329 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 192463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 7999967 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 4624643 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 26967807 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 549137 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 193030 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 8117080 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 4749158 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 542329 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 192463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 7999967 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 4624643 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 26967807 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.009262 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.041615 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.005344 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.049806 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.008836 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.039093 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005688 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.048391 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018913 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.748321 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.749858 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.749070 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.600000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.344789 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.347161 # 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average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10027.818041 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.023282 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.869565 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75638.343667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76875.600564 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 76246.636268 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64880.809955 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73632.337498 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65332.835824 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74260.183414 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 73112.083134 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64880.809955 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73632.337498 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65332.835824 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74260.183414 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 73112.083134 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 18 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 25440595 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25432319 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33859 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33859 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7101304 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1671768 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1565098 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 50543 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 50557 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2138912 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2138912 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32275606 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29216023 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 915477 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2586660 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 64993766 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1032811840 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1154800272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3083944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8731728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2199427784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 664547 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 36349119 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003178 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.056284 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 36233600 99.68% 99.68% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115519 0.32% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 36349119 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 52855909091 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2566500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 72684313037 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 43208232692 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 533902381 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1509803178 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40375 # Transaction distribution -system.iobus.trans_dist::ReadResp 40375 # Transaction distribution -system.iobus.trans_dist::WriteReq 136543 # Transaction distribution -system.iobus.trans_dist::WriteResp 136733 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 190 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354216 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492622 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 981411596 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 178989221 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 132719565 # Number of BP lookups -system.cpu0.branchPred.condPredicted 89993236 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5932836 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 90710148 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 64716268 # Number of BTB hits +system.cpu0.branchPred.lookups 131952150 # Number of BP lookups +system.cpu0.branchPred.condPredicted 89649773 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5822015 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 90992883 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 64634149 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.344022 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17452568 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 191045 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.032093 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17244860 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 187476 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1100,25 +424,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 106360367 # DTB read hits -system.cpu0.dtb.read_misses 615971 # DTB read misses -system.cpu0.dtb.write_hits 81393112 # DTB write hits -system.cpu0.dtb.write_misses 266071 # DTB write misses -system.cpu0.dtb.flush_tlb 1087 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 105327476 # DTB read hits +system.cpu0.dtb.read_misses 614604 # DTB read misses +system.cpu0.dtb.write_hits 81433492 # DTB write hits +system.cpu0.dtb.write_misses 261715 # DTB write misses +system.cpu0.dtb.flush_tlb 1084 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 22107 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 543 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56260 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 229 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9041 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 21241 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 54785 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 190 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8902 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 57266 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 106976338 # DTB read accesses -system.cpu0.dtb.write_accesses 81659183 # DTB write accesses +system.cpu0.dtb.perms_faults 53829 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 105942080 # DTB read accesses +system.cpu0.dtb.write_accesses 81695207 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 187753479 # DTB hits -system.cpu0.dtb.misses 882042 # DTB misses -system.cpu0.dtb.accesses 188635521 # DTB accesses +system.cpu0.dtb.hits 186760968 # DTB hits +system.cpu0.dtb.misses 876319 # DTB misses +system.cpu0.dtb.accesses 187637287 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1140,461 +464,760 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 95391690 # ITB inst hits -system.cpu0.itb.inst_misses 104013 # ITB inst misses +system.cpu0.itb.inst_hits 94794688 # ITB inst hits +system.cpu0.itb.inst_misses 101824 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1087 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1084 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 22107 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 543 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 41837 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21241 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 41122 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 207435 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 203923 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 95495703 # ITB inst accesses -system.cpu0.itb.hits 95391690 # DTB hits -system.cpu0.itb.misses 104013 # DTB misses -system.cpu0.itb.accesses 95495703 # DTB accesses -system.cpu0.numCycles 684418323 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 94896512 # ITB inst accesses +system.cpu0.itb.hits 94794688 # DTB hits +system.cpu0.itb.misses 101824 # DTB misses +system.cpu0.itb.accesses 94896512 # DTB accesses +system.cpu0.numCycles 673746678 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 248384937 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 589536301 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 132719565 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 82168836 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 395321090 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13514905 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2556917 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 20977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 5408 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5551519 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 175554 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 1648 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 95166614 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3687085 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 41415 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 658775231 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.047637 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.297009 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 246770894 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 586838334 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 131952150 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81879009 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 386930341 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13253583 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2358226 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 20576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 5110 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5338145 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 169787 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2046 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 94573624 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3603023 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 38939 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 648221646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.060144 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.307830 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 512971129 77.87% 77.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18432133 2.80% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18348661 2.79% 83.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13411814 2.04% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28741584 4.36% 89.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 9038627 1.37% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9794305 1.49% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8428424 1.28% 93.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 39608554 6.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 503028040 77.60% 77.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18376002 2.83% 80.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18277372 2.82% 83.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13314289 2.05% 85.31% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28669690 4.42% 89.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 8974243 1.38% 91.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9730545 1.50% 92.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8410547 1.30% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 39440918 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 658775231 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.193916 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.861368 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 200994103 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 333361407 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 105045785 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 14028144 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5343793 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19697248 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1433030 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 641923192 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4435962 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5343793 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 208785389 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 28964603 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 262496699 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 111103202 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 42079210 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 626316852 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 80050 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2362679 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1879089 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 21911490 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 5199 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 599577423 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 966250594 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 740756106 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 877957 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 502593400 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 96984018 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15462984 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13497488 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 79320336 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 100980804 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 85727659 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13927717 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14882282 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 593862929 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15564372 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 595387827 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 831090 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 76362787 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 53001437 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 356285 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 658775231 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.903780 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.628017 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 648221646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.195848 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.871007 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 200186064 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 323821330 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105067312 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13887509 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5257280 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19546951 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1388336 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 640651678 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4275147 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5257280 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 207892852 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 28836524 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 254594010 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111072647 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 40565977 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 625329125 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 73391 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2369804 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1783636 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 20590537 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 4721 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 598881072 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 965488055 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 739733763 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 970310 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 502829107 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96051965 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15333341 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13384841 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 78497988 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 100792231 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 85691546 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13482087 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14436592 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 593155856 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15408534 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 593869164 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 811141 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 75391106 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 52735595 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 350692 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 648221646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.916151 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.637744 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 423143545 64.23% 64.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 100533840 15.26% 79.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43588427 6.62% 86.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 31078402 4.72% 90.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 23328962 3.54% 94.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 15913876 2.42% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10814135 1.64% 98.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6320463 0.96% 99.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4053581 0.62% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 413675393 63.82% 63.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 99838135 15.40% 79.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43354420 6.69% 85.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 30999055 4.78% 90.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 23185151 3.58% 94.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 15937923 2.46% 96.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 10813303 1.67% 98.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6331141 0.98% 99.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4087125 0.63% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 658775231 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 648221646 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2985575 25.28% 25.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 23079 0.20% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 3324 0.03% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5019003 42.51% 68.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3776946 31.99% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2980479 25.39% 25.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 23946 0.20% 25.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2481 0.02% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 3 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4885958 41.63% 67.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3844513 32.75% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 402885613 67.67% 67.67% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1422777 0.24% 67.91% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 64552 0.01% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 67 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 58868 0.01% 67.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.93% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 108485553 18.22% 86.15% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82470396 13.85% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 402330448 67.75% 67.75% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1450246 0.24% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 67448 0.01% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 71724 0.01% 68.01% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.01% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.01% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 107439270 18.09% 86.11% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82509979 13.89% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 595387827 # Type of FU issued -system.cpu0.iq.rate 0.869918 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11807929 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019832 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1861125914 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 685987174 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 571772727 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1063990 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 505463 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 456200 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 606627126 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 568629 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4761213 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 593869164 # Type of FU issued +system.cpu0.iq.rate 0.881443 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11737380 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019764 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1847356027 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 684092325 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 571253396 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1152468 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 551459 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 500772 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 604990335 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 616209 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4719298 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16799552 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 22497 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 714171 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 9156054 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16584124 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 22051 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 699484 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8981937 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3900719 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 9933744 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3863484 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 8859794 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5343793 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15674856 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 11567544 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 609566615 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1794840 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 100980804 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 85727659 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13194913 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 258499 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 11189475 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 714171 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2685620 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2322794 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5008414 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 588648436 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 106351748 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5872018 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5257280 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15355080 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 11717568 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 608700724 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1772426 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 100792231 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 85691546 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13094550 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 251810 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 11354978 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 699484 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2666409 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2277536 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4943945 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 587171511 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 105317678 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5833659 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 139314 # number of nop insts executed -system.cpu0.iew.exec_refs 187749395 # number of memory reference insts executed -system.cpu0.iew.exec_branches 108957932 # Number of branches executed -system.cpu0.iew.exec_stores 81397647 # Number of stores executed -system.cpu0.iew.exec_rate 0.860071 # Inst execution rate -system.cpu0.iew.wb_sent 573457881 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 572228927 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 281462520 # num instructions producing a value -system.cpu0.iew.wb_consumers 488752044 # num instructions consuming a value +system.cpu0.iew.exec_nop 136334 # number of nop insts executed +system.cpu0.iew.exec_refs 186754203 # number of memory reference insts executed +system.cpu0.iew.exec_branches 108711734 # Number of branches executed +system.cpu0.iew.exec_stores 81436525 # Number of stores executed +system.cpu0.iew.exec_rate 0.871502 # Inst execution rate +system.cpu0.iew.wb_sent 572939308 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 571754168 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 281506422 # num instructions producing a value +system.cpu0.iew.wb_consumers 489082927 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.836081 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575880 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.848619 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575580 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 82137816 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15208087 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4518905 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 644781794 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.817863 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.810443 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 81075036 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15057842 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4452233 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 634439872 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.831521 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.823079 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 449449526 69.71% 69.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 97358122 15.10% 84.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 33578375 5.21% 90.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 14917712 2.31% 92.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10631887 1.65% 93.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6530680 1.01% 94.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5822825 0.90% 95.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3984235 0.62% 96.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22508432 3.49% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 439457438 69.27% 69.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 96886239 15.27% 84.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33460731 5.27% 89.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15060049 2.37% 92.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10644464 1.68% 93.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6550765 1.03% 94.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5894426 0.93% 95.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 4022234 0.63% 96.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22463526 3.54% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 644781794 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 448706085 # Number of instructions committed -system.cpu0.commit.committedOps 527343007 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 634439872 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 448815056 # Number of instructions committed +system.cpu0.commit.committedOps 527549931 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 160752856 # Number of memory references committed -system.cpu0.commit.loads 84181251 # Number of loads committed -system.cpu0.commit.membars 3744837 # Number of memory barriers committed -system.cpu0.commit.branches 100346754 # Number of branches committed -system.cpu0.commit.fp_insts 436641 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 484032213 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13338237 # Number of function calls committed. +system.cpu0.commit.refs 160917716 # Number of memory references committed +system.cpu0.commit.loads 84208107 # Number of loads committed +system.cpu0.commit.membars 3677805 # Number of memory barriers committed +system.cpu0.commit.branches 100249360 # Number of branches committed +system.cpu0.commit.fp_insts 481111 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 484287281 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13244362 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 365400890 69.29% 69.29% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1092025 0.21% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 47793 0.01% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 49443 0.01% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84181251 15.96% 85.48% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 76571605 14.52% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 365417797 69.27% 69.27% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1102287 0.21% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 49909 0.01% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 62180 0.01% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84208107 15.96% 85.46% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 76709609 14.54% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 527343007 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22508432 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 527549931 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22463526 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 1227661689 # The number of ROB reads -system.cpu0.rob.rob_writes 1232973286 # The number of ROB writes -system.cpu0.timesIdled 4104064 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25643092 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 54070741689 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 448706085 # Number of Instructions Simulated -system.cpu0.committedOps 527343007 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.525315 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.525315 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.655602 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.655602 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 693970255 # number of integer regfile reads -system.cpu0.int_regfile_writes 408353798 # number of integer regfile writes -system.cpu0.fp_regfile_reads 822679 # number of floating regfile reads -system.cpu0.fp_regfile_writes 492268 # number of floating regfile writes -system.cpu0.cc_regfile_reads 125884227 # number of cc regfile reads -system.cpu0.cc_regfile_writes 126919674 # number of cc regfile writes -system.cpu0.misc_regfile_reads 2342378074 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15341166 # number of misc regfile writes -system.cpu0.icache.tags.replacements 16116656 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.960235 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 173052626 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16117168 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.737161 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 11668105000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 286.930366 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 225.029869 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.560411 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.439511 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 1216684794 # The number of ROB reads +system.cpu0.rob.rob_writes 1231052317 # The number of ROB writes +system.cpu0.timesIdled 4081993 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25525032 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 47131326354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 448815056 # Number of Instructions Simulated +system.cpu0.committedOps 527549931 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.501168 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.501168 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.666148 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.666148 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 692564361 # number of integer regfile reads +system.cpu0.int_regfile_writes 407943900 # number of integer regfile writes +system.cpu0.fp_regfile_reads 896391 # number of floating regfile reads +system.cpu0.fp_regfile_writes 528896 # number of floating regfile writes +system.cpu0.cc_regfile_reads 125905812 # number of cc regfile reads +system.cpu0.cc_regfile_writes 126977702 # number of cc regfile writes +system.cpu0.misc_regfile_reads 2322757937 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15198906 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10638925 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.983549 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 304517896 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10639437 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.621617 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1654841000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 289.769940 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 222.213609 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.565957 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.434011 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 1345465491 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1345465491 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 79979109 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 80848758 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 160827867 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67346505 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 67891780 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 135238285 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204132 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 199440 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 403572 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 171160 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 153591 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 324751 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1784441 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1798021 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3582462 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2031437 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2062591 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4094028 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 147325614 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 148740538 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 296066152 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 147529746 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 148939978 # number of overall hits +system.cpu0.dcache.overall_hits::total 296469724 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6500737 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 6533272 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 13034009 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 6519313 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 6481267 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 13000580 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 668156 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 654202 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1322358 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 633593 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 607646 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 1241239 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 311874 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 325474 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 637348 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 10 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 13020050 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 13014539 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 26034589 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 13688206 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 13668741 # number of overall misses +system.cpu0.dcache.overall_misses::total 27356947 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 111607932917 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111225009746 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 222832942663 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 259750103307 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 246979475075 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 506729578382 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 25310357673 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 23982059689 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 49292417362 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4526632473 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4625804945 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 9152437418 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 268001 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 294001 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 371358036224 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 358204484821 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 729562521045 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 371358036224 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 358204484821 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 729562521045 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 86479846 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 87382030 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 173861876 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73865818 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 74373047 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 148238865 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 872288 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 853642 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1725930 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 804753 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 761237 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1565990 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2096315 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2123495 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4219810 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2031439 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2062601 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4094040 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 160345664 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 161755077 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 322100741 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 161217952 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 162608719 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 323826671 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075171 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.074767 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.074968 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.088259 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.087145 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.087700 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.765981 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.766366 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766171 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.787314 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.798235 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.792623 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.148772 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153273 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.151037 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000005 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081200 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.080458 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.080827 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.084905 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.084059 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.084480 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17168.504574 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17024.396006 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17096.270431 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39843.171099 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38106.665730 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38977.459343 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39947.344230 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 39467.156353 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39712.269242 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14514.298957 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14212.517574 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14360.188497 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26800.100000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24500.083333 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28522.013066 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27523.409382 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 28022.816917 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27129.781377 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26206.106680 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26668.272635 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 59155859 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 42706 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3724749 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 967 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.881838 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 44.163392 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 8137324 # number of writebacks +system.cpu0.dcache.writebacks::total 8137324 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3661999 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3663033 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 7325032 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5427863 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5389700 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 10817563 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 3334 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3491 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 6825 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 189406 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 198198 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 387604 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9089862 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 9052733 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 18142595 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9089862 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 9052733 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 18142595 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2838738 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2870239 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 5708977 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1091450 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1091567 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 2183017 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 661474 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 648177 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 1309651 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 630259 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 604155 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 1234414 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122468 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 127276 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 249744 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 10 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3930188 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3961806 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7891994 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4591662 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4609983 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 9201645 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43024166867 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 43656462738 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 86680629605 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40600883832 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 38849310828 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 79450194660 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13171462044 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12577725489 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 25749187533 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 23923452719 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 22638090123 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 46561542842 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1614671914 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1630090692 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3244762606 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 247999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 269999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83625050699 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 82505773566 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 166130824265 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 96796512743 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 95083499055 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 191880011798 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2877179750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2839380752 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5716560502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2798393044 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2781680461 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5580073505 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5675572794 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5621061213 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11296634007 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032825 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032836 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014776 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014677 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014726 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758321 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759308 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758809 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.783171 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.793649 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.788264 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058421 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059937 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059184 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024511 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024493 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024502 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028481 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028415 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15156.089384 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15210.044438 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15183.215768 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37199.032326 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35590.404279 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36394.675195 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19912.289892 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19404.769822 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19661.106305 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 37958.129466 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 37470.665844 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 37719.551821 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13184.439315 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12807.526101 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12992.354595 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 24799.900000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22499.916667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21277.620994 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20825.293708 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21050.551263 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21080.931642 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20625.563924 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20852.794451 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 16118591 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.955303 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 173100510 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16119103 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.738843 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13625340000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.422577 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 237.532726 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.535982 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.463931 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999913 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 206428941 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 206428941 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 86457913 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 86594713 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 173052626 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 86457913 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 86594713 # 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number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 160211036 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 161408246 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 321619282 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 161085816 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 162251355 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 323337171 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074846 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.073347 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.074094 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.089892 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.085573 # 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average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29024.056621 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 29035.789077 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 69133267 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 73151 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 4037000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 1206 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.124911 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 60.655887 # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 1565098 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7101304 # number of writebacks -system.cpu0.dcache.writebacks::total 7101304 # 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number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29043542969 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 28669048764 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 57712591733 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1626539446 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1632214456 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3258753902 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 137497 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 93497 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 230994 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 89507595408 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 87428463442 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 176936058850 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 102801556910 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 99759245219 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 202560802129 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3260677254 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2455829253 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5716506507 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3279198543 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2300797457 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5579996000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6539875797 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4756626710 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11296502507 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033263 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032366 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032813 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015059 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014700 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.755601 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758360 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756955 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059522 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060299 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059905 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024887 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024068 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024476 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028855 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027884 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028368 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15462.887815 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15452.055657 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15457.526908 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40555.548912 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41159.303892 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40851.286367 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20112.349754 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19285.529383 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19705.808199 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12808.304888 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13049.155402 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12927.818140 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15277.444444 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18699.400000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16499.571429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22449.342881 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22505.203842 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22476.910456 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22117.008154 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22050.184269 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22084.047493 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 132695624 # Number of BP lookups -system.cpu1.branchPred.condPredicted 90331188 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5850625 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91191115 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 65101533 # Number of BTB hits +system.cpu1.branchPred.lookups 133577738 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90779695 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5949901 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 90899106 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 65330171 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.390215 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17167330 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 185817 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 71.871082 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17378415 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 188946 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1912,25 +1257,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 106438912 # DTB read hits -system.cpu1.dtb.read_misses 617019 # DTB read misses -system.cpu1.dtb.write_hits 81859907 # DTB write hits -system.cpu1.dtb.write_misses 262953 # DTB write misses -system.cpu1.dtb.flush_tlb 1095 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 106064392 # DTB read hits +system.cpu1.dtb.read_misses 610373 # DTB read misses +system.cpu1.dtb.write_hits 82025488 # DTB write hits +system.cpu1.dtb.write_misses 271302 # DTB write misses +system.cpu1.dtb.flush_tlb 1088 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21187 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 524 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 54609 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 175 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8788 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 22250 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 55877 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 229 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8683 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 55422 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 107055931 # DTB read accesses -system.cpu1.dtb.write_accesses 82122860 # DTB write accesses +system.cpu1.dtb.perms_faults 56886 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 106674765 # DTB read accesses +system.cpu1.dtb.write_accesses 82296790 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 188298819 # DTB hits -system.cpu1.dtb.misses 879972 # DTB misses -system.cpu1.dtb.accesses 189178791 # DTB accesses +system.cpu1.dtb.hits 188089880 # DTB hits +system.cpu1.dtb.misses 881675 # DTB misses +system.cpu1.dtb.accesses 188971555 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1952,468 +1297,1193 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 95390425 # ITB inst hits -system.cpu1.itb.inst_misses 103002 # ITB inst misses +system.cpu1.itb.inst_hits 96043604 # ITB inst hits +system.cpu1.itb.inst_misses 103294 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1095 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1088 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21187 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 524 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40480 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 22250 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 41299 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 202732 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 205516 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 95493427 # ITB inst accesses -system.cpu1.itb.hits 95390425 # DTB hits -system.cpu1.itb.misses 103002 # DTB misses -system.cpu1.itb.accesses 95493427 # DTB accesses -system.cpu1.numCycles 672741965 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 96146898 # ITB inst accesses +system.cpu1.itb.hits 96043604 # DTB hits +system.cpu1.itb.misses 103294 # DTB misses +system.cpu1.itb.accesses 96146898 # DTB accesses +system.cpu1.numCycles 675301208 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 246640136 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 590780429 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 132695624 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 82268863 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 386429410 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13305333 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2543340 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 19984 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 4103 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5378147 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 163710 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 1900 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 95165721 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3597908 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 39974 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 647833125 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.067316 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.314702 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 248765293 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 593949498 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 133577738 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 82708586 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 386843919 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13545666 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2415137 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 21504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 4007 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5459319 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 169387 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 1822 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 95816300 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3685759 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 39432 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 650452950 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.068285 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.315163 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 501796172 77.46% 77.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18436133 2.85% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18485753 2.85% 83.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13501389 2.08% 85.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28566375 4.41% 89.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 9032490 1.39% 91.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9749840 1.50% 92.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8516033 1.31% 93.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 39748940 6.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 503682671 77.44% 77.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18498717 2.84% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18563467 2.85% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13597541 2.09% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28733288 4.42% 89.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9099977 1.40% 91.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9814186 1.51% 92.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8571904 1.32% 93.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 39891199 6.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 647833125 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.197246 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.878168 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 200194473 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 322668892 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 105843727 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13827399 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5296426 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19681907 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1375410 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 644487824 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4238266 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5296426 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 207887374 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 28633275 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 252987067 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 111782593 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 41244065 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 628972841 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 101309 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2336709 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1765264 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 21471594 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 4932 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 601986706 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 968135800 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 743741537 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 921788 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 504541868 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 97444838 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15091316 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13114684 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 77880403 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 101483347 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 86159667 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13596196 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14436334 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 596800589 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15137564 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 597335702 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 820098 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 76624490 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53348640 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 353802 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 647833125 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.922052 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.644482 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 650452950 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.197805 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.879533 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 201647992 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 323236826 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 106239229 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13947017 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5379639 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19860273 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1413177 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 647237018 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4350385 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5379639 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 209424655 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 28067269 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 255930457 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 112228565 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 39419858 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 631550288 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 96632 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2287540 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1813390 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19429955 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 4996 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 604714007 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 972949887 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 746652224 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 816553 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 506435319 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 98278683 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15335388 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13342018 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 78452935 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 101901110 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 86377507 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13921613 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14837029 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 598946566 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15418828 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 598874973 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 821829 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 77129289 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53862821 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 352968 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 650452950 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.920705 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.641335 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 412924221 63.74% 63.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 99304245 15.33% 79.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43461350 6.71% 85.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 31157407 4.81% 90.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23474401 3.62% 94.21% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16043027 2.48% 96.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10934122 1.69% 98.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6355751 0.98% 99.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4178601 0.65% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 414330356 63.70% 63.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 100076970 15.39% 79.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43847279 6.74% 85.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31289942 4.81% 90.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23378361 3.59% 94.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16103120 2.48% 96.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 10912961 1.68% 98.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6384879 0.98% 99.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4129082 0.63% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 647833125 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 650452950 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3005947 25.29% 25.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 24266 0.20% 25.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2049 0.02% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 4 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4972015 41.83% 67.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3881824 32.66% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3013028 25.67% 25.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 23161 0.20% 25.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2816 0.02% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 2 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4848351 41.30% 67.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3852019 32.81% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 404183986 67.66% 67.66% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1499549 0.25% 67.92% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 69544 0.01% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 173 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 16 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 70359 0.01% 67.94% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 108574781 18.18% 86.12% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 82937260 13.88% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 405949153 67.79% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1474390 0.25% 68.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 66030 0.01% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 142 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 56962 0.01% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 108207982 18.07% 86.12% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 83120313 13.88% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 597335702 # Type of FU issued -system.cpu1.iq.rate 0.887912 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11886105 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019899 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1854102856 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 688730877 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 574087973 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1107876 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 525044 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 478100 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 608629489 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 592317 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4742542 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 598874973 # Type of FU issued +system.cpu1.iq.rate 0.886826 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11739377 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019602 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1859775645 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 691731884 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 576296193 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 988457 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 469794 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 425393 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 610086136 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 528213 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4764786 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 16809176 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 22821 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 704571 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 9065130 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 16932520 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 21750 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 718636 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 9175857 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3904838 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 9464363 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3929336 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8527630 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5296426 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 15503911 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 11248845 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 612073318 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1785807 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 101483347 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 86159667 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12828539 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 251466 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 10878256 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 704571 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2684400 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2302903 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4987303 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 590552056 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 106426998 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5916414 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5379639 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 15396107 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 10835641 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 614503705 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1815595 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 101901110 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 86377507 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13042378 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 259470 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 10465486 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 718636 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2720399 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2342418 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5062817 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 592014750 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 106053814 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 5994040 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 135165 # number of nop insts executed -system.cpu1.iew.exec_refs 188286771 # number of memory reference insts executed -system.cpu1.iew.exec_branches 109138667 # Number of branches executed -system.cpu1.iew.exec_stores 81859773 # Number of stores executed -system.cpu1.iew.exec_rate 0.877828 # Inst execution rate -system.cpu1.iew.wb_sent 575751009 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 574566073 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 283200911 # num instructions producing a value -system.cpu1.iew.wb_consumers 491579029 # num instructions consuming a value +system.cpu1.iew.exec_nop 138311 # number of nop insts executed +system.cpu1.iew.exec_refs 188080635 # number of memory reference insts executed +system.cpu1.iew.exec_branches 109728675 # Number of branches executed +system.cpu1.iew.exec_stores 82026821 # Number of stores executed +system.cpu1.iew.exec_rate 0.876668 # Inst execution rate +system.cpu1.iew.wb_sent 577948748 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 576721586 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 284303568 # num instructions producing a value +system.cpu1.iew.wb_consumers 493660086 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.854066 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.576105 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.854021 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575910 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 82275122 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14783762 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4494113 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 633863514 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.835692 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.830647 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 82926260 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15065860 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4556436 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 636355753 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.835207 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.827690 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 439265925 69.30% 69.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 95913161 15.13% 84.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33589452 5.30% 89.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15187737 2.40% 92.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10634281 1.68% 93.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6553980 1.03% 94.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5971917 0.94% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 4055542 0.64% 96.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22691519 3.58% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 440359254 69.20% 69.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 97084176 15.26% 84.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33726039 5.30% 89.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15156809 2.38% 92.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10762314 1.69% 93.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6601636 1.04% 94.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5939289 0.93% 95.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 4020807 0.63% 96.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22705429 3.57% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 633863514 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 450820499 # Number of instructions committed -system.cpu1.commit.committedOps 529714748 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 636355753 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 452434315 # Number of instructions committed +system.cpu1.commit.committedOps 531488932 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 161768708 # Number of memory references committed -system.cpu1.commit.loads 84674171 # Number of loads committed -system.cpu1.commit.membars 3651509 # Number of memory barriers committed -system.cpu1.commit.branches 100548022 # Number of branches committed -system.cpu1.commit.fp_insts 459048 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 486295386 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13182426 # Number of function calls committed. +system.cpu1.commit.refs 162170239 # Number of memory references committed +system.cpu1.commit.loads 84968589 # Number of loads committed +system.cpu1.commit.membars 3740598 # Number of memory barriers committed +system.cpu1.commit.branches 101032588 # Number of branches committed +system.cpu1.commit.fp_insts 407528 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 487762142 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13294479 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 366696799 69.23% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1136926 0.21% 69.44% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 51579 0.01% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 60694 0.01% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84674171 15.98% 85.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 77094537 14.55% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 368091914 69.26% 69.26% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1129647 0.21% 69.47% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 49240 0.01% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 47892 0.01% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 84968589 15.99% 85.47% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 77201650 14.53% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 529714748 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22691519 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 531488932 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22705429 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 1219313535 # The number of ROB reads -system.cpu1.rob.rob_writes 1237971918 # The number of ROB writes -system.cpu1.timesIdled 4075861 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 24908840 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 47205322910 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 450820499 # Number of Instructions Simulated -system.cpu1.committedOps 529714748 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.492261 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.492261 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.670124 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.670124 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 696110289 # number of integer regfile reads -system.cpu1.int_regfile_writes 410149745 # number of integer regfile writes -system.cpu1.fp_regfile_reads 853704 # number of floating regfile reads -system.cpu1.fp_regfile_writes 525664 # number of floating regfile writes -system.cpu1.cc_regfile_reads 126283635 # number of cc regfile reads -system.cpu1.cc_regfile_writes 127381072 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2332819849 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14911197 # number of misc regfile writes -system.iocache.tags.replacements 115453 # number of replacements -system.iocache.tags.tagsinuse 10.425607 # Cycle average of tags in use +system.cpu1.rob.rob_reads 1224024924 # The number of ROB reads +system.cpu1.rob.rob_writes 1242947045 # The number of ROB writes +system.cpu1.timesIdled 4091922 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 24848258 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 54236174505 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 452434315 # Number of Instructions Simulated +system.cpu1.committedOps 531488932 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.492595 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.492595 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.669974 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.669974 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 697864723 # number of integer regfile reads +system.cpu1.int_regfile_writes 411651158 # number of integer regfile writes +system.cpu1.fp_regfile_reads 767907 # number of floating regfile reads +system.cpu1.fp_regfile_writes 473740 # number of floating regfile writes +system.cpu1.cc_regfile_reads 126991866 # number of cc regfile reads +system.cpu1.cc_regfile_writes 128085324 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2338745159 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15183498 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40379 # Transaction distribution +system.iobus.trans_dist::ReadResp 40379 # Transaction distribution +system.iobus.trans_dist::WriteReq 136733 # Transaction distribution +system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492654 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 1042420321 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 178996533 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115458 # number of replacements +system.iocache.tags.tagsinuse 10.429567 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13088656983000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544416 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.881191 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221526 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430074 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651600 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13090570223000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.541524 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.888043 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221345 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430503 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651848 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041134 # Number of tag accesses -system.iocache.tags.data_accesses 1041134 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 190 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 190 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8809 # number of demand (read+write) misses -system.iocache.demand_misses::total 8849 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses +system.iocache.demand_misses::total 8853 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8809 # number of overall misses -system.iocache.overall_misses::total 8849 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5533000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1914739091 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1920272091 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8813 # number of overall misses +system.iocache.overall_misses::total 8853 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1921756799 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1927241799 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5872000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1914739091 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1920611091 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5872000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1914739091 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1920611091 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28951102989 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28951102989 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1921756799 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1927580799 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1921756799 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1927580799 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8809 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106854 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106854 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8809 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8849 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8809 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8849 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001778 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.001778 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149540.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217361.685889 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217078.011644 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218059.321343 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217767.434915 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 146800 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 217361.685889 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217042.726975 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 146800 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 217361.685889 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217042.726975 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 52653 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271423.376106 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271423.376106 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 218059.321343 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 217731.932565 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 218059.321343 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 217731.932565 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 227766 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27719 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.590710 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.216963 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8809 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8809 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8849 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # 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mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97540.540541 # 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average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 165346.250539 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165027.361397 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94800 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 165346.250539 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165027.361397 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219418.201464 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219418.201464 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 166045.366277 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 143.176301 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 245.153324 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3359.514416 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 11467.907347 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 184.237244 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 273.594467 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3844.520884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 10027.331371 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.546366 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002185 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003741 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 538 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2779 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5047 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53889 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005234 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 295633480 # Number of tag accesses +system.l2c.tags.data_accesses 295633480 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 538849 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 186240 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 7977279 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3458474 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 540473 # 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number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004164 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011148 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.006154 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.043668 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004969 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.013032 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005515 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.042167 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016706 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.434769 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.404204 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.419810 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.783783 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.782939 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.783351 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.300000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.264312 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.249179 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.256747 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011148 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.006154 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.094230 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004969 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.013032 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005515 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.089360 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.035825 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011148 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.006154 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.094230 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004969 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.013032 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005515 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.089360 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035825 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65897.186275 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 72215.099662 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65814.719791 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72505.449672 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 70810.722538 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38285.106698 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 39123.441561 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38680.157922 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.757738 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10013.677326 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10015.181946 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 44000.333333 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 44000.333333 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85430.788076 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84150.197823 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 84809.519037 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 65897.186275 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80709.806083 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65814.719791 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79908.040638 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 78801.657987 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 65897.186275 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80709.806083 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65814.719791 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79908.040638 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 78801.657987 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 478201 # Transaction distribution +system.membus.trans_dist::ReadResp 478201 # Transaction distribution +system.membus.trans_dist::WriteReq 33860 # Transaction distribution +system.membus.trans_dist::WriteResp 33860 # Transaction distribution +system.membus.trans_dist::Writeback 1282324 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 624745 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 624745 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37074 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 37077 # Transaction distribution +system.membus.trans_dist::ReadExReq 551298 # Transaction distribution +system.membus.trans_dist::ReadExResp 551298 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4264222 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4394358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4729779 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 171538732 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 171711000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14073856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14073856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185784856 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2907 # Total snoops (count) +system.membus.snoop_fanout::samples 2919339 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 2919339 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2919339 # Request fanout histogram +system.membus.reqLayer0.occupancy 99723000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 54328 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5540499 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 18597273982 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 9904783124 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186654467 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 18 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 25451799 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25443711 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33860 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33860 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8137324 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1341081 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1234414 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 46359 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46371 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2149656 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2149656 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32279635 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29644963 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 905204 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2573359 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 65403161 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1032942144 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1201952920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3042880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8674456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2246612400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 665707 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 37265900 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003100 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.055590 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 37150380 99.69% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115520 0.31% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 37265900 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 56232033216 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 3430500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 72693447528 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 43148678653 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 527770675 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1503131700 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16389 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16411 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 3f21941cc..549c3e2c6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,177 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.861029 # Number of seconds simulated -sim_ticks 51861029093000 # Number of ticks simulated -final_tick 51861029093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.781932 # Number of seconds simulated +sim_ticks 51781931516000 # Number of ticks simulated +final_tick 51781931516000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 655308 # Simulator instruction rate (inst/s) -host_op_rate 770071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39176575505 # Simulator tick rate (ticks/s) -host_mem_usage 667356 # Number of bytes of host memory used -host_seconds 1323.78 # Real time elapsed on the host -sim_insts 867480679 # Number of instructions simulated -sim_ops 1019401547 # Number of ops (including micro ops) simulated +host_inst_rate 513884 # Simulator instruction rate (inst/s) +host_op_rate 603881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31103019215 # Simulator tick rate (ticks/s) +host_mem_usage 672564 # Number of bytes of host memory used +host_seconds 1664.85 # Real time elapsed on the host +sim_insts 855540358 # Number of instructions simulated +sim_ops 1005371984 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.ide 385536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 227072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 396672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2360360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 30329136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 251456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 422720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2259596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 29551000 # Number of bytes read from this memory -system.physmem.bytes_read::total 66183548 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2360360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2259596 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4619956 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 36744512 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 49590532 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 50357856 # Number of bytes written to this memory -system.physmem.bytes_written::total 143519396 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 6024 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 3548 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 6198 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 64295 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 473896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 6605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 48299 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 461744 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1074538 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 574133 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 774853 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 789092 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2244742 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 7434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 4378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 7649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 45513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 584816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 8151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 569811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1276171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 45513 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43570 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 708519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 131631 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 956220 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 971015 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2767384 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 708519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 139065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 7649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 45513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1541035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 8151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1540827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4043555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1074538 # Number of read requests accepted -system.physmem.writeReqs 2244742 # Number of write requests accepted -system.physmem.readBursts 1074538 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2244742 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 68582272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 188160 # Total number of bytes read from write queue -system.physmem.bytesWritten 138957696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 66183548 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 143519396 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2940 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 73507 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 34757 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 71255 # Per bank write bursts -system.physmem.perBankRdBursts::1 63640 # Per bank write bursts -system.physmem.perBankRdBursts::2 66612 # Per bank write bursts -system.physmem.perBankRdBursts::3 61740 # Per bank write bursts -system.physmem.perBankRdBursts::4 60545 # Per bank write bursts -system.physmem.perBankRdBursts::5 71198 # Per bank write bursts -system.physmem.perBankRdBursts::6 58053 # Per bank write bursts -system.physmem.perBankRdBursts::7 57022 # Per bank write bursts -system.physmem.perBankRdBursts::8 61158 # Per bank write bursts -system.physmem.perBankRdBursts::9 112029 # Per bank write bursts -system.physmem.perBankRdBursts::10 66876 # Per bank write bursts -system.physmem.perBankRdBursts::11 66235 # Per bank write bursts -system.physmem.perBankRdBursts::12 62785 # Per bank write bursts -system.physmem.perBankRdBursts::13 68778 # Per bank write bursts -system.physmem.perBankRdBursts::14 63805 # Per bank write bursts -system.physmem.perBankRdBursts::15 59867 # Per bank write bursts -system.physmem.perBankWrBursts::0 127784 # Per bank write bursts -system.physmem.perBankWrBursts::1 113302 # Per bank write bursts -system.physmem.perBankWrBursts::2 227736 # Per bank write bursts -system.physmem.perBankWrBursts::3 110987 # Per bank write bursts -system.physmem.perBankWrBursts::4 128170 # Per bank write bursts -system.physmem.perBankWrBursts::5 133310 # Per bank write bursts -system.physmem.perBankWrBursts::6 113658 # Per bank write bursts -system.physmem.perBankWrBursts::7 104648 # Per bank write bursts -system.physmem.perBankWrBursts::8 114567 # Per bank write bursts -system.physmem.perBankWrBursts::9 129854 # Per bank write bursts -system.physmem.perBankWrBursts::10 127393 # Per bank write bursts -system.physmem.perBankWrBursts::11 118149 # Per bank write bursts -system.physmem.perBankWrBursts::12 133562 # Per bank write bursts -system.physmem.perBankWrBursts::13 181801 # Per bank write bursts -system.physmem.perBankWrBursts::14 180172 # Per bank write bursts -system.physmem.perBankWrBursts::15 126121 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 107200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 102528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2434152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20994800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 96832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 103680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2545804 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 20458904 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 379200 # Number of bytes read from this memory +system.physmem.bytes_read::total 47223100 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2434152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2545804 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4979956 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68447104 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory +system.physmem.bytes_written::total 68467684 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1675 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1602 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 65448 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 328047 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1513 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1620 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 52771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 319680 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 5925 # Number of read requests responded to by this memory +system.physmem.num_reads::total 778281 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1069486 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1072059 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 47008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 405446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 395097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 911961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 47008 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49164 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 96172 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1321834 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1322231 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1321834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 47008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 405447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 395495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2234192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 778281 # Number of read requests accepted +system.physmem.writeReqs 1672780 # Number of write requests accepted +system.physmem.readBursts 778281 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1672780 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 49778368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31616 # Total number of bytes read from write queue +system.physmem.bytesWritten 106609920 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 47223100 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 106913828 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 494 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6998 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 34417 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 49121 # Per bank write bursts +system.physmem.perBankRdBursts::1 48968 # Per bank write bursts +system.physmem.perBankRdBursts::2 43998 # Per bank write bursts +system.physmem.perBankRdBursts::3 44044 # Per bank write bursts +system.physmem.perBankRdBursts::4 46923 # Per bank write bursts +system.physmem.perBankRdBursts::5 50978 # Per bank write bursts +system.physmem.perBankRdBursts::6 43709 # Per bank write bursts +system.physmem.perBankRdBursts::7 43367 # Per bank write bursts +system.physmem.perBankRdBursts::8 43043 # Per bank write bursts +system.physmem.perBankRdBursts::9 89491 # Per bank write bursts +system.physmem.perBankRdBursts::10 47224 # Per bank write bursts +system.physmem.perBankRdBursts::11 49584 # Per bank write bursts +system.physmem.perBankRdBursts::12 42821 # Per bank write bursts +system.physmem.perBankRdBursts::13 45810 # Per bank write bursts +system.physmem.perBankRdBursts::14 42383 # Per bank write bursts +system.physmem.perBankRdBursts::15 46323 # Per bank write bursts +system.physmem.perBankWrBursts::0 104557 # Per bank write bursts +system.physmem.perBankWrBursts::1 105414 # Per bank write bursts +system.physmem.perBankWrBursts::2 105583 # Per bank write bursts +system.physmem.perBankWrBursts::3 103819 # Per bank write bursts +system.physmem.perBankWrBursts::4 104348 # Per bank write bursts +system.physmem.perBankWrBursts::5 108141 # Per bank write bursts +system.physmem.perBankWrBursts::6 101114 # Per bank write bursts +system.physmem.perBankWrBursts::7 100245 # Per bank write bursts +system.physmem.perBankWrBursts::8 99850 # Per bank write bursts +system.physmem.perBankWrBursts::9 106510 # Per bank write bursts +system.physmem.perBankWrBursts::10 102540 # Per bank write bursts +system.physmem.perBankWrBursts::11 107777 # Per bank write bursts +system.physmem.perBankWrBursts::12 103459 # Per bank write bursts +system.physmem.perBankWrBursts::13 105336 # Per bank write bursts +system.physmem.perBankWrBursts::14 101779 # Per bank write bursts +system.physmem.perBankWrBursts::15 105308 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 51861026536500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 51781928959500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1031422 # Read request sizes (log2) +system.physmem.readPktSize::6 735165 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2242169 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1023941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 42084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 41 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1670207 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 745946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 26414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 89 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 38 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 634955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.856851 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.109909 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.606066 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 251774 39.65% 39.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 143572 22.61% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53819 8.48% 70.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28426 4.48% 75.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19160 3.02% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 14370 2.26% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10671 1.68% 82.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 11114 1.75% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 102049 16.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 634955 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 109417 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 9.793551 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 155.538286 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 109409 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-6143 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::18432-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 109417 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 109417 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.843480 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.459226 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 5.174824 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 51 0.05% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 17 0.02% 0.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 14 0.01% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 145 0.13% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 52162 47.67% 47.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 51235 46.83% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 1984 1.81% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1760 1.61% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 951 0.87% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 159 0.15% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 147 0.13% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 71 0.06% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 99 0.09% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 20 0.02% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 21 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 18 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 372 0.34% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 33 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 39 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 36 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 9 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 9 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 109417 # Writes before turning the bus around for reads -system.physmem.totQLat 11994975500 # Total ticks spent queuing -system.physmem.totMemAccLat 32087438000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5357990000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11193.54 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 1607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1486 # 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What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 531423 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.281520 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.194093 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.137010 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 219913 41.38% 41.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 131435 24.73% 66.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44338 8.34% 74.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23886 4.49% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15966 3.00% 81.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10709 2.02% 83.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7995 1.50% 85.48% # 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Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 70 0.09% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 53 0.07% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 161 0.20% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 11 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 23 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 15 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 11 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 80476 # Writes before turning the bus around for reads +system.physmem.totQLat 9983720499 # Total ticks spent queuing +system.physmem.totMemAccLat 24567226749 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3888935000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12836.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29943.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31586.06 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.91 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.58 # Average write queue length when enqueuing -system.physmem.readRowHits 810923 # Number of row buffer hits during reads -system.physmem.writeRowHits 1796931 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.76 # Row buffer hit rate for writes -system.physmem.avgGap 15624179.50 # Average gap between requests -system.physmem.pageHitRate 80.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49513780638000 # Time in different power states -system.physmem.memoryStateTime::REF 1731753660000 # Time in different power states +system.physmem.avgWrQLen 10.17 # Average write queue length when enqueuing +system.physmem.readRowHits 580589 # Number of row buffer hits during reads +system.physmem.writeRowHits 1331554 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.94 # Row buffer hit rate for writes +system.physmem.avgGap 21126332.21 # Average gap between requests +system.physmem.pageHitRate 78.25 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49696712332000 # Time in different power states +system.physmem.memoryStateTime::REF 1729112320000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 615493469500 # Time in different power states +system.physmem.memoryStateTime::ACT 356106481500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2375299080 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2424960720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1296046125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1323143250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3978491400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 4379902800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 6866175600 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 7203291120 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3387310158960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3387310158960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1391264257590 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1403130352860 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29896208916750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29885800061250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34689299345505 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34691571870960 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.889557 # Core power per rank (mW) -system.physmem.averagePower::1 668.933377 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 477149 # Transaction distribution -system.membus.trans_dist::ReadResp 477149 # Transaction distribution -system.membus.trans_dist::WriteReq 33873 # Transaction distribution -system.membus.trans_dist::WriteResp 33873 # Transaction distribution -system.membus.trans_dist::Writeback 574133 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1668036 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1668036 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34762 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 34763 # Transaction distribution -system.membus.trans_dist::ReadExReq 634040 # Transaction distribution -system.membus.trans_dist::ReadExResp 634040 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5908571 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6038767 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228229 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 228229 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6266996 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 202490912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 202661260 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7212032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7212032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 209873292 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2859 # Total snoops (count) -system.membus.snoop_fanout::samples 3311225 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3311225 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3311225 # Request fanout histogram -system.membus.reqLayer0.occupancy 107353000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5576998 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 22591732739 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 12337625717 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186623209 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 742012 # number of replacements -system.l2c.tags.tagsinuse 64270.398590 # Cycle average of tags in use -system.l2c.tags.total_refs 26902368 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 803524 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 33.480478 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 13975543266000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37175.370722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 164.612464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 268.035680 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3943.940555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8908.960135 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 136.845941 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 225.029794 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3060.985707 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10386.617592 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.567251 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002512 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004090 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.060180 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.135940 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002088 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003434 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.046707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.158487 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.980688 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 429 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 61083 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 418 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1800 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5332 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53777 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.006546 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.932053 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 254875429 # Number of tag accesses -system.l2c.tags.data_accesses 254875429 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 223794 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 158122 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 6853057 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3117827 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 234015 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 160485 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 6849994 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3144760 # number of ReadReq hits -system.l2c.ReadReq_hits::total 20742054 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 6657868 # number of Writeback hits -system.l2c.Writeback_hits::total 6657868 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 4874 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5098 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9972 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 711006 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 709189 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1420195 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 223794 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 158122 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6853057 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3828833 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 234015 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 160485 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6849994 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3853949 # number of demand (read+write) hits -system.l2c.demand_hits::total 22162249 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 223794 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 158122 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6853057 # number of overall hits -system.l2c.overall_hits::cpu0.data 3828833 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 234015 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 160485 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6849994 # number of overall hits -system.l2c.overall_hits::cpu1.data 3853949 # number of overall hits -system.l2c.overall_hits::total 22162249 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3548 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 6198 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 35053 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 148459 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3929 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 6605 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 34440 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 153129 # number of ReadReq misses -system.l2c.ReadReq_misses::total 391361 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17026 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17173 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 34199 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 325694 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 308906 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 634600 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3548 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 6198 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 35053 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 474153 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3929 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 6605 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 34440 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 462035 # number of demand (read+write) misses -system.l2c.demand_misses::total 1025961 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3548 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 6198 # 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number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 2549880993 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 11342604999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 29116529488 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 204473722 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 203951249 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 408424971 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 23499 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 23499 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 23498160740 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 22115873200 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 45614033940 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 271265250 # 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number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1524532500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4929366250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 724437500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5525716252 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 12704052502 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.015606 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.037719 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.005089 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045452 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.016512 # 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mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.308839 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.015606 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.037719 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005089 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.110192 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.016512 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.039530 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005003 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.107052 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.044245 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.015606 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.037719 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005089 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.110192 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.016512 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.039530 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005003 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.107052 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.044245 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64077.156144 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64393.877057 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61448.385359 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61921.392452 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64551.094426 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61368.888124 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61488.721934 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61808.552748 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.024727 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.852093 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.444487 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59385.087720 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58837.681366 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 59118.625213 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64077.156144 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64393.877057 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61448.385359 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 60179.213802 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64551.094426 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61368.888124 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59716.297036 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 60144.719509 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64077.156144 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64393.877057 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61448.385359 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 60179.213802 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64551.094426 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61368.888124 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59716.297036 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60144.719509 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 18 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.physmem.actEnergy::0 2031447600 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 1986110280 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1108428750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1083691125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 2894642400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 3172057200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 5399272080 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 5394982320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3382143697920 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3382143697920 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1286313063165 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1285469654400 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29940811051500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29941550883750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34620701603415 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34620801076995 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.586590 # Core power per rank (mW) +system.physmem.averagePower::1 668.588511 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 21596881 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 21588675 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33873 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33873 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 6657868 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1668053 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1561372 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 44174 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 44175 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2054795 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2054795 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 27631338 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27242891 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 786774 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1184296 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 56845299 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 881615316 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1077879160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2651280 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3722288 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 1965868044 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 493907 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 31944858 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003617 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.060036 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 31829300 99.64% 99.64% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115558 0.36% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 31944858 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 48864007000 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 3007500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 62042103256 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 39821087024 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 456077500 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 719536250 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40403 # Transaction distribution -system.iobus.trans_dist::ReadResp 40403 # Transaction distribution -system.iobus.trans_dist::WriteReq 136728 # Transaction distribution -system.iobus.trans_dist::WriteResp 136733 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 5 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 981115277 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179046791 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1051,25 +383,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 81298671 # DTB read hits -system.cpu0.dtb.read_misses 94598 # DTB read misses -system.cpu0.dtb.write_hits 74077534 # DTB write hits -system.cpu0.dtb.write_misses 29691 # DTB write misses -system.cpu0.dtb.flush_tlb 51863 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 80391901 # DTB read hits +system.cpu0.dtb.read_misses 93388 # DTB read misses +system.cpu0.dtb.write_hits 73043030 # DTB write hits +system.cpu0.dtb.write_misses 28813 # DTB write misses +system.cpu0.dtb.flush_tlb 51784 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 19908 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 526 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 72449 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 20238 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 514 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 70641 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4385 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4105 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9644 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 81393269 # DTB read accesses -system.cpu0.dtb.write_accesses 74107225 # DTB write accesses +system.cpu0.dtb.perms_faults 9619 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 80485289 # DTB read accesses +system.cpu0.dtb.write_accesses 73071843 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 155376205 # DTB hits -system.cpu0.dtb.misses 124289 # DTB misses -system.cpu0.dtb.accesses 155500494 # DTB accesses +system.cpu0.dtb.hits 153434931 # DTB hits +system.cpu0.dtb.misses 122201 # DTB misses +system.cpu0.dtb.accesses 153557132 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1091,480 +423,368 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 433719693 # ITB inst hits -system.cpu0.itb.inst_misses 76771 # ITB inst misses +system.cpu0.itb.inst_hits 427471663 # ITB inst hits +system.cpu0.itb.inst_misses 76376 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51863 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51784 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 19908 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 526 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 53078 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 20238 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 514 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 52019 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 433796464 # ITB inst accesses -system.cpu0.itb.hits 433719693 # DTB hits -system.cpu0.itb.misses 76771 # DTB misses -system.cpu0.itb.accesses 433796464 # DTB accesses -system.cpu0.numCycles 51861670459 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 427548039 # ITB inst accesses +system.cpu0.itb.hits 427471663 # DTB hits +system.cpu0.itb.misses 76376 # DTB misses +system.cpu0.itb.accesses 427548039 # DTB accesses +system.cpu0.numCycles 51782412762 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 433465167 # Number of instructions committed -system.cpu0.committedOps 509426348 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 467950836 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 437595 # Number of float alu accesses -system.cpu0.num_func_calls 25817816 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 66030471 # number of instructions that are conditional controls -system.cpu0.num_int_insts 467950836 # number of integer instructions -system.cpu0.num_fp_insts 437595 # number of float instructions -system.cpu0.num_int_register_reads 681169150 # number of times the integer registers were read -system.cpu0.num_int_register_writes 371166205 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 709571 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 361724 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 113513031 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 113190912 # number of times the CC registers were written -system.cpu0.num_mem_refs 155365727 # number of memory refs -system.cpu0.num_load_insts 81295009 # Number of load instructions -system.cpu0.num_store_insts 74070718 # Number of store instructions -system.cpu0.num_idle_cycles 50261080538.032112 # Number of idle cycles -system.cpu0.num_busy_cycles 1600589920.967886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.030863 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.969137 # Percentage of idle cycles -system.cpu0.Branches 96751437 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 353168573 69.29% 69.29% # Class of executed instruction -system.cpu0.op_class::IntMult 1074186 0.21% 69.50% # Class of executed instruction -system.cpu0.op_class::IntDiv 48850 0.01% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 52802 0.01% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::MemRead 81295009 15.95% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 74070718 14.53% 100.00% # Class of executed instruction +system.cpu0.committedInsts 427217866 # Number of instructions committed +system.cpu0.committedOps 502133426 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 461356318 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 442453 # Number of float alu accesses +system.cpu0.num_func_calls 25480565 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 64997329 # number of instructions that are conditional controls +system.cpu0.num_int_insts 461356318 # number of integer instructions +system.cpu0.num_fp_insts 442453 # number of float instructions +system.cpu0.num_int_register_reads 669433821 # number of times the integer registers were read +system.cpu0.num_int_register_writes 365789159 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 711452 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 379824 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 111391626 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 111077654 # number of times the CC registers were written +system.cpu0.num_mem_refs 153423964 # number of memory refs +system.cpu0.num_load_insts 80387324 # Number of load instructions +system.cpu0.num_store_insts 73036640 # Number of store instructions +system.cpu0.num_idle_cycles 50249111943.842865 # Number of idle cycles +system.cpu0.num_busy_cycles 1533300818.157139 # Number of busy cycles +system.cpu0.not_idle_fraction 0.029610 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.970390 # Percentage of idle cycles +system.cpu0.Branches 95379703 # Number of branches fetched +system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 347836061 69.23% 69.23% # Class of executed instruction +system.cpu0.op_class::IntMult 1052847 0.21% 69.44% # Class of executed instruction +system.cpu0.op_class::IntDiv 47944 0.01% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 6 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 5 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 9 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 55653 0.01% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::MemRead 80387324 16.00% 85.46% # Class of executed instruction +system.cpu0.op_class::MemWrite 73036640 14.54% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 509710139 # Class of executed instruction +system.cpu0.op_class::total 502416489 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16204 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 13772027 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.894677 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 854244882 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13772539 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 62.025229 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 31522505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 257.415454 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 254.479223 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.502765 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.497030 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999794 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 881789970 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 881789970 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 426831583 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 427413299 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 854244882 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 426831583 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 427413299 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 854244882 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 426831583 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 427413299 # number of overall hits -system.cpu0.icache.overall_hits::total 854244882 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6888110 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 6884434 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 13772544 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6888110 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 6884434 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 13772544 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6888110 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 6884434 # number of overall misses -system.cpu0.icache.overall_misses::total 13772544 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92034347501 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 91949004755 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 183983352256 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 92034347501 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 91949004755 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 183983352256 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 92034347501 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 91949004755 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 183983352256 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 433719693 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 434297733 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 868017426 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 433719693 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 434297733 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 868017426 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 433719693 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 434297733 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 868017426 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015881 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015852 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015867 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015881 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015852 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015867 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015881 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015852 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015867 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13361.335330 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13356.073245 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13358.704990 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13361.335330 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13356.073245 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13358.704990 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13361.335330 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13356.073245 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13358.704990 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6888110 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6884434 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 13772544 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6888110 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 6884434 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 13772544 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6888110 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 6884434 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 13772544 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 78245563999 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 78167770745 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 156413334744 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 78245563999 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 78167770745 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 156413334744 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 78245563999 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 78167770745 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 156413334744 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1919614500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 912090000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2831704500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1919614500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 912090000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 2831704500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015881 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015852 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015867 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015881 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015852 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.015867 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015881 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015852 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.015867 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11359.511390 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11354.277018 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11356.894902 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11359.511390 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11354.277018 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11356.894902 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11359.511390 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11354.277018 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11356.894902 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 9844382 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.969698 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 301160300 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9844894 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.590507 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 16160 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 9666641 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.969685 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 297154926 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9667153 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.738618 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 3092948250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 231.008949 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 280.960750 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.451189 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.548751 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 283.466253 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 228.503431 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.553645 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.446296 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1254251724 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1254251724 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 76026969 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 76417394 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 152444363 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 70302658 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 70301847 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 140604505 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 192417 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 194709 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 387126 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 774852 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 786520 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 1561372 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1759844 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1765909 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3525753 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1907304 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1911679 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3818983 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 146329627 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 146719241 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 293048868 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 146522044 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 146913950 # number of overall hits -system.cpu0.dcache.overall_hits::total 293435994 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2535096 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2582985 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 5118081 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1068169 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1052040 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2120209 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 619845 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 606565 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1226410 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148352 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 146540 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 294892 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1237347722 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1237347722 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75260834 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 75246301 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 150507135 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69349664 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 69346777 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 138696441 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190562 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191577 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 382139 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 171619 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 160816 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 332435 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1711920 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1739353 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3451273 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1857030 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1885244 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3742274 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 144610498 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 144593078 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 289203576 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 144801060 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 144784655 # number of overall hits +system.cpu0.dcache.overall_hits::total 289585715 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2479823 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2539735 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 5019558 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1027548 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1051512 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2079060 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 586953 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 604316 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1191269 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 612872 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 613029 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3004117998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5728220998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2593769750 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2980348000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5574117750 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5317872750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5984465998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11302338748 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032238 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032663 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032451 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014832 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014580 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014706 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762894 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.756761 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759849 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059686 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058128 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058906 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3493451 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3577376 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7070827 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4080259 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4181502 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 8261761 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 33166863497 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 33981034998 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 67147898495 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25195325118 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 25212990469 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 50408315587 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 8922621248 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 8744886500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17667507748 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 12346009492 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12314345000 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 24660354492 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1340334000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1349733250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2690067250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 73000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 73000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58362188615 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 59194025467 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 117556214082 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 67284809863 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 67938911967 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 135223721830 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2674522248 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3054322749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5728844997 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2557892750 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3016153500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5574046250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5232414998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6070476249 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11302891247 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031850 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032613 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032232 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014456 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014780 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014618 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754722 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759054 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756914 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.781235 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.792186 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786673 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059093 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059494 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023953 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024081 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024017 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027935 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027965 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027950 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13760.451596 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13798.852093 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13779.830690 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31087.495244 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30276.252568 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30685.397593 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15177.486404 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15260.974681 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15218.777808 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12055.040696 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12230.837216 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12141.873909 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24499 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18867.875352 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18533.420400 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18699.966333 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18324.815005 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18063.990320 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18194.153896 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023586 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024141 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023864 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028067 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027736 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13394.918697 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13394.866508 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13394.892286 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24765.081360 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24231.470524 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24495.276732 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15205.350384 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14475.269232 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14835.001560 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 20144.515481 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20087.703844 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20116.106025 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12043.832219 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12110.444407 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12077.162836 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 73000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16706.170665 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16546.772122 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16625.525428 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16490.328154 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16247.490009 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16367.421162 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1575,6 +795,136 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 13477112 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.892486 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 842591946 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13477624 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 62.517840 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 32076200250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.322157 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 270.570329 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471332 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.528458 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999790 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 869547204 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 869547204 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 420727456 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 421864490 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 842591946 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 420727456 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 421864490 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 842591946 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 420727456 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 421864490 # number of overall hits +system.cpu0.icache.overall_hits::total 842591946 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6744207 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 6733422 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 13477629 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6744207 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 6733422 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 13477629 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6744207 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 6733422 # number of overall misses +system.cpu0.icache.overall_misses::total 13477629 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 90268756253 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 90304288753 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 180573045006 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 90268756253 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 90304288753 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 180573045006 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 90268756253 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 90304288753 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 180573045006 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 427471663 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 428597912 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 856069575 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 427471663 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 428597912 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 856069575 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 427471663 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 428597912 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 856069575 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015777 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015710 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015744 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015777 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015710 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015744 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015777 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015710 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015744 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13384.636067 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13411.351428 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13397.983058 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13384.636067 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13411.351428 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13397.983058 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13384.636067 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13411.351428 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13397.983058 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6744207 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6733422 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 13477629 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6744207 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 6733422 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 13477629 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6744207 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 6733422 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 13477629 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 76767439747 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 76823488247 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 153590927994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 76767439747 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 76823488247 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 153590927994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 76767439747 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 76823488247 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 153590927994 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1919614500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 912090000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2831704500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1919614500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 912090000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 2831704500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015777 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015710 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015744 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015777 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015710 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.015744 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015777 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015710 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.015744 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11382.722942 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11409.278707 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11395.990199 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11382.722942 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11409.278707 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11395.990199 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11382.722942 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11409.278707 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11395.990199 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1598,25 +948,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 81731723 # DTB read hits -system.cpu1.dtb.read_misses 99102 # DTB read misses -system.cpu1.dtb.write_hits 74078403 # DTB write hits -system.cpu1.dtb.write_misses 30075 # DTB write misses -system.cpu1.dtb.flush_tlb 51867 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 80485889 # DTB read hits +system.cpu1.dtb.read_misses 94650 # DTB read misses +system.cpu1.dtb.write_hits 73083689 # DTB write hits +system.cpu1.dtb.write_misses 28922 # DTB write misses +system.cpu1.dtb.flush_tlb 51788 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 20925 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 19698 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 72169 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 69957 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4438 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4240 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9782 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 81830825 # DTB read accesses -system.cpu1.dtb.write_accesses 74108478 # DTB write accesses +system.cpu1.dtb.perms_faults 9564 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 80580539 # DTB read accesses +system.cpu1.dtb.write_accesses 73112611 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 155810126 # DTB hits -system.cpu1.dtb.misses 129177 # DTB misses -system.cpu1.dtb.accesses 155939303 # DTB accesses +system.cpu1.dtb.hits 153569578 # DTB hits +system.cpu1.dtb.misses 123572 # DTB misses +system.cpu1.dtb.accesses 153693150 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1638,224 +988,916 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 434297733 # ITB inst hits -system.cpu1.itb.inst_misses 78021 # ITB inst misses +system.cpu1.itb.inst_hits 428597912 # ITB inst hits +system.cpu1.itb.inst_misses 76336 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51867 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51788 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 20925 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 19698 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 53659 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 51781 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 434375754 # ITB inst accesses -system.cpu1.itb.hits 434297733 # DTB hits -system.cpu1.itb.misses 78021 # DTB misses -system.cpu1.itb.accesses 434375754 # DTB accesses -system.cpu1.numCycles 51860387727 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 428674248 # ITB inst accesses +system.cpu1.itb.hits 428597912 # DTB hits +system.cpu1.itb.misses 76336 # DTB misses +system.cpu1.itb.accesses 428674248 # DTB accesses +system.cpu1.numCycles 51781450270 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 434015512 # Number of instructions committed -system.cpu1.committedOps 509975199 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 468434913 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 458508 # Number of float alu accesses -system.cpu1.num_func_calls 25828963 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 66119194 # number of instructions that are conditional controls -system.cpu1.num_int_insts 468434913 # number of integer instructions -system.cpu1.num_fp_insts 458508 # number of float instructions -system.cpu1.num_int_register_reads 681011171 # number of times the integer registers were read -system.cpu1.num_int_register_writes 371474138 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 735722 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 396908 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 113358693 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113081851 # number of times the CC registers were written -system.cpu1.num_mem_refs 155802990 # number of memory refs -system.cpu1.num_load_insts 81728236 # Number of load instructions -system.cpu1.num_store_insts 74074754 # Number of store instructions -system.cpu1.num_idle_cycles 50263670387.895683 # Number of idle cycles -system.cpu1.num_busy_cycles 1596717339.104316 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030789 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969211 # Percentage of idle cycles -system.cpu1.Branches 96920557 # Number of branches fetched -system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 353254188 69.23% 69.23% # Class of executed instruction -system.cpu1.op_class::IntMult 1106936 0.22% 69.45% # Class of executed instruction -system.cpu1.op_class::IntDiv 48650 0.01% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 58473 0.01% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::MemRead 81728236 16.02% 85.48% # Class of executed instruction -system.cpu1.op_class::MemWrite 74074754 14.52% 100.00% # Class of executed instruction +system.cpu1.committedInsts 428322492 # Number of instructions committed +system.cpu1.committedOps 503238558 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 462373470 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 457847 # Number of float alu accesses +system.cpu1.num_func_calls 25589000 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 65138542 # number of instructions that are conditional controls +system.cpu1.num_int_insts 462373470 # number of integer instructions +system.cpu1.num_fp_insts 457847 # number of float instructions +system.cpu1.num_int_register_reads 672243876 # number of times the integer registers were read +system.cpu1.num_int_register_writes 366665103 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 741025 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 381476 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 111687570 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 111401234 # number of times the CC registers were written +system.cpu1.num_mem_refs 153562143 # number of memory refs +system.cpu1.num_load_insts 80482788 # Number of load instructions +system.cpu1.num_store_insts 73079355 # Number of store instructions +system.cpu1.num_idle_cycles 50246687172.676186 # Number of idle cycles +system.cpu1.num_busy_cycles 1534763097.323812 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029639 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970361 # Percentage of idle cycles +system.cpu1.Branches 95580848 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 348749586 69.26% 69.26% # Class of executed instruction +system.cpu1.op_class::IntMult 1110324 0.22% 69.48% # Class of executed instruction +system.cpu1.op_class::IntDiv 49704 0.01% 69.49% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 2 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 8 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 12 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 56056 0.01% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::MemRead 80482788 15.98% 85.49% # Class of executed instruction +system.cpu1.op_class::MemWrite 73079355 14.51% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 510271279 # Class of executed instruction +system.cpu1.op_class::total 503527836 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.tags.replacements 115483 # number of replacements -system.iocache.tags.tagsinuse 10.461502 # Cycle average of tags in use +system.iobus.trans_dist::ReadReq 40424 # Transaction distribution +system.iobus.trans_dist::ReadResp 40424 # Transaction distribution +system.iobus.trans_dist::WriteReq 136733 # Transaction distribution +system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354314 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7493014 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 1042410724 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179081273 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115504 # number of replacements +system.iocache.tags.tagsinuse 10.454717 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115520 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13154061165000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.844281 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.617221 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.365268 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.288576 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653844 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13154373196000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.509635 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.945082 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219352 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434068 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653420 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039906 # Number of tag accesses -system.iocache.tags.data_accesses 1039906 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1040055 # Number of tag accesses +system.iocache.tags.data_accesses 1040055 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8858 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8895 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 5 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 5 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses -system.iocache.demand_misses::total 8877 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8858 # number of demand (read+write) misses +system.iocache.demand_misses::total 8898 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8837 # number of overall misses -system.iocache.overall_misses::total 8877 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1908690112 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1914175112 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8858 # number of overall misses +system.iocache.overall_misses::total 8898 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5479000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1913667012 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1919146012 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1908690112 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1914514112 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1908690112 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1914514112 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28832566439 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28832566439 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5818000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1913667012 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1919485012 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5818000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1913667012 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1919485012 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8858 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8895 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106669 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106669 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8858 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8898 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8858 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8898 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000047 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000047 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 215988.470295 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 215706.007663 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 216038.271845 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 215755.594379 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 215988.470295 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 215671.297961 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 215988.470295 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 215671.297961 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 51929 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270312.068167 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270312.068167 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 145450 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 216038.271845 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 215720.949876 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 145450 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 216038.271845 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 215720.949876 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 223529 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27514 # 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average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 163978.851646 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 163661.722654 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 163978.851646 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 163661.722654 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218311.637338 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218311.637338 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 164028.167984 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 152.896952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 229.074218 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2954.015231 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9873.444708 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.350600 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 215.925176 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4167.527871 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9496.132455 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.581246 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002333 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003495 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.045075 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.150657 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002309 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003295 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.063591 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.144899 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996901 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 242 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 61762 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 421 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2430 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5430 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53446 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003693 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.942413 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 255508368 # Number of tag accesses +system.l2c.tags.data_accesses 255508368 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 218363 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 160178 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 6707988 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3047209 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 224681 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5166542500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1524532500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4850541252 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 724437500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5605162751 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 12704674003 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007612 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.009902 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.005370 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.039999 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.006689 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.009918 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005779 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.037944 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016054 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.403995 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.402045 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.403019 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.781743 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.784775 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.783242 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.202662 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.193086 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.197818 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007612 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.009902 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005370 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.078835 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.006689 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.009918 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005779 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.074958 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.032192 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007612 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.009902 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005370 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.078835 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.006689 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.009918 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005779 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.074958 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.032192 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65767.611940 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 68221.285893 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61631.926724 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63439.189981 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65790.647720 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67211.419753 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61674.155916 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63571.088259 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63148.059349 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 21627.881226 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 21595.975088 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21611.964709 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.950776 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.980922 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.470317 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 60000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61112.461453 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61172.908878 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61142.307951 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65767.611940 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 68221.285893 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61631.926724 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62011.141139 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65790.647720 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67211.419753 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61674.155916 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62097.232927 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62053.720068 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65767.611940 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 68221.285893 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61631.926724 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62011.141139 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65790.647720 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67211.419753 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61674.155916 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62097.232927 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62053.720068 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 417721 # Transaction distribution +system.membus.trans_dist::ReadResp 417721 # Transaction distribution +system.membus.trans_dist::WriteReq 33871 # Transaction distribution +system.membus.trans_dist::WriteResp 33871 # Transaction distribution +system.membus.trans_dist::Writeback 1069486 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 600721 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 600721 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34423 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 34424 # Transaction distribution +system.membus.trans_dist::ReadExReq 397977 # Transaction distribution +system.membus.trans_dist::ReadExResp 397977 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3570318 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3700502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334782 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 334782 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4035284 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 140106848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 140277172 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14030080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14030080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 154307252 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3630 # Total snoops (count) +system.membus.snoop_fanout::samples 2443419 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 2443419 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2443419 # Request fanout histogram +system.membus.reqLayer0.occupancy 107392500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5575997 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 16318205493 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 7697194309 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186789727 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 18 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 21137473 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 21129474 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33871 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33871 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7479557 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1332565 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1225901 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 43231 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43232 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2014651 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2014651 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 27041508 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27036574 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 774452 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1144323 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 55996857 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 862740756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1097639072 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2601008 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3569856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 1966550692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 492520 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 31930568 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003619 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.060051 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 31815006 99.64% 99.64% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115562 0.36% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 31930568 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 50801737999 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 4033500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 60715950506 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 38798201181 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 449711000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 698488000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |