diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/fs/10.linux-boot/ref/arm | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
8 files changed, 10148 insertions, 10052 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index d5447172f..4b75ac871 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,143 +1,143 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.146775 # Number of seconds simulated -sim_ticks 1146774863500 # Number of ticks simulated -final_tick 1146774863500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.145505 # Number of seconds simulated +sim_ticks 1145504982000 # Number of ticks simulated +final_tick 1145504982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52366 # Simulator instruction rate (inst/s) -host_op_rate 67406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 970268509 # Simulator tick rate (ticks/s) -host_mem_usage 448492 # Number of bytes of host memory used -host_seconds 1181.92 # Real time elapsed on the host -sim_insts 61892059 # Number of instructions simulated -sim_ops 79667620 # Number of ops (including micro ops) simulated +host_inst_rate 75061 # Simulator instruction rate (inst/s) +host_op_rate 90396 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1390275818 # Simulator tick rate (ticks/s) +host_mem_usage 476724 # Number of bytes of host memory used +host_seconds 823.94 # Real time elapsed on the host +sim_insts 61845931 # Number of instructions simulated +sim_ops 74481224 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7022076 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7004988 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3606712 # Number of bytes read from this memory -system.physmem.bytes_read::total 60963700 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 763904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 275840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1039744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4294592 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 3603320 # Number of bytes read from this memory +system.physmem.bytes_read::total 60941044 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 751104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 270784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1021888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4281152 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7321936 # Number of bytes written to this memory +system.physmem.bytes_written::total 7308496 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 40 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 109794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 109512 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56383 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6457684 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 67103 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56320 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457305 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66893 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823939 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43889738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 2232 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823729 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43938393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 335 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 6123326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 3145092 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53161001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 666132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 240535 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 906668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3744930 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 14824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 2625052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6384807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3744930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43889738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 6115196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 3145617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53200156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 655697 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 236388 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 892085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3737349 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 14841 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 2627962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6380152 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3737349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43938393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 335 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 6138150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 5770144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59545808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6457684 # Number of read requests accepted -system.physmem.writeReqs 823939 # Number of write requests accepted -system.physmem.readBursts 6457684 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823939 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 413268352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7334336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 60963700 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7321936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 366 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709320 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12375 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 403317 # Per bank write bursts -system.physmem.perBankRdBursts::1 403674 # Per bank write bursts -system.physmem.perBankRdBursts::2 403089 # Per bank write bursts -system.physmem.perBankRdBursts::3 403454 # Per bank write bursts -system.physmem.perBankRdBursts::4 406236 # Per bank write bursts -system.physmem.perBankRdBursts::5 403730 # Per bank write bursts -system.physmem.perBankRdBursts::6 403529 # Per bank write bursts -system.physmem.perBankRdBursts::7 403381 # Per bank write bursts -system.physmem.perBankRdBursts::8 403672 # Per bank write bursts -system.physmem.perBankRdBursts::9 404158 # Per bank write bursts -system.physmem.perBankRdBursts::10 403104 # Per bank write bursts -system.physmem.perBankRdBursts::11 402562 # Per bank write bursts -system.physmem.perBankRdBursts::12 403651 # Per bank write bursts -system.physmem.perBankRdBursts::13 403575 # Per bank write bursts -system.physmem.perBankRdBursts::14 403252 # Per bank write bursts -system.physmem.perBankRdBursts::15 402934 # Per bank write bursts -system.physmem.perBankWrBursts::0 7008 # Per bank write bursts -system.physmem.perBankWrBursts::1 7418 # Per bank write bursts -system.physmem.perBankWrBursts::2 6865 # Per bank write bursts -system.physmem.perBankWrBursts::3 7084 # Per bank write bursts -system.physmem.perBankWrBursts::4 7615 # Per bank write bursts -system.physmem.perBankWrBursts::5 7300 # Per bank write bursts -system.physmem.perBankWrBursts::6 7325 # Per bank write bursts -system.physmem.perBankWrBursts::7 7167 # Per bank write bursts -system.physmem.perBankWrBursts::8 7323 # Per bank write bursts -system.physmem.perBankWrBursts::9 7753 # Per bank write bursts -system.physmem.perBankWrBursts::10 6901 # Per bank write bursts -system.physmem.perBankWrBursts::11 6492 # Per bank write bursts -system.physmem.perBankWrBursts::12 7387 # Per bank write bursts -system.physmem.perBankWrBursts::13 7157 # Per bank write bursts -system.physmem.perBankWrBursts::14 7029 # Per bank write bursts -system.physmem.perBankWrBursts::15 6775 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 6130037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 5773579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59580308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6457305 # Number of read requests accepted +system.physmem.writeReqs 823729 # Number of write requests accepted +system.physmem.readBursts 6457305 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 823729 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 413239936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 27584 # Total number of bytes read from write queue +system.physmem.bytesWritten 7320448 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 60941044 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7308496 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 431 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709326 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12284 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 403300 # Per bank write bursts +system.physmem.perBankRdBursts::1 403658 # Per bank write bursts +system.physmem.perBankRdBursts::2 403038 # Per bank write bursts +system.physmem.perBankRdBursts::3 403410 # Per bank write bursts +system.physmem.perBankRdBursts::4 406147 # Per bank write bursts +system.physmem.perBankRdBursts::5 403703 # Per bank write bursts +system.physmem.perBankRdBursts::6 403511 # Per bank write bursts +system.physmem.perBankRdBursts::7 403334 # Per bank write bursts +system.physmem.perBankRdBursts::8 403656 # Per bank write bursts +system.physmem.perBankRdBursts::9 404136 # Per bank write bursts +system.physmem.perBankRdBursts::10 403079 # Per bank write bursts +system.physmem.perBankRdBursts::11 402530 # Per bank write bursts +system.physmem.perBankRdBursts::12 403635 # Per bank write bursts +system.physmem.perBankRdBursts::13 403544 # Per bank write bursts +system.physmem.perBankRdBursts::14 403293 # Per bank write bursts +system.physmem.perBankRdBursts::15 402900 # Per bank write bursts +system.physmem.perBankWrBursts::0 6991 # Per bank write bursts +system.physmem.perBankWrBursts::1 7395 # Per bank write bursts +system.physmem.perBankWrBursts::2 6850 # Per bank write bursts +system.physmem.perBankWrBursts::3 7056 # Per bank write bursts +system.physmem.perBankWrBursts::4 7584 # Per bank write bursts +system.physmem.perBankWrBursts::5 7290 # Per bank write bursts +system.physmem.perBankWrBursts::6 7311 # Per bank write bursts +system.physmem.perBankWrBursts::7 7141 # Per bank write bursts +system.physmem.perBankWrBursts::8 7309 # Per bank write bursts +system.physmem.perBankWrBursts::9 7743 # Per bank write bursts +system.physmem.perBankWrBursts::10 6877 # Per bank write bursts +system.physmem.perBankWrBursts::11 6465 # Per bank write bursts +system.physmem.perBankWrBursts::12 7382 # Per bank write bursts +system.physmem.perBankWrBursts::13 7153 # Per bank write bursts +system.physmem.perBankWrBursts::14 7067 # Per bank write bursts +system.physmem.perBankWrBursts::15 6768 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1146771945000 # Total gap between requests +system.physmem.totGap 1145502120500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 109 # Read request sizes (log2) -system.physmem.readPktSize::3 6291456 # Read request sizes (log2) +system.physmem.readPktSize::2 59 # Read request sizes (log2) +system.physmem.readPktSize::3 6291481 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166119 # Read request sizes (log2) +system.physmem.readPktSize::6 165765 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 67103 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 558746 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 398674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 399850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 441647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 404684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 430598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1121698 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1089151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1417401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 50859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 37752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 7903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 180 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66893 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 558286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 398741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 399967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 444496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 405001 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 431562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1118263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1083915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1408608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 55788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 45494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 41962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 40334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 7851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 218 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -168,25 +168,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -217,66 +217,66 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 461513 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 911.356100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 779.117173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 292.189115 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24977 5.41% 5.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21582 4.68% 10.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5972 1.29% 11.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2646 0.57% 11.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2555 0.55% 12.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1574 0.34% 12.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4102 0.89% 13.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 979 0.21% 13.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 397126 86.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 461513 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6665 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 968.839160 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 26148.924018 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6658 99.89% 99.89% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 460787 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 912.700193 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 781.910252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 290.668132 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24338 5.28% 5.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21658 4.70% 9.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5935 1.29% 11.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2553 0.55% 11.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2424 0.53% 12.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1615 0.35% 12.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4021 0.87% 13.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 977 0.21% 13.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 397266 86.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 460787 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6652 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 970.665664 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 26177.869763 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6645 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6665 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6665 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.194149 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.165520 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.984786 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2686 40.30% 40.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 20 0.30% 40.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3941 59.13% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 15 0.23% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6665 # Writes before turning the bus around for reads -system.physmem.totQLat 165007028750 # Total ticks spent queuing -system.physmem.totMemAccLat 286081741250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 32286590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25553.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6652 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6652 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.195129 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.166489 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.984981 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2678 40.26% 40.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 22 0.33% 40.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3930 59.08% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 20 0.30% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6652 # Writes before turning the bus around for reads +system.physmem.totQLat 165525335000 # Total ticks spent queuing +system.physmem.totMemAccLat 286591722500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 32284370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25635.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44303.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.16 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44385.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 360.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.39 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.20 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 6.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.87 # Data bus utilization in percentage system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 4.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.54 # Average write queue length when enqueuing -system.physmem.readRowHits 6015984 # Number of row buffer hits during reads -system.physmem.writeRowHits 94420 # Number of row buffer hits during writes +system.physmem.avgRdQLen 3.81 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing +system.physmem.readRowHits 6016106 # Number of row buffer hits during reads +system.physmem.writeRowHits 94363 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.38 # Row buffer hit rate for writes -system.physmem.avgGap 157488.51 # Average gap between requests -system.physmem.pageHitRate 92.98 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 908124290750 # Time in different power states -system.physmem.memoryStateTime::REF 38293320000 # Time in different power states +system.physmem.writeRowHitRate 82.48 # Row buffer hit rate for writes +system.physmem.avgGap 157326.85 # Average gap between requests +system.physmem.pageHitRate 92.99 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 907058635500 # Time in different power states +system.physmem.memoryStateTime::REF 38250680000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 200357121750 # Time in different power states +system.physmem.memoryStateTime::ACT 200188472000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory @@ -289,266 +289,266 @@ system.realview.nvmem.num_reads::cpu1.inst 7 # system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 223 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 391 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 614 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 615 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 223 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 391 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 614 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 615 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 223 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 391 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 614 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 61651742 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7506663 # Transaction distribution -system.membus.trans_dist::ReadResp 7506663 # Transaction distribution -system.membus.trans_dist::WriteReq 767825 # Transaction distribution -system.membus.trans_dist::WriteResp 767825 # Transaction distribution -system.membus.trans_dist::Writeback 67103 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33483 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17276 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12375 # Transaction distribution -system.membus.trans_dist::ReadExReq 137796 # Transaction distribution -system.membus.trans_dist::ReadExResp 137454 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382664 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bw_total::total 615 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 61688542 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7506218 # Transaction distribution +system.membus.trans_dist::ReadResp 7506218 # Transaction distribution +system.membus.trans_dist::WriteReq 767823 # Transaction distribution +system.membus.trans_dist::WriteResp 767823 # Transaction distribution +system.membus.trans_dist::Writeback 66893 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33061 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17229 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12284 # Transaction distribution +system.membus.trans_dist::ReadExReq 137868 # Transaction distribution +system.membus.trans_dist::ReadExResp 137512 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382652 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11272 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 874 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976707 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4371551 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975193 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4370017 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12582912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12582912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16954463 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16952929 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389988 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22544 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1748 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17953988 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20369020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17917892 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20332884 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 50331648 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 50331648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 70700668 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 70700668 # Total data (bytes) +system.membus.tot_pkt_size::total 70664532 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 70664532 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1725618000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1775897999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.reqLayer1.occupancy 16500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 10203000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 10198500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 700000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8808401000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8866177500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4909176600 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4931588899 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 15579623500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 15569082998 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 73595 # number of replacements -system.l2c.tags.tagsinuse 53913.869309 # Cycle average of tags in use -system.l2c.tags.total_refs 2430089 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 138750 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.514155 # Average number of references to valid blocks. +system.l2c.tags.replacements 73238 # number of replacements +system.l2c.tags.tagsinuse 53823.910561 # Cycle average of tags in use +system.l2c.tags.total_refs 2398257 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 138408 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.327445 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38825.506974 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 30.840279 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001297 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8944.299229 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.867460 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6105.354070 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.592430 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000471 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 38958.946929 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.880846 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8788.881914 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.740937 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6066.458640 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.594466 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.136479 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000120 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.093160 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.822660 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65141 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.134108 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000118 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.092567 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.821288 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2303 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8599 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54129 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.993973 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 23296068 # Number of tag accesses -system.l2c.tags.data_accesses 23296068 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 29004 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6772 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 959141 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 26476 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5085 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 968677 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1995155 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 576981 # number of Writeback hits -system.l2c.Writeback_hits::total 576981 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 913 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 959 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1872 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 209 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 100 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 309 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 58748 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 50778 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109526 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 29004 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6772 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 1017889 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 26476 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5085 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 1019455 # number of demand (read+write) hits -system.l2c.demand_hits::total 2104681 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 29004 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6772 # number of overall hits -system.l2c.overall_hits::cpu0.inst 1017889 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 26476 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5085 # number of overall hits -system.l2c.overall_hits::cpu1.inst 1019455 # number of overall hits -system.l2c.overall_hits::total 2104681 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 40 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8664 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53947 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 23040420 # Number of tag accesses +system.l2c.tags.data_accesses 23040420 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 22272 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6564 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 949144 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 22723 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5189 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 959680 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1965572 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 575172 # number of Writeback hits +system.l2c.Writeback_hits::total 575172 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 954 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 1026 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1980 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 203 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 94 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 297 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 58656 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 50708 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109364 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22272 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6564 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 1007800 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 22723 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5189 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 1010388 # number of demand (read+write) hits +system.l2c.demand_hits::total 2074936 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22272 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6564 # number of overall hits +system.l2c.overall_hits::cpu0.inst 1007800 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 22723 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5189 # number of overall hits +system.l2c.overall_hits::cpu1.inst 1010388 # number of overall hits +system.l2c.overall_hits::total 2074936 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 6 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 16374 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 16107 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9914 # number of ReadReq misses -system.l2c.ReadReq_misses::total 26339 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 4863 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 4102 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8965 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 683 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 310 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 993 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 92483 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 47388 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139871 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 40 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.inst 9802 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25926 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 4879 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 4062 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8941 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 695 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 300 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 995 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 92450 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 47410 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139860 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 108857 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 108557 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 57302 # number of demand (read+write) misses -system.l2c.demand_misses::total 166210 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 40 # number of overall misses +system.l2c.demand_misses::cpu1.inst 57212 # number of demand (read+write) misses +system.l2c.demand_misses::total 165786 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 108857 # number of overall misses +system.l2c.overall_misses::cpu0.inst 108557 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses -system.l2c.overall_misses::cpu1.inst 57302 # number of overall misses -system.l2c.overall_misses::total 166210 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 3039250 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.inst 57212 # number of overall misses +system.l2c.overall_misses::total 165786 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 592000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1157856000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 661250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 747415749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1909121749 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 8211643 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 13589417 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21801060 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 673971 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 2091409 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2765380 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 6321431326 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 3362017496 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9683448822 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 3039250 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1134045250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 716250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 732959500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1868462500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.inst 8149146 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.inst 13619415 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 21768561 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 695470 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 2181906 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2877376 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.inst 6400503611 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.inst 3385304039 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9785807650 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 592000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 7479287326 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 661250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4109433245 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11592570571 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 3039250 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 7534548861 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 716250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4118263539 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11654270150 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 592000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 7479287326 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 661250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4109433245 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11592570571 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 29044 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6774 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 975515 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 26485 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5085 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 978591 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2021494 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 576981 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 576981 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 5776 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 5061 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10837 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 892 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 410 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1302 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 151231 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 98166 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249397 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 29044 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6774 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 1126746 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 26485 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5085 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 1076757 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2270891 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 29044 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6774 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 1126746 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 26485 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5085 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 1076757 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2270891 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001377 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000295 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016785 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000340 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010131 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.013029 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.841932 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.810512 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.827258 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.765695 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.756098 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.762673 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.611535 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.482733 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.560837 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001377 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000295 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.096612 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000340 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.053217 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.073192 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001377 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000295 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.096612 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000340 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.053217 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.073192 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75981.250000 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 7534548861 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 716250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4118263539 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11654270150 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 22278 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6566 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 965251 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 22732 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5189 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 969482 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1991498 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 575172 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 575172 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.inst 5833 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.inst 5088 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10921 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.inst 898 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.inst 394 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1292 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.inst 151106 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.inst 98118 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249224 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 22278 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6566 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 1116357 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 22732 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5189 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 1067600 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2240722 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 22278 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6566 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 1116357 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 22732 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5189 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 1067600 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2240722 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000305 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016687 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010111 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.836448 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.798349 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.818698 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.773942 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.761421 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.770124 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.inst 0.611822 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.inst 0.483194 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.561182 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000305 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.097242 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.053589 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.073988 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000305 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.097242 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.053589 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.073988 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70713.081715 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 73472.222222 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75389.928283 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 72482.696723 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1688.596134 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 3312.875914 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2431.796988 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 986.780381 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 6746.480645 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2784.874119 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 68352.360174 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 70946.600321 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69231.283268 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75981.250000 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70406.981437 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74776.525199 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 72069.061946 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1670.249231 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 3352.884047 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2434.689744 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 1000.676259 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 7273.020000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2891.835176 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 69232.056366 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 71404.852120 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 69968.594666 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 68707.454054 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 73472.222222 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 71715.354525 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 69746.528915 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75981.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 69406.384305 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 71982.513092 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 70297.070621 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 68707.454054 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 73472.222222 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 71715.354525 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 69746.528915 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 69406.384305 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 71982.513092 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 70297.070621 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -557,134 +557,134 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 67103 # number of writebacks -system.l2c.writebacks::total 67103 # number of writebacks +system.l2c.writebacks::writebacks 66893 # number of writebacks +system.l2c.writebacks::total 66893 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 49 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 19 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 22 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 49 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 19 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 22 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 49 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 19 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 68 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 40 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::cpu1.inst 22 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 16325 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 16058 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 9895 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 26271 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 4863 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 4102 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8965 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 683 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 310 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 993 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 92483 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 47388 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139871 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 40 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 9780 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25855 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.inst 4879 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.inst 4062 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8941 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 695 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 300 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 995 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.inst 92450 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.inst 47410 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139860 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 108808 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 108508 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 57283 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 166142 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 40 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 57190 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165715 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 108808 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 108508 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 57283 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 166142 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2549250 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.inst 57190 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165715 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 518500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 950227250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 549750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 622555749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1576006999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 48716838 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 41086590 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 89803428 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6847181 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 3100809 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 9947990 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5160123162 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 2766953994 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7927077156 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2549250 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 929504000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 609332000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1540083250 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 48881350 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 40684546 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 89565896 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6993689 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 3002299 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 9995988 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5227989883 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 2775821957 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8003811840 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 518500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 6110350412 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 549750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3389509743 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9503084155 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2549250 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 6157493883 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 603750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3385153957 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9543895090 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 518500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 6110350412 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 549750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3389509743 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9503084155 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156402291235 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10978060744 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167380351979 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1364398990 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15414990793 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16779389783 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157766690225 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 26393051537 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184159741762 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001377 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000295 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016735 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000340 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010111 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.012996 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.841932 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.810512 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.827258 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.765695 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.756098 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.762673 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.611535 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.482733 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.560837 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001377 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000295 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.096568 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000340 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053200 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.073162 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001377 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000295 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.096568 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000340 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053200 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.073162 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 6157493883 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 603750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3385153957 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9543895090 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156449024487 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10979297747 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167428322234 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1364347483 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15414886347 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16779233830 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157813371970 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 26394184094 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184207556064 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016636 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010088 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.012983 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.836448 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.798349 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.818698 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.773942 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.761421 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770124 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.611822 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.483194 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.561182 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.073956 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.073956 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58206.875957 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62916.194947 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59990.369571 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10017.856878 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10016.233545 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.114110 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10025.155198 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10002.609677 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10018.116818 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 55795.369549 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58389.338947 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56674.200914 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57884.169884 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62303.885481 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59566.167086 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10018.723099 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10015.890202 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.436081 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10062.861871 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10007.663333 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10046.219095 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 56549.376777 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58549.292491 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57227.311883 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56157.179729 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59171.302882 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57198.566016 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56157.179729 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59171.302882 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57198.566016 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -701,62 +701,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 164548117 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 3298522 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3298521 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767825 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767825 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576981 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 32938 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17585 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 50523 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260723 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260723 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1574360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3288712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16464 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 66826 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1600801 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2571055 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13478 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 62668 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9194364 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 50355392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43867388 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 116176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 51198592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38125568 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20340 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 105940 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 183816492 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 183816492 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4883152 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5169541990 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3546630183 # Layer occupancy (ticks) +system.toL2Bus.throughput 163445997 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 3265310 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3265309 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767823 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767823 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 575172 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 32693 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17526 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 50219 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260531 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260531 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1555911 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3285118 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16087 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52607 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1583939 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2567940 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13476 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 53641 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9128719 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49766528 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43750900 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 89112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 50661248 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38001760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 90928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 182407496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 182407496 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4820708 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5144551012 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3505001405 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2800512724 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2792622052 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9693493 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9525491 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 37783748 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30330496 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 3604679924 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 3566573438 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1938501968 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 1934335367 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 8396493 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.occupancy 8290992 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 36187242 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 30912744 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45973854 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7474822 # Transaction distribution -system.iobus.trans_dist::ReadResp 7474822 # Transaction distribution +system.iobus.throughput 46024799 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7474816 # Transaction distribution +system.iobus.trans_dist::ReadResp 7474816 # Transaction distribution system.iobus.trans_dist::WriteReq 7966 # Transaction distribution system.iobus.trans_dist::WriteResp 7966 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 732 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -778,12 +778,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382664 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382652 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12582912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12582912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14965576 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 14965564 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16100 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16076 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1464 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -805,14 +805,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390012 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389988 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 50331648 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 50331648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 52721660 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 52721660 # Total data (bytes) +system.iobus.tot_pkt_size::total 52721636 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 52721636 # Total data (bytes) system.iobus.reqLayer0.occupancy 21429000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4031000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4025000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -858,19 +858,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6291456000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374698000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374686000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 15850285500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 15862213002 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu0.branchPred.lookups 6861856 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5181081 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 652173 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4714052 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3350352 # Number of BTB hits +system.cpu0.branchPred.lookups 6670288 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4756995 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 639495 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4605007 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3289427 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.071596 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 844036 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 70439 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.431531 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 870926 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 69312 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -894,25 +894,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8249046 # DTB read hits -system.cpu0.dtb.read_misses 22426 # DTB read misses -system.cpu0.dtb.write_hits 6048331 # DTB write hits -system.cpu0.dtb.write_misses 1452 # DTB write misses +system.cpu0.dtb.read_hits 7193152 # DTB read hits +system.cpu0.dtb.read_misses 17493 # DTB read misses +system.cpu0.dtb.write_hits 6058571 # DTB write hits +system.cpu0.dtb.write_misses 1416 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1952 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1134 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 199 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1942 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1486 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 207 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 288 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8271472 # DTB read accesses -system.cpu0.dtb.write_accesses 6049783 # DTB write accesses +system.cpu0.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7210645 # DTB read accesses +system.cpu0.dtb.write_accesses 6059987 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14297377 # DTB hits -system.cpu0.dtb.misses 23878 # DTB misses -system.cpu0.dtb.accesses 14321255 # DTB accesses +system.cpu0.dtb.hits 13251723 # DTB hits +system.cpu0.dtb.misses 18909 # DTB misses +system.cpu0.dtb.accesses 13270632 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -934,8 +934,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 12515958 # ITB inst hits -system.cpu0.itb.inst_misses 4886 # ITB inst misses +system.cpu0.itb.inst_hits 12268451 # ITB inst hits +system.cpu0.itb.inst_misses 4809 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -944,82 +944,82 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1295 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1294 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2118 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2809 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 12520844 # ITB inst accesses -system.cpu0.itb.hits 12515958 # DTB hits -system.cpu0.itb.misses 4886 # DTB misses -system.cpu0.itb.accesses 12520844 # DTB accesses -system.cpu0.numCycles 433909161 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 12273260 # ITB inst accesses +system.cpu0.itb.hits 12268451 # DTB hits +system.cpu0.itb.misses 4809 # DTB misses +system.cpu0.itb.accesses 12273260 # DTB accesses +system.cpu0.numCycles 431172708 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29915294 # Number of instructions committed -system.cpu0.committedOps 39343022 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 1900672 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 39481 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 1859706962 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 14.504593 # CPI: cycles per instruction -system.cpu0.ipc 0.068944 # IPC: instructions per cycle +system.cpu0.committedInsts 29878954 # Number of instructions committed +system.cpu0.committedOps 36403873 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 1704985 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 39450 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 1859905219 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 14.430649 # CPI: cycles per instruction +system.cpu0.ipc 0.069297 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 50347 # number of quiesce instructions executed -system.cpu0.tickCycles 353761855 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 80147306 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 784713 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.784867 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 11728456 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 785225 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 14.936427 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10280766000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.784867 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997627 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997627 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 50317 # number of quiesce instructions executed +system.cpu0.tickCycles 351703832 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 79468876 # Total number of cycles that the object has spent stopped +system.cpu0.icache.tags.replacements 775463 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.771777 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 11489502 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 775975 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 14.806536 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10202297000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.771777 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997601 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997601 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 506 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 13298912 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 13298912 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 11728456 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11728456 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 11728456 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11728456 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 11728456 # number of overall hits -system.cpu0.icache.overall_hits::total 11728456 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 785228 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 785228 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 785228 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 785228 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 785228 # number of overall misses -system.cpu0.icache.overall_misses::total 785228 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10819127683 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10819127683 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10819127683 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10819127683 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10819127683 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10819127683 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 12513684 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12513684 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 12513684 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12513684 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 12513684 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12513684 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.062750 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.062750 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.062750 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.062750 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.062750 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.062750 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13778.326401 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13778.326401 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13778.326401 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13778.326401 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13778.326401 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13778.326401 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 13041458 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 13041458 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 11489502 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11489502 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 11489502 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11489502 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 11489502 # number of overall hits +system.cpu0.icache.overall_hits::total 11489502 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 775978 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 775978 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 775978 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 775978 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 775978 # number of overall misses +system.cpu0.icache.overall_misses::total 775978 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10689826155 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10689826155 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10689826155 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10689826155 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10689826155 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10689826155 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 12265480 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12265480 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 12265480 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12265480 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 12265480 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12265480 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.063265 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.063265 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.063265 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.063265 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.063265 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.063265 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13775.939724 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13775.939724 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13775.939724 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13775.939724 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1028,125 +1028,125 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 785228 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 785228 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 785228 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 785228 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 785228 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 785228 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9244507317 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9244507317 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9244507317 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9244507317 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9244507317 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9244507317 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 171313500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 171313500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 171313500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 171313500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.062750 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.062750 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.062750 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.062750 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.062750 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.062750 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11773.023016 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11773.023016 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11773.023016 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11773.023016 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11773.023016 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11773.023016 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 775978 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 775978 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 775978 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 775978 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 775978 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 775978 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9133730845 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9133730845 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9133730845 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9133730845 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9133730845 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9133730845 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 171406750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 171406750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 171406750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 171406750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.063265 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.063265 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.063265 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11770.605410 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 332522 # number of replacements -system.cpu0.dcache.tags.tagsinuse 495.116335 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12493941 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 332889 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.531853 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 236260250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 495.116335 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.967024 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.967024 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 52581205 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 52581205 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 6652234 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6652234 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 5513247 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5513247 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 152467 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 152467 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 153686 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 153686 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 12165481 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12165481 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 12165481 # number of overall hits -system.cpu0.dcache.overall_hits::total 12165481 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 257861 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 257861 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 307489 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 307489 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 8753 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8753 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 7461 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7461 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 565350 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 565350 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 565350 # number of overall misses -system.cpu0.dcache.overall_misses::total 565350 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3878128215 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3878128215 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 15135680350 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 15135680350 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 89040000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 89040000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 47241681 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 47241681 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 19013808565 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 19013808565 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 19013808565 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 19013808565 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6910095 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6910095 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5820736 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5820736 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 161220 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 161220 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 161147 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 161147 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 12730831 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12730831 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 12730831 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12730831 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.037317 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037317 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.052826 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.052826 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.054292 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054292 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.046299 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046299 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.044408 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.044408 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.044408 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.044408 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15039.607444 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15039.607444 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49223.485556 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 49223.485556 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10172.512282 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10172.512282 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 6331.816244 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6331.816244 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33631.924587 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33631.924587 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33631.924587 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33631.924587 # average overall miss latency +system.cpu0.dcache.tags.replacements 331184 # number of replacements +system.cpu0.dcache.tags.tagsinuse 495.308279 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11419092 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 331547 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.441850 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 235572250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 495.308279 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.967399 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.967399 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 363 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 48281639 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 48281639 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 5587990 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5587990 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 5501455 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5501455 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 152609 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 152609 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 153662 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 153662 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 11089445 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11089445 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 11089445 # number of overall hits +system.cpu0.dcache.overall_hits::total 11089445 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 255115 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 255115 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 311930 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 311930 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 8548 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8548 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 7439 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7439 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 567045 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 567045 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 567045 # number of overall misses +system.cpu0.dcache.overall_misses::total 567045 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3832963977 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3832963977 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 15354005377 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 15354005377 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 89150250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 89150250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 47371188 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 47371188 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 19186969354 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 19186969354 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 19186969354 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 19186969354 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 5843105 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5843105 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5813385 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5813385 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 161157 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 161157 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 161101 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 161101 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 11656490 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11656490 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 11656490 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11656490 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.043661 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.043661 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.053657 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.053657 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.053041 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053041 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.046176 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046176 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.048646 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.048646 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.048646 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.048646 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15024.455547 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.455547 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49222.599227 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 49222.599227 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10429.369443 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10429.369443 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 6367.951069 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6367.951069 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33836.766666 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33836.766666 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1155,72 +1155,72 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 307804 # number of writebacks -system.cpu0.dcache.writebacks::total 307804 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 51446 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 51446 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 139700 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 139700 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 20 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 20 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 191146 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 191146 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 191146 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 191146 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 206415 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 206415 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 167789 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 167789 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8733 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8733 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 7461 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 374204 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 374204 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 374204 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 374204 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2545797312 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2545797312 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 7212492893 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7212492893 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71207000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71207000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 32318319 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32318319 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9758290205 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9758290205 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9758290205 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9758290205 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170750199252 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170750199252 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1513150500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1513150500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172263349752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172263349752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.029872 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029872 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.028826 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028826 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.054168 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.054168 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.046299 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.046299 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.029394 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029394 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.029394 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029394 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12333.392980 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12333.392980 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 42985.493048 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42985.493048 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8153.784496 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8153.784496 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4331.633695 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4331.633695 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26077.460970 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26077.460970 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26077.460970 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26077.460970 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 307170 # number of writebacks +system.cpu0.dcache.writebacks::total 307170 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 50178 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 50178 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 144238 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 144238 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 22 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 194416 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 194416 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 194416 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 194416 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 204937 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 204937 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 167692 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 167692 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8526 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 7439 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7439 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 372629 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 372629 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 372629 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 372629 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2523643558 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2523643558 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 7293302576 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7293302576 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71695750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71695750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 32490812 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32490812 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9816946134 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9816946134 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9816946134 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9816946134 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170796520252 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170796520252 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1513122000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1513122000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172309642252 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172309642252 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.035073 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035073 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.028846 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028846 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.052905 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.052905 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.046176 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.046176 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.031968 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031968 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12314.240757 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12314.240757 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 43492.251127 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43492.251127 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8409.072250 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8409.072250 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4367.631671 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4367.631671 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1228,15 +1228,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 6346953 # Number of BP lookups -system.cpu1.branchPred.condPredicted 4931527 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 433505 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4095605 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3083437 # Number of BTB hits +system.cpu1.branchPred.lookups 6159330 # Number of BP lookups +system.cpu1.branchPred.condPredicted 4534606 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 426160 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3924244 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3043762 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 75.286484 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 663921 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 63861 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 77.563016 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 713205 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 64399 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1260,25 +1260,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7581512 # DTB read hits -system.cpu1.dtb.read_misses 20239 # DTB read misses -system.cpu1.dtb.write_hits 5551171 # DTB write hits -system.cpu1.dtb.write_misses 2521 # DTB write misses +system.cpu1.dtb.read_hits 6763605 # DTB read hits +system.cpu1.dtb.read_misses 17087 # DTB read misses +system.cpu1.dtb.write_hits 5563764 # DTB write hits +system.cpu1.dtb.write_misses 2456 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1717 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2404 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 233 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1713 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1918 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 237 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7601751 # DTB read accesses -system.cpu1.dtb.write_accesses 5553692 # DTB write accesses +system.cpu1.dtb.perms_faults 260 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6780692 # DTB read accesses +system.cpu1.dtb.write_accesses 5566220 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13132683 # DTB hits -system.cpu1.dtb.misses 22760 # DTB misses -system.cpu1.dtb.accesses 13155443 # DTB accesses +system.cpu1.dtb.hits 12327369 # DTB hits +system.cpu1.dtb.misses 19543 # DTB misses +system.cpu1.dtb.accesses 12346912 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1300,8 +1300,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 11349850 # ITB inst hits -system.cpu1.itb.inst_misses 4207 # ITB inst misses +system.cpu1.itb.inst_hits 11206823 # ITB inst hits +system.cpu1.itb.inst_misses 4156 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1310,84 +1310,84 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1191 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1190 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2046 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2956 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 11354057 # ITB inst accesses -system.cpu1.itb.hits 11349850 # DTB hits -system.cpu1.itb.misses 4207 # DTB misses -system.cpu1.itb.accesses 11354057 # DTB accesses -system.cpu1.numCycles 149527233 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 11210979 # ITB inst accesses +system.cpu1.itb.hits 11206823 # DTB hits +system.cpu1.itb.misses 4156 # DTB misses +system.cpu1.itb.accesses 11210979 # DTB accesses +system.cpu1.numCycles 147611080 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31976765 # Number of instructions committed -system.cpu1.committedOps 40324598 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1783017 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 39969 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 2144960974 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 4.676121 # CPI: cycles per instruction -system.cpu1.ipc 0.213852 # IPC: instructions per cycle +system.cpu1.committedInsts 31966977 # Number of instructions committed +system.cpu1.committedOps 38077351 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1608279 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 39953 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 2144312243 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 4.617611 # CPI: cycles per instruction +system.cpu1.ipc 0.216562 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 40497 # number of quiesce instructions executed -system.cpu1.tickCycles 120083069 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 29444164 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 800234 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.617194 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 10546899 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 800746 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 13.171341 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 82063984250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.617194 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938705 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938705 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 40481 # number of quiesce instructions executed +system.cpu1.tickCycles 117794277 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 29816803 # Total number of cycles that the object has spent stopped +system.cpu1.icache.tags.replacements 791766 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.612166 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 10411414 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 792278 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 13.141112 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 82581306250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.612166 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938696 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938696 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 12148392 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 12148392 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 10546899 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 10546899 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 10546899 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 10546899 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 10546899 # number of overall hits -system.cpu1.icache.overall_hits::total 10546899 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 800747 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 800747 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 800747 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 800747 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 800747 # number of overall misses -system.cpu1.icache.overall_misses::total 800747 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10721128674 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10721128674 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10721128674 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10721128674 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10721128674 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10721128674 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 11347646 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 11347646 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 11347646 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 11347646 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 11347646 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 11347646 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.070565 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.070565 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.070565 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.070565 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.070565 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.070565 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13388.908949 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13388.908949 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13388.908949 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13388.908949 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13388.908949 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13388.908949 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 11995971 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 11995971 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 10411414 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 10411414 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 10411414 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 10411414 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 10411414 # number of overall hits +system.cpu1.icache.overall_hits::total 10411414 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 792279 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 792279 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 792279 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 792279 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 792279 # number of overall misses +system.cpu1.icache.overall_misses::total 792279 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10606605688 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10606605688 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10606605688 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10606605688 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10606605688 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10606605688 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 11203693 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 11203693 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 11203693 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 11203693 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 11203693 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 11203693 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.070716 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.070716 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.070716 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.070716 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.070716 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.070716 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.462861 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13387.462861 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13387.462861 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13387.462861 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1396,128 +1396,128 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 800747 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 800747 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 800747 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 800747 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 800747 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 800747 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9117705326 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 9117705326 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9117705326 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 9117705326 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9117705326 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 9117705326 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5654750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5654750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5654750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5654750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.070565 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.070565 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.070565 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.070565 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.070565 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.070565 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11386.499514 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11386.499514 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11386.499514 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11386.499514 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11386.499514 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11386.499514 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 792279 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 792279 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 792279 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 792279 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 792279 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 792279 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9020137312 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 9020137312 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9020137312 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 9020137312 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9020137312 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 9020137312 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5771250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5771250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5771250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5771250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.070716 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.070716 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.070716 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11385.051619 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 301108 # number of replacements -system.cpu1.dcache.tags.tagsinuse 446.775625 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11731236 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 301620 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 38.894092 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 76702840250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 446.775625 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.872609 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.872609 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 300206 # number of replacements +system.cpu1.dcache.tags.tagsinuse 447.094079 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 10899911 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 300718 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 36.246287 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 76416861250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 447.094079 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.873231 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.873231 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 350 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 49070289 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 49070289 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 7114972 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7114972 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 4425981 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4425981 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 78462 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78462 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 79072 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79072 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 11540953 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11540953 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 11540953 # number of overall hits -system.cpu1.dcache.overall_hits::total 11540953 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 243175 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 243175 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 224036 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 224036 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 10782 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10782 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 10124 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10124 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 467211 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 467211 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 467211 # number of overall misses -system.cpu1.dcache.overall_misses::total 467211 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3616409978 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3616409978 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 8727689439 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8727689439 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 90341500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 90341500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 50520310 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 50520310 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 12344099417 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12344099417 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 12344099417 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12344099417 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 7358147 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7358147 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 4650017 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4650017 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 89244 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 89244 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 89196 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 89196 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 12008164 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12008164 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 12008164 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12008164 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.033048 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.033048 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.048180 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.048180 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.120815 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120815 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.113503 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113503 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.038908 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038908 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.038908 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.038908 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.635563 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.635563 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 38956.638393 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 38956.638393 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 8378.918568 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8378.918568 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 4990.153102 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4990.153102 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26420.823604 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 26420.823604 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26420.823604 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 26420.823604 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 45736548 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 45736548 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.inst 6288103 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6288103 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.inst 4421998 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4421998 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 78443 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78443 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 79055 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79055 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.inst 10710101 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 10710101 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 10710101 # number of overall hits +system.cpu1.dcache.overall_hits::total 10710101 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 241320 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 241320 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 223635 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 223635 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 10750 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10750 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 10087 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10087 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.inst 464955 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 464955 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.inst 464955 # number of overall misses +system.cpu1.dcache.overall_misses::total 464955 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3586794993 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3586794993 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 8773828993 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8773828993 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 90116500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 90116500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 50277799 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 50277799 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 12360623986 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12360623986 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.inst 12360623986 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12360623986 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6529423 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6529423 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.inst 4645633 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4645633 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 89193 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 89193 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 89142 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 89142 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 11175056 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11175056 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 11175056 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11175056 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.036959 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036959 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.048139 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.048139 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.120525 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120525 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.113157 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113157 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.041607 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.041607 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.041607 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.041607 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14863.231365 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14863.231365 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 39232.807892 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39232.807892 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 8382.930233 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8382.930233 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 4984.415485 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4984.415485 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26584.559766 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26584.559766 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1526,72 +1526,72 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 269177 # number of writebacks -system.cpu1.dcache.writebacks::total 269177 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 37509 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 37509 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 98167 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 98167 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 30 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 30 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 135676 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 135676 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 135676 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 135676 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 205666 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 205666 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 125869 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 125869 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 10752 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10752 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 10124 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10124 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 331535 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 331535 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 331535 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 331535 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2422782037 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2422782037 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 4131508096 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4131508096 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 68345000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68345000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30271690 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30271690 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6554290133 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6554290133 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6554290133 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6554290133 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11992419500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11992419500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672512707 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672512707 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36664932207 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36664932207 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.027951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027069 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027069 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120479 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120479 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.113503 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113503 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.027609 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027609 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.027609 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027609 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11780.177749 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11780.177749 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 32823.873202 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32823.873202 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6356.491815 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6356.491815 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 2990.091861 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2990.091861 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19769.526997 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19769.526997 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19769.526997 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19769.526997 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 268002 # number of writebacks +system.cpu1.dcache.writebacks::total 268002 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36395 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 36395 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 98109 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 98109 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 34 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 134504 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 134504 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 134504 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 134504 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 204925 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 204925 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 125526 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 125526 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 10716 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10716 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 10087 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10087 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 330451 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 330451 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 330451 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 330451 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2412502275 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2412502275 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 4153602004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4153602004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 68123500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68123500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30103201 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30103201 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6566104279 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6566104279 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6566104279 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6566104279 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11993503500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11993503500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672579152 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672579152 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36666082652 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36666082652 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.031385 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.031385 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027020 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027020 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120144 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120144 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.113157 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113157 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029570 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029570 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.610833 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11772.610833 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 33089.575100 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33089.575100 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6357.176185 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6357.176185 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 2984.356201 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2984.356201 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1615,10 +1615,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 721880739500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 721880739500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 721880739500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 721880739500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722335941002 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 722335941002 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722335941002 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 722335941002 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 4491c3f13..4c74a9fb4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.567677 # Number of seconds simulated -sim_ticks 2567677478000 # Number of ticks simulated -final_tick 2567677478000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.566439 # Number of seconds simulated +sim_ticks 2566439177500 # Number of ticks simulated +final_tick 2566439177500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53140 # Simulator instruction rate (inst/s) -host_op_rate 68307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2251849348 # Simulator tick rate (ticks/s) -host_mem_usage 443244 # Number of bytes of host memory used -host_seconds 1140.25 # Real time elapsed on the host -sim_insts 60592948 # Number of instructions simulated -sim_ops 77887482 # Number of ops (including micro ops) simulated +host_inst_rate 73545 # Simulator instruction rate (inst/s) +host_op_rate 88536 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3115018228 # Simulator tick rate (ticks/s) +host_mem_usage 470576 # Number of bytes of host memory used +host_seconds 823.89 # Real time elapsed on the host +sim_insts 60593470 # Number of instructions simulated +sim_ops 72944147 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10106264 # Number of bytes read from this memory -system.physmem.bytes_read::total 131218072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1017856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1017856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3829760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 10079960 # Number of bytes read from this memory +system.physmem.bytes_read::total 131191960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1001344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1001344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3811328 # Number of bytes written to this memory system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6845832 # Number of bytes written to this memory +system.physmem.bytes_written::total 6827400 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 157946 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15296782 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59840 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 157525 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15296364 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59552 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813858 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47167344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 449 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813570 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47190103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 524 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3935955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51103798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 396411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 396411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1491527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 1174630 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2666157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1491527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47167344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3927605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51118281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 390169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 390169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1485065 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.inst 1175197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2660262 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1485065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47190103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5110586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53769956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15296782 # Number of read requests accepted -system.physmem.writeReqs 813858 # Number of write requests accepted -system.physmem.readBursts 15296782 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813858 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978883904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 110144 # Total number of bytes read from write queue -system.physmem.bytesWritten 6853696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131218072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6845832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1721 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706743 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4671 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955926 # Per bank write bursts -system.physmem.perBankRdBursts::1 955615 # Per bank write bursts -system.physmem.perBankRdBursts::2 955732 # Per bank write bursts -system.physmem.perBankRdBursts::3 955955 # Per bank write bursts -system.physmem.perBankRdBursts::4 957630 # Per bank write bursts -system.physmem.perBankRdBursts::5 955653 # Per bank write bursts -system.physmem.perBankRdBursts::6 955569 # Per bank write bursts -system.physmem.perBankRdBursts::7 955430 # Per bank write bursts -system.physmem.perBankRdBursts::8 956341 # Per bank write bursts -system.physmem.perBankRdBursts::9 955977 # Per bank write bursts -system.physmem.perBankRdBursts::10 955547 # Per bank write bursts -system.physmem.perBankRdBursts::11 955151 # Per bank write bursts -system.physmem.perBankRdBursts::12 956306 # Per bank write bursts -system.physmem.perBankRdBursts::13 956026 # Per bank write bursts -system.physmem.perBankRdBursts::14 956165 # Per bank write bursts -system.physmem.perBankRdBursts::15 956038 # Per bank write bursts -system.physmem.perBankWrBursts::0 6624 # Per bank write bursts -system.physmem.perBankWrBursts::1 6445 # Per bank write bursts -system.physmem.perBankWrBursts::2 6544 # Per bank write bursts -system.physmem.perBankWrBursts::3 6594 # Per bank write bursts -system.physmem.perBankWrBursts::4 6491 # Per bank write bursts -system.physmem.perBankWrBursts::5 6747 # Per bank write bursts -system.physmem.perBankWrBursts::6 6783 # Per bank write bursts -system.physmem.perBankWrBursts::7 6690 # Per bank write bursts -system.physmem.perBankWrBursts::8 7075 # Per bank write bursts -system.physmem.perBankWrBursts::9 6811 # Per bank write bursts -system.physmem.perBankWrBursts::10 6482 # Per bank write bursts -system.physmem.perBankWrBursts::11 6150 # Per bank write bursts -system.physmem.perBankWrBursts::12 7106 # Per bank write bursts -system.physmem.perBankWrBursts::13 6684 # Per bank write bursts -system.physmem.perBankWrBursts::14 7011 # Per bank write bursts -system.physmem.perBankWrBursts::15 6852 # Per bank write bursts +system.physmem.bw_total::cpu.inst 5102802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15296364 # Number of read requests accepted +system.physmem.writeReqs 813570 # Number of write requests accepted +system.physmem.readBursts 15296364 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813570 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978868736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 98560 # Total number of bytes read from write queue +system.physmem.bytesWritten 6836224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131191960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6827400 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1540 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706728 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4670 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955903 # Per bank write bursts +system.physmem.perBankRdBursts::1 955584 # Per bank write bursts +system.physmem.perBankRdBursts::2 955711 # Per bank write bursts +system.physmem.perBankRdBursts::3 955912 # Per bank write bursts +system.physmem.perBankRdBursts::4 957606 # Per bank write bursts +system.physmem.perBankRdBursts::5 955733 # Per bank write bursts +system.physmem.perBankRdBursts::6 955604 # Per bank write bursts +system.physmem.perBankRdBursts::7 955438 # Per bank write bursts +system.physmem.perBankRdBursts::8 956293 # Per bank write bursts +system.physmem.perBankRdBursts::9 955954 # Per bank write bursts +system.physmem.perBankRdBursts::10 955536 # Per bank write bursts +system.physmem.perBankRdBursts::11 955097 # Per bank write bursts +system.physmem.perBankRdBursts::12 956286 # Per bank write bursts +system.physmem.perBankRdBursts::13 955995 # Per bank write bursts +system.physmem.perBankRdBursts::14 956150 # Per bank write bursts +system.physmem.perBankRdBursts::15 956022 # Per bank write bursts +system.physmem.perBankWrBursts::0 6610 # Per bank write bursts +system.physmem.perBankWrBursts::1 6419 # Per bank write bursts +system.physmem.perBankWrBursts::2 6537 # Per bank write bursts +system.physmem.perBankWrBursts::3 6577 # Per bank write bursts +system.physmem.perBankWrBursts::4 6482 # Per bank write bursts +system.physmem.perBankWrBursts::5 6744 # Per bank write bursts +system.physmem.perBankWrBursts::6 6779 # Per bank write bursts +system.physmem.perBankWrBursts::7 6682 # Per bank write bursts +system.physmem.perBankWrBursts::8 7031 # Per bank write bursts +system.physmem.perBankWrBursts::9 6794 # Per bank write bursts +system.physmem.perBankWrBursts::10 6476 # Per bank write bursts +system.physmem.perBankWrBursts::11 6093 # Per bank write bursts +system.physmem.perBankWrBursts::12 7096 # Per bank write bursts +system.physmem.perBankWrBursts::13 6664 # Per bank write bursts +system.physmem.perBankWrBursts::14 6987 # Per bank write bursts +system.physmem.perBankWrBursts::15 6845 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2567675574500 # Total gap between requests +system.physmem.totGap 2566437420000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 38 # Read request sizes (log2) -system.physmem.readPktSize::3 15138816 # Read request sizes (log2) +system.physmem.readPktSize::2 18 # Read request sizes (log2) +system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157928 # Read request sizes (log2) +system.physmem.readPktSize::6 157520 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59840 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1112326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 958648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 963944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1085542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 974308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1043218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2679684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2578598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3358182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 142716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 121801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 111705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 108393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59552 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1111382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 958419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 963594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1074014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 973771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1037292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2691805 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2600171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3390697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 109522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 101552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -155,25 +155,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -204,63 +204,64 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1015088 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.085857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 904.509360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 205.145024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22501 2.22% 2.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22772 2.24% 4.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8563 0.84% 5.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2455 0.24% 5.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2778 0.27% 5.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1897 0.19% 6.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8457 0.83% 6.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 971 0.10% 6.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 944694 93.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1015088 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6216 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2460.593951 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115853.550339 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6211 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1014534 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.583959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.812030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 204.103928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21965 2.17% 2.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22634 2.23% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8771 0.86% 5.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2477 0.24% 5.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2600 0.26% 5.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1707 0.17% 5.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8766 0.86% 6.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1031 0.10% 6.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 944583 93.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1014534 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2467.302629 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 115861.516346 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6194 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6216 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.227960 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.199911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.974162 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2395 38.53% 38.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 16 0.26% 38.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3798 61.10% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 7 0.11% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6216 # Writes before turning the bus around for reads -system.physmem.totQLat 396370290250 # Total ticks spent queuing -system.physmem.totMemAccLat 683152684000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76475305000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25914.92 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.231166 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.203067 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.975146 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2381 38.41% 38.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 18 0.29% 38.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3787 61.09% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 12 0.19% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads +system.physmem.totQLat 394563559000 # Total ticks spent queuing +system.physmem.totMemAccLat 681341509000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76474120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25797.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44664.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.23 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44547.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.66 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.12 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.49 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.85 # Average write queue length when enqueuing -system.physmem.readRowHits 14297424 # Number of row buffer hits during reads -system.physmem.writeRowHits 89638 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.61 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.40 # Average write queue length when enqueuing +system.physmem.readRowHits 14297661 # Number of row buffer hits during reads +system.physmem.writeRowHits 89445 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.68 # Row buffer hit rate for writes -system.physmem.avgGap 159377.63 # Average gap between requests +system.physmem.writeRowHitRate 83.72 # Row buffer hit rate for writes +system.physmem.avgGap 159307.76 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2210132306750 # Time in different power states -system.physmem.memoryStateTime::REF 85740200000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2209628504250 # Time in different power states +system.physmem.memoryStateTime::REF 85698860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 271799415750 # Time in different power states +system.physmem.memoryStateTime::ACT 271106544500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory @@ -274,49 +275,49 @@ system.realview.nvmem.bw_inst_read::cpu.inst 100 system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54704015 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16349240 # Transaction distribution -system.membus.trans_dist::ReadResp 16349240 # Transaction distribution +system.membus.throughput 54713053 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16348871 # Transaction distribution +system.membus.trans_dist::ReadResp 16348871 # Transaction distribution system.membus.trans_dist::WriteReq 763365 # Transaction distribution system.membus.trans_dist::WriteResp 763365 # Transaction distribution -system.membus.trans_dist::Writeback 59840 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4671 # Transaction distribution -system.membus.trans_dist::ReadExReq 131634 # Transaction distribution -system.membus.trans_dist::ReadExResp 131634 # Transaction distribution +system.membus.trans_dist::Writeback 59552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4670 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4670 # Transaction distribution +system.membus.trans_dist::ReadExReq 131585 # Transaction distribution +system.membus.trans_dist::ReadExResp 131585 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383068 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892024 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278902 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34557660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34556534 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390502 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16953376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19351738 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908832 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19307194 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140462266 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140462266 # Total data (bytes) +system.membus.tot_pkt_size::total 140417722 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140417722 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1731218500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1781248000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3525000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3519500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17560732500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17618628000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4805026968 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4827706725 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37408380500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37448813750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -324,7 +325,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48098342 # Throughput (bytes/s) +system.iobus.throughput 48121550 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322172 # Transaction distribution system.iobus.trans_dist::ReadResp 16322172 # Transaction distribution system.iobus.trans_dist::WriteReq 8178 # Transaction distribution @@ -434,18 +435,18 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374890000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38224979500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38181688250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 12907759 # Number of BP lookups -system.cpu.branchPred.condPredicted 9898849 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1085572 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8888360 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6291175 # Number of BTB hits +system.cpu.branchPred.lookups 12541574 # Number of BP lookups +system.cpu.branchPred.condPredicted 9090690 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1061681 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8536244 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6183587 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.779930 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1515479 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 141893 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.439202 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1558068 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 139509 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -469,25 +470,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 15416418 # DTB read hits -system.cpu.dtb.read_misses 42733 # DTB read misses -system.cpu.dtb.write_hits 11344011 # DTB write hits -system.cpu.dtb.write_misses 3796 # DTB write misses +system.cpu.dtb.read_hits 13629654 # DTB read hits +system.cpu.dtb.read_misses 33608 # DTB read misses +system.cpu.dtb.write_hits 11376786 # DTB write hits +system.cpu.dtb.write_misses 3775 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3452 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1264 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1586 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 251 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 531 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15459151 # DTB read accesses -system.cpu.dtb.write_accesses 11347807 # DTB write accesses +system.cpu.dtb.perms_faults 593 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 13663262 # DTB read accesses +system.cpu.dtb.write_accesses 11380561 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26760429 # DTB hits -system.cpu.dtb.misses 46529 # DTB misses -system.cpu.dtb.accesses 26806958 # DTB accesses +system.cpu.dtb.hits 25006440 # DTB hits +system.cpu.dtb.misses 37383 # DTB misses +system.cpu.dtb.accesses 25043823 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -509,8 +510,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 23352687 # ITB inst hits -system.cpu.itb.inst_misses 9286 # ITB inst misses +system.cpu.itb.inst_hits 22903214 # ITB inst hits +system.cpu.itb.inst_misses 9061 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -519,84 +520,84 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2392 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2388 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4189 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 5760 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 23361973 # ITB inst accesses -system.cpu.itb.hits 23352687 # DTB hits -system.cpu.itb.misses 9286 # DTB misses -system.cpu.itb.accesses 23361973 # DTB accesses -system.cpu.numCycles 576983411 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 22912275 # ITB inst accesses +system.cpu.itb.hits 22903214 # DTB hits +system.cpu.itb.misses 9061 # DTB misses +system.cpu.itb.accesses 22912275 # DTB accesses +system.cpu.numCycles 572663270 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60592948 # Number of instructions committed -system.cpu.committedOps 77887482 # Number of ops (including micro ops) committed -system.cpu.discardedOps 3584241 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 77491 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 4560301069 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 9.522287 # CPI: cycles per instruction -system.cpu.ipc 0.105017 # IPC: instructions per cycle +system.cpu.committedInsts 60593470 # Number of instructions committed +system.cpu.committedOps 72944147 # Number of ops (including micro ops) committed +system.cpu.discardedOps 3225433 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 77492 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 4562060973 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 9.450907 # CPI: cycles per instruction +system.cpu.ipc 0.105810 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 82977 # number of quiesce instructions executed -system.cpu.tickCycles 470832364 # Number of cycles that the object actually ticked -system.cpu.idleCycles 106151047 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 1545254 # number of replacements -system.cpu.icache.tags.tagsinuse 511.467506 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 21802506 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1545766 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.104661 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 10068892000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.467506 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998960 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998960 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 82978 # number of quiesce instructions executed +system.cpu.tickCycles 466702382 # Number of cycles that the object actually ticked +system.cpu.idleCycles 105960888 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 1529303 # number of replacements +system.cpu.icache.tags.tagsinuse 511.463660 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 21367406 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1529815 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.967314 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 9992606000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.463660 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998952 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998952 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 24894039 # Number of tag accesses -system.cpu.icache.tags.data_accesses 24894039 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 21802506 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 21802506 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 21802506 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 21802506 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 21802506 # number of overall hits -system.cpu.icache.overall_hits::total 21802506 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1545767 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1545767 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1545767 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1545767 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1545767 # number of overall misses -system.cpu.icache.overall_misses::total 1545767 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20898816329 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20898816329 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20898816329 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20898816329 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20898816329 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20898816329 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23348273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23348273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23348273 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23348273 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23348273 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23348273 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066205 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.066205 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.066205 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.066205 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.066205 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.066205 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13520.030075 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13520.030075 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13520.030075 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13520.030075 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13520.030075 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13520.030075 # average overall miss latency +system.cpu.icache.tags.tag_accesses 24427037 # Number of tag accesses +system.cpu.icache.tags.data_accesses 24427037 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 21367406 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 21367406 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 21367406 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 21367406 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 21367406 # number of overall hits +system.cpu.icache.overall_hits::total 21367406 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1529816 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1529816 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1529816 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1529816 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1529816 # number of overall misses +system.cpu.icache.overall_misses::total 1529816 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20677210137 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20677210137 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20677210137 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20677210137 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20677210137 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20677210137 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22897222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22897222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22897222 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22897222 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22897222 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22897222 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066812 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.066812 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.066812 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.066812 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.066812 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.066812 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13516.141900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13516.141900 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13516.141900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13516.141900 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -605,198 +606,198 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1545767 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1545767 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1545767 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1545767 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1545767 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1545767 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17801487671 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17801487671 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17801487671 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17801487671 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17801487671 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17801487671 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172412750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172412750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172412750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 172412750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066205 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.066205 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.066205 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11516.281348 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11516.281348 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11516.281348 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11516.281348 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11516.281348 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11516.281348 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1529816 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1529816 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1529816 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1529816 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1529816 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1529816 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17611902863 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17611902863 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17611902863 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17611902863 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17611902863 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17611902863 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172141250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172141250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172141250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 172141250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066812 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.066812 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.066812 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11512.432125 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11512.432125 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 71776562 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3214470 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3214469 # Transaction distribution +system.cpu.toL2Bus.throughput 71285625 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3182019 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3182018 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 602969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2961 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247546 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3094256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5780457 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29847 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9031212 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 98954304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84855034 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 45620 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214364 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 184069322 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 184069322 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 229740 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3400466435 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 600964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247467 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3062398 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5774016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28971 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 100817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8966202 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 97936512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84584698 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43908 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 166616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 182731734 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 182731734 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 218488 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3381194945 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2325579079 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2301585887 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2551211790 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2547997212 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18447489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 18000487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 73062749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 59164999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 65493 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51631.050557 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2439202 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 130882 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.636650 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2525290748000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36364.368368 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.573566 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 65085 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51558.734735 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2407104 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 130473 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.449058 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2524856942500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36497.819876 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.059887 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15253.108047 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.554876 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000207 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 15046.854396 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.556913 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000215 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.232744 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.787827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2430 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6701 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56138 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000153 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 23227461 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 23227461 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53573 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11403 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1910560 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1975536 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 602969 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 602969 # number of Writeback hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.229597 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.786724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65374 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2560 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6585 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56117 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997528 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 22967155 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 22967155 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 41633 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10975 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1892880 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1945488 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 600964 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 600964 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.inst 25 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 25 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 114177 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 114177 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 53573 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 11403 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 2024737 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2089713 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 53573 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 11403 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 2024737 # number of overall hits -system.cpu.l2cache.overall_hits::total 2089713 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 18 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.inst 114159 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 114159 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 41633 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10975 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2007039 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2059647 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 41633 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10975 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2007039 # number of overall hits +system.cpu.l2cache.overall_hits::total 2059647 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 24020 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 24040 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2936 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2936 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 133369 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133369 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 18 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 23661 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23684 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2947 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2947 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 133308 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133308 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 157389 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 157409 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 18 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 156969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156992 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 157389 # number of overall misses -system.cpu.l2cache.overall_misses::total 157409 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1388250 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 156969 # number of overall misses +system.cpu.l2cache.overall_misses::total 156992 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1631500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1729894000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1731431750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 394983 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 394983 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9208617265 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9208617265 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1388250 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1700660750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1702441750 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 347985 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 347985 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9353977027 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9353977027 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1631500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10938511265 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10940049015 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1388250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11054637777 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11056418777 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1631500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10938511265 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10940049015 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53591 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11405 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1934580 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1999576 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 602969 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 602969 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2961 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247546 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247546 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53591 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 11405 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 2182126 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2247122 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53591 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 11405 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2182126 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2247122 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000336 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000175 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.012023 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991557 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991557 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538765 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.538765 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000336 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000175 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072126 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.070049 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000336 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000175 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072126 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.070049 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77125 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 11054637777 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11056418777 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 41654 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10977 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1916541 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1969172 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 600964 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 600964 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2972 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2972 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247467 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247467 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 41654 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10977 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 2164008 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2216639 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 41654 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10977 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2164008 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2216639 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000504 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000182 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012346 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.012027 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991588 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991588 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538690 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.538690 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000504 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000182 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072536 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.070824 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000504 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000182 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072536 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.070824 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77690.476190 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72018.900916 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72022.951331 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 134.530995 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 134.530995 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69046.159640 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69046.159640 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77125 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71876.114704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71881.512836 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 118.081099 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 118.081099 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70168.159653 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70168.159653 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77690.476190 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69499.846018 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69500.784676 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77125 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70425.611280 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70426.638154 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77690.476190 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69499.846018 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69500.784676 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70425.611280 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70426.638154 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -805,84 +806,84 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59840 # number of writebacks -system.cpu.l2cache.writebacks::total 59840 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 18 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 59552 # number of writebacks +system.cpu.l2cache.writebacks::total 59552 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23950 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23970 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2936 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2936 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133369 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133369 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 18 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23592 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23615 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2947 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2947 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133308 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133308 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 157319 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 157339 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 18 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 156900 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156923 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 157319 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 157339 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1165250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 156900 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156923 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1370000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1425512750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1426803000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29363936 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29363936 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7535729235 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7535729235 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1165250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1400834750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1402329750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29473947 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29473947 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7655220473 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7655220473 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1370000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8961241985 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8962532235 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1165250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9056055223 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9057550223 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1370000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8961241985 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8962532235 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167312402000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167312402000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707876361 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707876361 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184020278361 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184020278361 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000336 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000175 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012380 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011988 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991557 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991557 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538765 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538765 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000336 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000175 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072094 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.070018 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000336 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000175 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072094 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.070018 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9056055223 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9057550223 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167362107750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167362107750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707879855 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707879855 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184069987605 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184069987605 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012310 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011992 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991588 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991588 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538690 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538690 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072504 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.070793 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072504 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.070793 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59520.365344 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59524.530663 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.340599 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.340599 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56502.854749 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56502.854749 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59377.532638 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59383.008681 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.339328 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.339328 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57425.064310 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57425.064310 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56962.235871 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56963.195616 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56962.235871 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56963.195616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -890,86 +891,86 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 637780 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.959208 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23638258 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 638292 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.033612 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 227414250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959208 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 635561 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.959259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21828853 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 636073 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.318157 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 227074250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959259 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999920 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999920 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 98967232 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 98967232 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 13401610 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13401610 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 9749262 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9749262 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236772 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236772 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 247602 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 23150872 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23150872 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 23150872 # number of overall hits -system.cpu.dcache.overall_hits::total 23150872 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 462868 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 462868 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 473290 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 473290 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10831 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 10831 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.inst 936158 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 936158 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 936158 # number of overall misses -system.cpu.dcache.overall_misses::total 936158 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7014286436 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7014286436 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21912161323 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21912161323 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 150765000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 150765000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 28926447759 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28926447759 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 28926447759 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28926447759 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 13864478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13864478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 10222552 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222552 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247603 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247603 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 247602 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247602 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 24087030 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24087030 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 24087030 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24087030 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.033385 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033385 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046299 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046299 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043743 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043743 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.038866 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.038866 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.038866 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038866 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15153.967083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15153.967083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46297.537077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46297.537077 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13919.767335 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13919.767335 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 30899.108654 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30899.108654 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 30899.108654 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30899.108654 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 91724261 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 91724261 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 11595405 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11595405 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 9746069 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9746069 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236744 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236744 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 247613 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247613 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 21341474 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21341474 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 21341474 # number of overall hits +system.cpu.dcache.overall_hits::total 21341474 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 458732 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 458732 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 476614 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 476614 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10870 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 10870 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.inst 935346 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 935346 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 935346 # number of overall misses +system.cpu.dcache.overall_misses::total 935346 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6943170934 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6943170934 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 22231593506 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22231593506 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 151835000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 151835000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 29174764440 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29174764440 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 29174764440 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29174764440 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 12054137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12054137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 10222683 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222683 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247614 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247614 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 247613 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247613 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 22276820 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 22276820 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 22276820 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 22276820 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.038056 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.038056 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046623 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046623 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043899 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043899 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.041987 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.041987 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.041987 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.041987 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15135.571388 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15135.571388 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46644.860424 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46644.860424 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13968.261270 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13968.261270 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31191.414129 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31191.414129 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -978,64 +979,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 602969 # number of writebacks -system.cpu.dcache.writebacks::total 602969 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 82884 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 82884 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 222784 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 222784 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 68 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 68 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 305668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 305668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 305668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 305668 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 379984 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 379984 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250506 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250506 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10763 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 10763 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 630490 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 630490 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 630490 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 630490 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4859150309 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4859150309 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10668108512 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10668108512 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 128265000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128265000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15527258821 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15527258821 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15527258821 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15527258821 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182582279000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182582279000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058245639 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058245639 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208640524639 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208640524639 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.027407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043469 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043469 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.026175 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026175 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.026175 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026175 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12787.776088 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12787.776088 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 42586.239499 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42586.239499 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11917.216389 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11917.216389 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24627.288016 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24627.288016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24627.288016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24627.288016 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 600964 # number of writebacks +system.cpu.dcache.writebacks::total 600964 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80923 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 80923 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 226176 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 226176 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 72 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 72 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 307099 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 307099 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 307099 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 307099 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377809 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 377809 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250438 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250438 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10798 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 10798 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 628247 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 628247 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 628247 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 628247 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4823958811 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4823958811 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10813361832 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10813361832 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129211000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129211000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15637320643 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15637320643 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15637320643 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15637320643 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182632094250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182632094250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058171145 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058171145 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208690265395 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208690265395 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031343 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031343 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024498 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024498 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043608 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043608 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028202 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028202 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12768.247477 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12768.247477 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43177.799823 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43177.799823 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11966.197444 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11966.197444 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -1059,10 +1060,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1738541884500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1738541884500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1738541884500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1738541884500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736623648250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736623648250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 76ba3533e..05396d247 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525889 # Number of seconds simulated -sim_ticks 2525888859000 # Number of ticks simulated -final_tick 2525888859000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542203 # Number of seconds simulated +sim_ticks 2542202956000 # Number of ticks simulated +final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55568 # Simulator instruction rate (inst/s) -host_op_rate 71500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2327295647 # Simulator tick rate (ticks/s) -host_mem_usage 420424 # Number of bytes of host memory used -host_seconds 1085.33 # Real time elapsed on the host -sim_insts 60309513 # Number of instructions simulated -sim_ops 77601128 # Number of ops (including micro ops) simulated +host_inst_rate 40853 # Simulator instruction rate (inst/s) +host_op_rate 49218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1721973071 # Simulator tick rate (ticks/s) +host_mem_usage 411692 # Number of bytes of host memory used +host_seconds 1476.33 # Real time elapsed on the host +sim_insts 60311945 # Number of instructions simulated +sim_ops 72661478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094168 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory +system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory +system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142132 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096846 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 14991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15295607 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47324990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51242245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692556 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47324990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53934801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096846 # Number of read requests accepted -system.physmem.writeReqs 813159 # Number of write requests accepted -system.physmem.readBursts 15096846 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 961407104 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4791040 # Total number of bytes read from write queue -system.physmem.bytesWritten 6818432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129432216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 74860 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706594 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943526 # Per bank write bursts -system.physmem.perBankRdBursts::1 937990 # Per bank write bursts -system.physmem.perBankRdBursts::2 937469 # Per bank write bursts -system.physmem.perBankRdBursts::3 937431 # Per bank write bursts -system.physmem.perBankRdBursts::4 943079 # Per bank write bursts -system.physmem.perBankRdBursts::5 938170 # Per bank write bursts -system.physmem.perBankRdBursts::6 937203 # Per bank write bursts -system.physmem.perBankRdBursts::7 936910 # Per bank write bursts -system.physmem.perBankRdBursts::8 943866 # Per bank write bursts -system.physmem.perBankRdBursts::9 938107 # Per bank write bursts -system.physmem.perBankRdBursts::10 936563 # Per bank write bursts -system.physmem.perBankRdBursts::11 936045 # Per bank write bursts -system.physmem.perBankRdBursts::12 943886 # Per bank write bursts -system.physmem.perBankRdBursts::13 937531 # Per bank write bursts -system.physmem.perBankRdBursts::14 937186 # Per bank write bursts -system.physmem.perBankRdBursts::15 937024 # Per bank write bursts -system.physmem.perBankWrBursts::0 6617 # Per bank write bursts -system.physmem.perBankWrBursts::1 6376 # Per bank write bursts -system.physmem.perBankWrBursts::2 6529 # Per bank write bursts -system.physmem.perBankWrBursts::3 6558 # Per bank write bursts -system.physmem.perBankWrBursts::4 6459 # Per bank write bursts -system.physmem.perBankWrBursts::5 6705 # Per bank write bursts -system.physmem.perBankWrBursts::6 6711 # Per bank write bursts -system.physmem.perBankWrBursts::7 6649 # Per bank write bursts -system.physmem.perBankWrBursts::8 7036 # Per bank write bursts -system.physmem.perBankWrBursts::9 6794 # Per bank write bursts -system.physmem.perBankWrBursts::10 6454 # Per bank write bursts -system.physmem.perBankWrBursts::11 6111 # Per bank write bursts -system.physmem.perBankWrBursts::12 7073 # Per bank write bursts -system.physmem.perBankWrBursts::13 6679 # Per bank write bursts -system.physmem.perBankWrBursts::14 6963 # Per bank write bursts -system.physmem.perBankWrBursts::15 6824 # Per bank write bursts +system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47639992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51523292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1472436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15295607 # Number of read requests accepted +system.physmem.writeReqs 812506 # Number of write requests accepted +system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue +system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955786 # Per bank write bursts +system.physmem.perBankRdBursts::1 955478 # Per bank write bursts +system.physmem.perBankRdBursts::2 953003 # Per bank write bursts +system.physmem.perBankRdBursts::3 951059 # Per bank write bursts +system.physmem.perBankRdBursts::4 958601 # Per bank write bursts +system.physmem.perBankRdBursts::5 955602 # Per bank write bursts +system.physmem.perBankRdBursts::6 952653 # Per bank write bursts +system.physmem.perBankRdBursts::7 950407 # Per bank write bursts +system.physmem.perBankRdBursts::8 956154 # Per bank write bursts +system.physmem.perBankRdBursts::9 955874 # Per bank write bursts +system.physmem.perBankRdBursts::10 952889 # Per bank write bursts +system.physmem.perBankRdBursts::11 950148 # Per bank write bursts +system.physmem.perBankRdBursts::12 956166 # Per bank write bursts +system.physmem.perBankRdBursts::13 955918 # Per bank write bursts +system.physmem.perBankRdBursts::14 953918 # Per bank write bursts +system.physmem.perBankRdBursts::15 950940 # Per bank write bursts +system.physmem.perBankWrBursts::0 6546 # Per bank write bursts +system.physmem.perBankWrBursts::1 6352 # Per bank write bursts +system.physmem.perBankWrBursts::2 6488 # Per bank write bursts +system.physmem.perBankWrBursts::3 6518 # Per bank write bursts +system.physmem.perBankWrBursts::4 6421 # Per bank write bursts +system.physmem.perBankWrBursts::5 6701 # Per bank write bursts +system.physmem.perBankWrBursts::6 6665 # Per bank write bursts +system.physmem.perBankWrBursts::7 6611 # Per bank write bursts +system.physmem.perBankWrBursts::8 6966 # Per bank write bursts +system.physmem.perBankWrBursts::9 6759 # Per bank write bursts +system.physmem.perBankWrBursts::10 6421 # Per bank write bursts +system.physmem.perBankWrBursts::11 6055 # Per bank write bursts +system.physmem.perBankWrBursts::12 7037 # Per bank write bursts +system.physmem.perBankWrBursts::13 6645 # Per bank write bursts +system.physmem.perBankWrBursts::14 6920 # Per bank write bursts +system.physmem.perBankWrBursts::15 6806 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525887732500 # Total gap between requests +system.physmem.totGap 2542201638000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 38 # Read request sizes (log2) -system.physmem.readPktSize::3 14942208 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::2 18 # Read request sizes (log2) +system.physmem.readPktSize::3 15138826 # Read request sizes (log2) +system.physmem.readPktSize::4 3351 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154600 # Read request sizes (log2) +system.physmem.readPktSize::6 153412 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59141 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1057329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 995712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 953847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1057444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 956989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1015779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2635918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2545995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3318157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 125455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 108163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 99319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 95398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58488 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1110293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 964892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 965548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1076032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 973735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1036027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2680967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2587988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3368391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 111642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 103064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98734 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -171,28 +171,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -220,113 +220,113 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 995372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 972.727318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 907.205467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 202.336600 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22984 2.31% 2.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19752 1.98% 4.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8337 0.84% 5.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2265 0.23% 5.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2301 0.23% 5.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1840 0.18% 5.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8587 0.86% 6.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 978 0.10% 6.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 928328 93.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 995372 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2406.981894 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 114987.414706 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6237 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.070662 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.017388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.386394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3585 57.44% 57.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 32 0.51% 57.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1616 25.89% 83.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 845 13.54% 97.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 54 0.87% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 36 0.58% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 33 0.53% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 31 0.50% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.14% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads -system.physmem.totQLat 389024977250 # Total ticks spent queuing -system.physmem.totMemAccLat 670687214750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75109930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25897.04 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads +system.physmem.totQLat 395449280750 # Total ticks spent queuing +system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44647.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.99 # Data bus utilization in percentage -system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.02 # Data bus utilization in percentage +system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing -system.physmem.readRowHits 14042089 # Number of row buffer hits during reads -system.physmem.writeRowHits 91063 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing +system.physmem.readRowHits 14269193 # Number of row buffer hits during reads +system.physmem.writeRowHits 90708 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes -system.physmem.avgGap 158760.96 # Average gap between requests +system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes +system.physmem.avgGap 157821.19 # Average gap between requests system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2186215098000 # Time in different power states -system.physmem.memoryStateTime::REF 84344780000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states +system.physmem.memoryStateTime::REF 84889480000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 255323240750 # Time in different power states +system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54884184 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149487 # Transaction distribution -system.membus.trans_dist::ReadResp 16149487 # Transaction distribution -system.membus.trans_dist::WriteReq 763349 # Transaction distribution -system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59141 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution -system.membus.trans_dist::ReadExReq 131431 # Transaction distribution -system.membus.trans_dist::ReadExResp 131431 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) +system.membus.throughput 55125441 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16348039 # Transaction distribution +system.membus.trans_dist::ReadResp 16348039 # Transaction distribution +system.membus.trans_dist::WriteReq 763357 # Transaction distribution +system.membus.trans_dist::WriteResp 763357 # Transaction distribution +system.membus.trans_dist::Writeback 58488 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution +system.membus.trans_dist::ReadExReq 131651 # Transaction distribution +system.membus.trans_dist::ReadExResp 131651 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272651 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157067 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390450 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16695648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19093686 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138631350 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138631350 # Total data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140140058 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486861000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3602500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17311099000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4710414902 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 36916757411 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -334,15 +334,15 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48271369 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125555 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125555 # Transaction distribution -system.iobus.trans_dist::WriteReq 8174 # Transaction distribution -system.iobus.trans_dist::WriteResp 8174 # Transaction distribution +system.iobus.throughput 48580309 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution +system.iobus.trans_dist::WriteReq 8176 # Transaction distribution +system.iobus.trans_dist::WriteResp 8176 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -362,14 +362,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -389,18 +389,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390450 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121928114 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121928114 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123501006 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -440,22 +440,22 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37649719589 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14910337 # Number of BP lookups -system.cpu.branchPred.condPredicted 11976867 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705848 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9580478 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7742107 # Number of BTB hits +system.cpu.branchPred.lookups 13201290 # Number of BP lookups +system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.811281 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1408303 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72648 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -479,25 +479,25 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987595 # DTB read hits -system.cpu.checker.dtb.read_misses 7306 # DTB read misses -system.cpu.checker.dtb.write_hits 11227720 # DTB write hits -system.cpu.checker.dtb.write_misses 2191 # DTB write misses +system.cpu.checker.dtb.read_hits 13156743 # DTB read hits +system.cpu.checker.dtb.read_misses 7321 # DTB read misses +system.cpu.checker.dtb.write_hits 11227340 # DTB write hits +system.cpu.checker.dtb.write_misses 2193 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 3398 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994901 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229911 # DTB write accesses +system.cpu.checker.dtb.read_accesses 13164064 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229533 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215315 # DTB hits -system.cpu.checker.dtb.misses 9497 # DTB misses -system.cpu.checker.dtb.accesses 26224812 # DTB accesses +system.cpu.checker.dtb.hits 24384083 # DTB hits +system.cpu.checker.dtb.misses 9514 # DTB misses +system.cpu.checker.dtb.accesses 24393597 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -519,7 +519,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61483491 # ITB inst hits +system.cpu.checker.itb.inst_hits 61486079 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -536,11 +536,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61487964 # ITB inst accesses -system.cpu.checker.itb.hits 61483491 # DTB hits +system.cpu.checker.itb.inst_accesses 61490552 # ITB inst accesses +system.cpu.checker.itb.hits 61486079 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61487964 # DTB accesses -system.cpu.checker.numCycles 77886925 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61490552 # DTB accesses +system.cpu.checker.numCycles 72947431 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -566,25 +566,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51097792 # DTB read hits -system.cpu.dtb.read_misses 64987 # DTB read misses -system.cpu.dtb.write_hits 11709971 # DTB write hits -system.cpu.dtb.write_misses 15921 # DTB write misses +system.cpu.dtb.read_hits 31642294 # DTB read hits +system.cpu.dtb.read_misses 39524 # DTB read misses +system.cpu.dtb.write_hits 11381361 # DTB write hits +system.cpu.dtb.write_misses 10135 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3472 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2569 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 428 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51162779 # DTB read accesses -system.cpu.dtb.write_accesses 11725892 # DTB write accesses +system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 31681818 # DTB read accesses +system.cpu.dtb.write_accesses 11391496 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62807763 # DTB hits -system.cpu.dtb.misses 80908 # DTB misses -system.cpu.dtb.accesses 62888671 # DTB accesses +system.cpu.dtb.hits 43023655 # DTB hits +system.cpu.dtb.misses 49659 # DTB misses +system.cpu.dtb.accesses 43073314 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -606,8 +606,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11575507 # ITB inst hits -system.cpu.itb.inst_misses 11335 # ITB inst misses +system.cpu.itb.inst_hits 24159481 # ITB inst hits +system.cpu.itb.inst_misses 10516 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -616,607 +616,598 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2514 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2954 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11586842 # ITB inst accesses -system.cpu.itb.hits 11575507 # DTB hits -system.cpu.itb.misses 11335 # DTB misses -system.cpu.itb.accesses 11586842 # DTB accesses -system.cpu.numCycles 476238509 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 24169997 # ITB inst accesses +system.cpu.itb.hits 24159481 # DTB hits +system.cpu.itb.misses 10516 # DTB misses +system.cpu.itb.accesses 24169997 # DTB accesses +system.cpu.numCycles 499350041 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29789702 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91027179 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14910337 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9150410 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20302096 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4754274 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125108 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93772455 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2699 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88682 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2727734 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 553 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11572027 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 712397 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5390 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150113292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.756026 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.113644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 129826802 86.49% 86.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1312716 0.87% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1720953 1.15% 88.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2304331 1.54% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2116294 1.41% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1112529 0.74% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2605432 1.74% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 752346 0.50% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8361889 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150113292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031309 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.191138 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31268958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96222513 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18495001 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 992442 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3134378 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1970530 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172531 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 108153308 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572201 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3134378 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32906794 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14229038 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 56831984 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17995352 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25015746 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103064055 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1610 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17097046 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 19764397 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2757051 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 1781 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107250734 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 477314257 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 435890251 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10500 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727504 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28523229 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1172187 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1078501 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 11007211 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19896895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13369840 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2003415 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2457274 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95806828 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1986007 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122955094 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 190842 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19616274 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 49695395 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 503680 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150113292 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819082 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.543742 # Number of insts issued each cycle +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.548412 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106692829 71.07% 71.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13471343 8.97% 80.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6554897 4.37% 84.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5548193 3.70% 88.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12665338 8.44% 96.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2805396 1.87% 98.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723552 1.15% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 514218 0.34% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 137526 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 430558497 86.88% 86.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150113292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66740 0.75% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8421993 94.18% 94.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 453824 5.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58064867 47.22% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52433900 42.64% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12332230 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122955094 # Type of FU issued -system.cpu.iq.rate 0.258180 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8942563 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.072730 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 405214220 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117427083 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85619955 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23208 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131856805 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 652625 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued +system.cpu.iq.rate 0.188050 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4242114 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5511 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 31676 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1637740 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33981236 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 675243 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3134378 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11621778 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1344860 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98019144 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 177250 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19896895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13369840 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1412264 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 282212 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 925122 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 31676 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351157 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270951 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 622108 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120868290 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51786364 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2086804 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 226309 # number of nop insts executed -system.cpu.iew.exec_refs 64008543 # number of memory reference insts executed -system.cpu.iew.exec_branches 11843747 # Number of branches executed -system.cpu.iew.exec_stores 12222179 # Number of stores executed -system.cpu.iew.exec_rate 0.253798 # Inst execution rate -system.cpu.iew.wb_sent 119919333 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85630251 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47892202 # num instructions producing a value -system.cpu.iew.wb_consumers 88557277 # num instructions consuming a value +system.cpu.iew.exec_nop 176010 # number of nop insts executed +system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed +system.cpu.iew.exec_branches 10791342 # Number of branches executed +system.cpu.iew.exec_stores 11888889 # Number of stores executed +system.cpu.iew.exec_rate 0.186738 # Inst execution rate +system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back +system.cpu.iew.wb_producers 35465784 # num instructions producing a value +system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179805 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.540805 # average fanout of values written-back +system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19373634 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482327 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535963 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146978914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.528998 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.513466 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118714103 80.77% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14514329 9.88% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3718532 2.53% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2215097 1.51% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1629859 1.11% 95.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1057435 0.72% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1495738 1.02% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 696782 0.47% 98.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2937039 2.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146978914 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60459894 # Number of instructions committed -system.cpu.commit.committedOps 77751509 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60462326 # Number of instructions committed +system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386881 # Number of memory references committed -system.cpu.commit.loads 15654781 # Number of loads committed -system.cpu.commit.membars 403574 # Number of memory barriers committed -system.cpu.commit.branches 10306383 # Number of branches committed +system.cpu.commit.refs 25244569 # Number of memory references committed +system.cpu.commit.loads 13512926 # Number of loads committed +system.cpu.commit.membars 403660 # Number of memory barriers committed +system.cpu.commit.branches 10308073 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69191543 # Number of committed integer instructions. -system.cpu.commit.function_calls 991261 # Number of function calls committed. +system.cpu.commit.int_insts 64250122 # Number of committed integer instructions. +system.cpu.commit.function_calls 991634 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 50274580 64.66% 64.66% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 15654781 20.13% 84.91% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11732100 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 77751509 # Class of committed instruction -system.cpu.commit.bw_lim_events 2937039 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction +system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239318561 # The number of ROB reads -system.cpu.rob.rob_writes 197472000 # The number of ROB writes -system.cpu.timesIdled 1764819 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 326125217 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575456172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309513 # Number of Instructions Simulated -system.cpu.committedOps 77601128 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.896574 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.896574 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126637 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126637 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548833946 # number of integer regfile reads -system.cpu.int_regfile_writes 87707846 # number of integer regfile writes -system.cpu.fp_regfile_reads 8328 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 264312368 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173237 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58892733 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607940 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5797376 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30926 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128827 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7919103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85556470 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148561726 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148561726 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 194772 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129487727 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 568287463 # The number of ROB reads +system.cpu.rob.rob_writes 154414560 # The number of ROB writes +system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60311945 # Number of Instructions Simulated +system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads +system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 109116898 # number of integer regfile reads +system.cpu.int_regfile_writes 47012348 # number of integer regfile writes +system.cpu.fp_regfile_reads 8305 # number of floating regfile reads +system.cpu.fp_regfile_writes 2780 # number of floating regfile writes +system.cpu.cc_regfile_reads 320404209 # number of cc regfile reads +system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes +system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes +system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474700416 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1447056987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550487184 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2544187527 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20248986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 17686240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74797546 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 51535649 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980898 # number of replacements -system.cpu.icache.tags.tagsinuse 511.584882 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10510158 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981410 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.709243 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6868426250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.584882 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999189 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 959881 # number of replacements +system.cpu.icache.tags.tagsinuse 511.383361 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23149457 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 960393 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 24.104150 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 11344582250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.383361 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12553342 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12553342 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10510158 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10510158 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10510158 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10510158 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10510158 # number of overall hits -system.cpu.icache.overall_hits::total 10510158 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061739 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061739 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061739 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061739 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061739 # number of overall misses -system.cpu.icache.overall_misses::total 1061739 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14266290615 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14266290615 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14266290615 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14266290615 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14266290615 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14266290615 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11571897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11571897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11571897 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11571897 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11571897 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11571897 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091752 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091752 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091752 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091752 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091752 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091752 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13436.720903 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13436.720903 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13436.720903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13436.720903 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7331 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 116 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.883582 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 116 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 25115239 # Number of tag accesses +system.cpu.icache.tags.data_accesses 25115239 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23149457 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23149457 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23149457 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23149457 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23149457 # number of overall hits +system.cpu.icache.overall_hits::total 23149457 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1005369 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1005369 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1005369 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1005369 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1005369 # number of overall misses +system.cpu.icache.overall_misses::total 1005369 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13656038478 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13656038478 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13656038478 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13656038478 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13656038478 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13656038478 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24154826 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24154826 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24154826 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24154826 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24154826 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24154826 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13583.110756 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13583.110756 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 119 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.588235 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80293 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 80293 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 80293 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 80293 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 80293 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 80293 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981446 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981446 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981446 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981446 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981446 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981446 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11573178578 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11573178578 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11573178578 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11573178578 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11573178578 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11573178578 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8964000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8964000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8964000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8964000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084813 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.084813 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.084813 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11791.966729 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11791.966729 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44956 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 44956 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 44956 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 44956 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 44956 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 44956 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960413 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 960413 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 960413 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 960413 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 960413 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 960413 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283890760 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11283890760 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283890760 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11283890760 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283890760 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11283890760 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223026500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223026500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223026500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 223026500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039761 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.039761 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.039761 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64369 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51363.817213 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1888922 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129761 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.556932 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2490733870000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36937.336839 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 33.862464 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000252 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8170.435646 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6222.182012 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563619 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000517 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 63302 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51128.734687 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1829071 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 128690 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.213000 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2530789670500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37302.599889 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.814194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7723.154288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.165612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.569193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000104 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124671 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.094943 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783750 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65369 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3050 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54961 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997452 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18802940 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18802940 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54086 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10683 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967938 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387449 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1420156 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607940 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607940 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112904 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112904 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 54086 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10683 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967938 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500353 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1533060 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 54086 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10683 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967938 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500353 # number of overall hits -system.cpu.l2cache.overall_hits::total 1533060 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 48 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12347 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10729 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23125 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133201 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133201 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 48 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12347 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143930 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156326 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 48 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12347 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143930 # number of overall misses -system.cpu.l2cache.overall_misses::total 156326 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3943500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 83000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 890764250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 800380499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1695171249 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 583475 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 583475 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9778985980 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9778985980 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3943500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 83000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 890764250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10579366479 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11474157229 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3943500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 83000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 890764250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10579366479 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11474157229 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54134 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10684 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 980285 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 398178 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1443281 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607940 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607940 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246105 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54134 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10684 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 980285 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 644283 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1689386 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54134 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10684 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 980285 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 644283 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1689386 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000887 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000094 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012595 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026945 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016023 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985502 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985502 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.272727 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.272727 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541236 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541236 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000887 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000094 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012595 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223396 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092534 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000887 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000094 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012595 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223396 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092534 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 82156.250000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72144.184822 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74599.729611 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73304.702659 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 199.615121 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 199.615121 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73415.259495 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73415.259495 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 82156.250000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72144.184822 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73503.553665 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73398.905038 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 82156.250000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72144.184822 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73503.553665 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73398.905038 # average overall miss latency +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117846 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.093020 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.780163 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65381 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3024 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6221 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55835 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997635 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18316308 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18316308 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33888 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9476 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 947771 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 377103 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1368238 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 599976 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 599976 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113216 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113216 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 33888 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 9476 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 947771 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 490319 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1481454 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 33888 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 9476 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 947771 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 490319 # number of overall hits +system.cpu.l2cache.overall_hits::total 1481454 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 11654 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10148 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 21816 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2909 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133354 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133354 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 11 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 11654 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143502 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 155170 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 11 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 11654 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143502 # number of overall misses +system.cpu.l2cache.overall_misses::total 155170 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 830265249 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 761175750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1592469999 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 348485 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9338459797 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9338459797 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 830265249 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10099635547 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10930929796 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 830265249 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10099635547 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10930929796 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33899 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9479 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 959425 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 387251 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1390054 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 599976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 599976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2950 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246570 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246570 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33899 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 9479 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 959425 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 633821 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1636624 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33899 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 9479 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 959425 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 633821 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1636624 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000324 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000316 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012147 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026205 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015694 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986102 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986102 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540836 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.540836 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000324 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000316 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012147 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.226408 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.094811 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000324 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000316 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012147 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.226408 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.094811 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71840.909091 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79583.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71242.942252 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75007.464525 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72995.507838 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 119.795462 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 119.795462 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70027.594200 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70027.594200 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70444.865605 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70444.865605 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1225,109 +1216,104 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59141 # number of writebacks -system.cpu.l2cache.writebacks::total 59141 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 48 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12336 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10663 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133201 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133201 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 48 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12336 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143864 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156249 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 48 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12336 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143864 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156249 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3351000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 71000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 734971750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 663368999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1401762749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29236922 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29236922 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8137112520 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8137112520 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3351000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 71000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 734971750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8800481519 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9538875269 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3351000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 71000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 734971750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8800481519 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9538875269 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6435500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942048250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948483750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17498078150 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17498078150 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6435500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184440126400 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184446561900 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026779 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015969 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985502 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985502 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.272727 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541236 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541236 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092489 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092489 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59579.422017 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62212.229110 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60819.279287 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.368115 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.368115 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61088.974707 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61088.974707 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 58488 # number of writebacks +system.cpu.l2cache.writebacks::total 58488 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11640 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10108 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 21761 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133354 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133354 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 11640 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143462 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 155115 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 11640 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143462 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 155115 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 596250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 201250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 683475499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 632292750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1316565749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29106909 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29106909 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7676486703 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7676486703 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 596250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 201250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 683475499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8308779453 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8993052452 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 596250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 201250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 683475499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8308779453 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8993052452 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174348000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167014389750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167188737750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17147727018 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17147727018 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174348000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184162116768 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184336464768 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015655 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.094777 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.094777 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58717.826375 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62553.695093 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60501.160287 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.812650 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.812650 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57564.727740 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57564.727740 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1337,168 +1323,184 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643771 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993313 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21491250 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 644283 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.356848 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 42393250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993313 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 633309 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.949942 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19068560 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 633821 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.085087 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.949942 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101573451 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101573451 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13743815 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13743815 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7253892 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7253892 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242816 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242816 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 20997707 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20997707 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20997707 # number of overall hits -system.cpu.dcache.overall_hits::total 20997707 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 762201 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 762201 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2968429 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2968429 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13530 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13530 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3730630 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3730630 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3730630 # number of overall misses -system.cpu.dcache.overall_misses::total 3730630 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10170757825 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10170757825 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 136412874713 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 136412874713 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184826749 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184826749 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 180503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 180503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 146583632538 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 146583632538 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 146583632538 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 146583632538 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14506016 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14506016 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256346 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256346 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247609 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247609 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24728337 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24728337 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24728337 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24728337 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052544 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052544 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290387 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.290387 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052780 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052780 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.150865 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.150865 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.150865 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.150865 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13343.931358 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13343.931358 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45954.568802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45954.568802 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13660.513599 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13660.513599 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16409.363636 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16409.363636 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39291.924564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39291.924564 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33676 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 25542 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2667 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 316 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.626922 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 80.829114 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 91797001 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 91797001 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11311240 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11311240 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7209458 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7209458 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60823 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60823 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236444 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236444 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 18520698 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18520698 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18581521 # number of overall hits +system.cpu.dcache.overall_hits::total 18581521 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 573261 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 573261 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3012484 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3012484 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 126501 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 126501 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 12988 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 12988 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3585745 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3585745 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3712246 # number of overall misses +system.cpu.dcache.overall_misses::total 3712246 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7216358166 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7216358166 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126016512064 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126016512064 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 178185500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 178185500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133232870230 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133232870230 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133232870230 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133232870230 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 11884501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11884501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10221942 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10221942 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 187324 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 187324 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 249432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 22106443 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 22106443 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 22293767 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 22293767 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048236 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.048236 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675306 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.675306 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052070 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052070 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.162204 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.162204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.166515 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.166515 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12588.259390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12588.259390 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41831.429499 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41831.429499 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13719.240838 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13719.240838 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37156.259084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37156.259084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35890.097324 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35890.097324 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18826 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1227 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.343113 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607940 # number of writebacks -system.cpu.dcache.writebacks::total 607940 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 376141 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 376141 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2719425 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2719425 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3095566 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3095566 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3095566 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3095566 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386060 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386060 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249004 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249004 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635064 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635064 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635064 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635064 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4968476363 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4968476363 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11232028289 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11232028289 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145250501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145250501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 158497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 158497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16200504652 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16200504652 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16200504652 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16200504652 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26891357119 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26891357119 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047533 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047533 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 599976 # number of writebacks +system.cpu.dcache.writebacks::total 599976 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271755 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 271755 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763119 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2763119 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3034874 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3034874 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3034874 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3034874 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 301506 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249365 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249365 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74145 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 74145 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11755 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11755 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 550871 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 550871 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 625016 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 625016 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569781578 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569781578 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10783879319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10783879319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1231283000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1231283000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140188500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140188500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14353660897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14353660897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15584943897 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15584943897 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26599942575 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26599942575 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1522,16 +1524,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1711484214589 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index fcbba5f01..b3c80425c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,155 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.605246 # Number of seconds simulated -sim_ticks 2605245500000 # Number of ticks simulated -final_tick 2605245500000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.621647 # Number of seconds simulated +sim_ticks 2621647051000 # Number of ticks simulated +final_tick 2621647051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66179 # Simulator instruction rate (inst/s) -host_op_rate 85203 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2745863070 # Simulator tick rate (ticks/s) -host_mem_usage 426204 # Number of bytes of host memory used -host_seconds 948.79 # Real time elapsed on the host -sim_insts 62790043 # Number of instructions simulated -sim_ops 80839298 # Number of ops (including micro ops) simulated +host_inst_rate 56801 # Simulator instruction rate (inst/s) +host_op_rate 68443 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2377539464 # Simulator tick rate (ticks/s) +host_mem_usage 411700 # Number of bytes of host memory used +host_seconds 1102.67 # Real time elapsed on the host +sim_insts 62632896 # Number of instructions simulated +sim_ops 75470296 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4351548 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 427968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5241528 # Number of bytes read from this memory -system.physmem.bytes_read::total 131526900 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 427968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4250944 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7280080 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 516048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6568572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 301968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2981560 # Number of bytes read from this memory +system.physmem.bytes_read::total 131479316 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 516048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 301968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 818016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4189696 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 3029096 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 7218832 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6149 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68067 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6687 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81927 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301674 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66421 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823705 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46487184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1670302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 164272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2011913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50485415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 164272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1631687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6525 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1156181 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2794393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1631687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46487184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1676828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 164272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3168095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53279808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15301674 # Number of read requests accepted -system.physmem.writeReqs 823705 # Number of write requests accepted -system.physmem.readBursts 15301674 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823705 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 974584832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4722304 # Total number of bytes read from write queue -system.physmem.bytesWritten 7299840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131526900 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7280080 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 73786 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709619 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14174 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956301 # Per bank write bursts -system.physmem.perBankRdBursts::1 950868 # Per bank write bursts -system.physmem.perBankRdBursts::2 950386 # Per bank write bursts -system.physmem.perBankRdBursts::3 950557 # Per bank write bursts -system.physmem.perBankRdBursts::4 956616 # Per bank write bursts -system.physmem.perBankRdBursts::5 950990 # Per bank write bursts -system.physmem.perBankRdBursts::6 949776 # Per bank write bursts -system.physmem.perBankRdBursts::7 949548 # Per bank write bursts -system.physmem.perBankRdBursts::8 956645 # Per bank write bursts -system.physmem.perBankRdBursts::9 951285 # Per bank write bursts -system.physmem.perBankRdBursts::10 949982 # Per bank write bursts -system.physmem.perBankRdBursts::11 948991 # Per bank write bursts -system.physmem.perBankRdBursts::12 956228 # Per bank write bursts -system.physmem.perBankRdBursts::13 950424 # Per bank write bursts -system.physmem.perBankRdBursts::14 949846 # Per bank write bursts -system.physmem.perBankRdBursts::15 949445 # Per bank write bursts -system.physmem.perBankWrBursts::0 7049 # Per bank write bursts -system.physmem.perBankWrBursts::1 6917 # Per bank write bursts -system.physmem.perBankWrBursts::2 7321 # Per bank write bursts -system.physmem.perBankWrBursts::3 7203 # Per bank write bursts -system.physmem.perBankWrBursts::4 7749 # Per bank write bursts -system.physmem.perBankWrBursts::5 7300 # Per bank write bursts -system.physmem.perBankWrBursts::6 7008 # Per bank write bursts -system.physmem.perBankWrBursts::7 6995 # Per bank write bursts -system.physmem.perBankWrBursts::8 7363 # Per bank write bursts -system.physmem.perBankWrBursts::9 7456 # Per bank write bursts -system.physmem.perBankWrBursts::10 6910 # Per bank write bursts -system.physmem.perBankWrBursts::11 6580 # Per bank write bursts -system.physmem.perBankWrBursts::12 7092 # Per bank write bursts -system.physmem.perBankWrBursts::13 7012 # Per bank write bursts -system.physmem.perBankWrBursts::14 7131 # Per bank write bursts -system.physmem.perBankWrBursts::15 6974 # Per bank write bursts +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10590 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 102693 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4761 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 46605 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15303475 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65464 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 757274 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 822748 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46196351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 196841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2505513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 115183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1137285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50151418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 196841 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 115183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 312024 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1598116 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 1155417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2753548 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1598116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46196351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 196841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3660931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 115183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1137300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 52904966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15303475 # Number of read requests accepted +system.physmem.writeReqs 822748 # Number of write requests accepted +system.physmem.readBursts 15303475 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 822748 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 977402304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2020096 # Total number of bytes read from write queue +system.physmem.bytesWritten 7239040 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131479316 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7218832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 31564 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709609 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12033 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 956536 # Per bank write bursts +system.physmem.perBankRdBursts::1 956505 # Per bank write bursts +system.physmem.perBankRdBursts::2 953083 # Per bank write bursts +system.physmem.perBankRdBursts::3 951219 # Per bank write bursts +system.physmem.perBankRdBursts::4 959451 # Per bank write bursts +system.physmem.perBankRdBursts::5 955886 # Per bank write bursts +system.physmem.perBankRdBursts::6 953593 # Per bank write bursts +system.physmem.perBankRdBursts::7 950807 # Per bank write bursts +system.physmem.perBankRdBursts::8 956024 # Per bank write bursts +system.physmem.perBankRdBursts::9 956507 # Per bank write bursts +system.physmem.perBankRdBursts::10 953309 # Per bank write bursts +system.physmem.perBankRdBursts::11 950948 # Per bank write bursts +system.physmem.perBankRdBursts::12 956403 # Per bank write bursts +system.physmem.perBankRdBursts::13 956390 # Per bank write bursts +system.physmem.perBankRdBursts::14 954120 # Per bank write bursts +system.physmem.perBankRdBursts::15 951130 # Per bank write bursts +system.physmem.perBankWrBursts::0 7301 # Per bank write bursts +system.physmem.perBankWrBursts::1 7301 # Per bank write bursts +system.physmem.perBankWrBursts::2 6635 # Per bank write bursts +system.physmem.perBankWrBursts::3 6826 # Per bank write bursts +system.physmem.perBankWrBursts::4 7245 # Per bank write bursts +system.physmem.perBankWrBursts::5 6961 # Per bank write bursts +system.physmem.perBankWrBursts::6 7187 # Per bank write bursts +system.physmem.perBankWrBursts::7 6869 # Per bank write bursts +system.physmem.perBankWrBursts::8 6823 # Per bank write bursts +system.physmem.perBankWrBursts::9 7301 # Per bank write bursts +system.physmem.perBankWrBursts::10 6956 # Per bank write bursts +system.physmem.perBankWrBursts::11 6738 # Per bank write bursts +system.physmem.perBankWrBursts::12 7232 # Per bank write bursts +system.physmem.perBankWrBursts::13 7102 # Per bank write bursts +system.physmem.perBankWrBursts::14 7378 # Per bank write bursts +system.physmem.perBankWrBursts::15 7255 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2605244301000 # Total gap between requests +system.physmem.totGap 2621645657000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 109 # Read request sizes (log2) -system.physmem.readPktSize::3 15138816 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::2 59 # Read request sizes (log2) +system.physmem.readPktSize::3 15138841 # Read request sizes (log2) +system.physmem.readPktSize::4 3426 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 162749 # Read request sizes (log2) +system.physmem.readPktSize::6 161149 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66421 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1076672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1007796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 966781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1073648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 970528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1031139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2669789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2577083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3357471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 128637 # What read queue length does an incoming req see +system.physmem.writePktSize::6 65464 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1118217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 965108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 965171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1074431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 973448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1034951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2682221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2590422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3372339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 127125 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 110466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 102015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 101918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 97549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 19015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -176,28 +176,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see @@ -225,383 +225,385 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1012037 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 970.206299 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 901.657757 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 207.022901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24841 2.45% 2.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20798 2.06% 4.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8822 0.87% 5.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2548 0.25% 5.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2540 0.25% 5.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1879 0.19% 6.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8798 0.87% 6.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1115 0.11% 7.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 940696 92.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1012037 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2278.257181 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 111148.889106 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6680 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.064632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.010880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.396865 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3849 57.59% 57.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 42 0.63% 58.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1749 26.17% 84.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 863 12.91% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 73 1.09% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 28 0.42% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 31 0.46% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 31 0.46% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 14 0.21% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads -system.physmem.totQLat 394529621500 # Total ticks spent queuing -system.physmem.totMemAccLat 680052521500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76139440000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25908.36 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1014826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 970.256324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 901.955292 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 206.811149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24748 2.44% 2.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20792 2.05% 4.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9109 0.90% 5.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2441 0.24% 5.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2631 0.26% 5.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1759 0.17% 6.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9074 0.89% 6.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1088 0.11% 7.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943184 92.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1014826 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6619 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2307.281009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 96810.313262 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6612 99.89% 99.89% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 2 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6619 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6619 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.088684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.037372 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.359683 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3686 55.69% 55.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 52 0.79% 56.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1827 27.60% 84.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 927 14.01% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 37 0.56% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 27 0.41% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 28 0.42% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.32% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 11 0.17% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6619 # Writes before turning the bus around for reads +system.physmem.totQLat 395207982750 # Total ticks spent queuing +system.physmem.totMemAccLat 681556314000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76359555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25878.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44658.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.09 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44628.10 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 372.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.94 # Data bus utilization in percentage -system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.93 # Data bus utilization in percentage +system.physmem.busUtilRead 2.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing -system.physmem.readRowHits 14233868 # Number of row buffer hits during reads -system.physmem.writeRowHits 96043 # Number of row buffer hits during writes +system.physmem.avgRdQLen 5.85 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.60 # Average write queue length when enqueuing +system.physmem.readRowHits 14274861 # Number of row buffer hits during reads +system.physmem.writeRowHits 95334 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.18 # Row buffer hit rate for writes -system.physmem.avgGap 161561.74 # Average gap between requests +system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes +system.physmem.avgGap 162570.35 # Average gap between requests system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2261037204000 # Time in different power states -system.physmem.memoryStateTime::REF 86994700000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2271344460000 # Time in different power states +system.physmem.memoryStateTime::REF 87542520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 257208674750 # Time in different power states +system.physmem.memoryStateTime::ACT 262759227500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54210578 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16352619 # Transaction distribution -system.membus.trans_dist::ReadResp 16352619 # Transaction distribution -system.membus.trans_dist::WriteReq 769183 # Transaction distribution -system.membus.trans_dist::WriteResp 769183 # Transaction distribution -system.membus.trans_dist::Writeback 66421 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35773 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 18321 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14174 # Transaction distribution -system.membus.trans_dist::ReadExReq 137666 # Transaction distribution -system.membus.trans_dist::ReadExResp 137285 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384364 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13834 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 192 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 192 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 12 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 55 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 73 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 55 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 73 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 55 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 73 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 53827614 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16353736 # Transaction distribution +system.membus.trans_dist::ReadResp 16353736 # Transaction distribution +system.membus.trans_dist::WriteReq 768463 # Transaction distribution +system.membus.trans_dist::WriteResp 768463 # Transaction distribution +system.membus.trans_dist::Writeback 65464 # Transaction distribution +system.membus.trans_dist::UpgradeReq 28363 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16887 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12033 # Transaction distribution +system.membus.trans_dist::ReadExReq 137713 # Transaction distribution +system.membus.trans_dist::ReadExResp 137251 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10950 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975354 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4375612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967095 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4364477 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34653244 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27668 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34642109 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392641 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 192 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 21900 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17696452 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20121337 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4116 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17587620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20006477 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141231865 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141231865 # Total data (bytes) +system.membus.tot_pkt_size::total 141117005 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141117005 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487709500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1559281500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 14500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11701000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9763000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1799000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1786500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17608394498 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17605374000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4825319244 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4830238688 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37398632151 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37428300697 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 72458 # number of replacements -system.l2c.tags.tagsinuse 53011.924457 # Cycle average of tags in use -system.l2c.tags.total_refs 1875821 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137631 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.629349 # Average number of references to valid blocks. +system.l2c.tags.replacements 71035 # number of replacements +system.l2c.tags.tagsinuse 52844.560777 # Cycle average of tags in use +system.l2c.tags.total_refs 1830685 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 136207 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.440462 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37713.505334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.216539 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4181.052971 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2965.825646 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.076579 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4028.442908 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4106.804235 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.575462 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000080 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37821.803984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.739512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000522 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5415.027395 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6377.582658 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.953654 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2390.174334 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 833.278718 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.577115 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000088 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063798 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045255 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061469 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.062665 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808898 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.082627 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.097314 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.036471 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012715 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.806344 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3104 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8671 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53043 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3098 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8323 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53527 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18870937 # Number of tag accesses -system.l2c.tags.data_accesses 18870937 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 23602 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 393472 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166101 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 33133 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5623 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 609766 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 201485 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1437806 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 583097 # number of Writeback hits -system.l2c.Writeback_hits::total 583097 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1009 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 849 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1858 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 170 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 380 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48094 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59208 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107302 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 23602 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4624 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 393472 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214195 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 33133 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5623 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 609766 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260693 # number of demand (read+write) hits -system.l2c.demand_hits::total 1545108 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 23602 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4624 # number of overall hits -system.l2c.overall_hits::cpu0.inst 393472 # number of overall hits -system.l2c.overall_hits::cpu0.data 214195 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 33133 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5623 # number of overall hits -system.l2c.overall_hits::cpu1.inst 609766 # number of overall hits -system.l2c.overall_hits::cpu1.data 260693 # number of overall hits -system.l2c.overall_hits::total 1545108 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6027 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 13 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6652 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6349 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25371 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5736 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4455 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10191 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 772 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 591 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1363 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63106 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76799 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139905 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6027 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69421 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6652 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83148 # number of demand (read+write) misses -system.l2c.demand_misses::total 165276 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6027 # number of overall misses -system.l2c.overall_misses::cpu0.data 69421 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 13 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6652 # number of overall misses -system.l2c.overall_misses::cpu1.data 83148 # number of overall misses -system.l2c.overall_misses::total 165276 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1286000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 293000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 437446500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 469525749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1020750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 484881000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 483780000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1878232999 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 9370079 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12322478 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21692557 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 533977 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3118865 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3652842 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4338208852 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5958244026 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10296452878 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1286000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 293000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 437446500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4807734601 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1020750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 484881000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6442024026 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 12174685877 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1286000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 293000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 437446500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4807734601 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1020750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 484881000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6442024026 # number of overall miss cycles -system.l2c.overall_miss_latency::total 12174685877 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 23616 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4625 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 399499 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 172416 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 33146 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5623 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 616418 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 207834 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1463177 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 583097 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 583097 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6745 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5304 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 12049 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 982 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 761 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1743 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111200 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 136007 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 23616 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4625 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 399499 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 283616 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 33146 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5623 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 616418 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 343841 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1710384 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 23616 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4625 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 399499 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 283616 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 33146 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5623 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 616418 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 343841 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1710384 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000593 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000216 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015086 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036627 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000392 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010791 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030548 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017340 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.850408 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.839932 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.845796 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.786151 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776610 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.781985 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.567500 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.564669 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.565943 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000593 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000216 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015086 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244771 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000392 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010791 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.241821 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.096631 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000593 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000216 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015086 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244771 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000392 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010791 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.241821 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.096631 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 91857.142857 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 293000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72581.134893 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 74350.870784 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78519.230769 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72892.513530 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76197.826429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 74030.704308 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1633.556311 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2765.988328 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2128.599450 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 691.680052 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5277.267343 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2680.001467 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68744.792128 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77582.312608 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73596.032150 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91857.142857 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 293000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 72581.134893 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 69254.758661 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78519.230769 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72892.513530 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 77476.596262 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 73662.757309 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91857.142857 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 293000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 72581.134893 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 69254.758661 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78519.230769 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72892.513530 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 77476.596262 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 73662.757309 # average overall miss latency +system.l2c.tags.tag_accesses 18484845 # Number of tag accesses +system.l2c.tags.data_accesses 18484845 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 20873 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 5362 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 546777 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 243323 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 15709 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4324 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 434561 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 119239 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1390168 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 583269 # number of Writeback hits +system.l2c.Writeback_hits::total 583269 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 378 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1712 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 271 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 117 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 388 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 65538 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 44550 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 20873 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5362 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 546777 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 308861 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 15709 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4324 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 434561 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 163789 # number of demand (read+write) hits +system.l2c.demand_hits::total 1500256 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 20873 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5362 # number of overall hits +system.l2c.overall_hits::cpu0.inst 546777 # number of overall hits +system.l2c.overall_hits::cpu0.data 308861 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 15709 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4324 # number of overall hits +system.l2c.overall_hits::cpu1.inst 434561 # number of overall hits +system.l2c.overall_hits::cpu1.data 163789 # number of overall hits +system.l2c.overall_hits::total 1500256 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7230 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9897 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4714 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2106 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23958 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4509 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3863 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8372 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 516 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 628 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1144 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 94130 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 45638 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139768 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7230 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 104027 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4714 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 47744 # number of demand (read+write) misses +system.l2c.demand_misses::total 163726 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7230 # number of overall misses +system.l2c.overall_misses::cpu0.data 104027 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4714 # number of overall misses +system.l2c.overall_misses::cpu1.data 47744 # number of overall misses +system.l2c.overall_misses::total 163726 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 551500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 522312750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 733828247 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 83500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 334292999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 165107999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1756326995 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 11295015 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12799954 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 24094969 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1793923 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1118952 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2912875 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6378706625 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3294603599 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9673310224 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 551500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 522312750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 7112534872 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 83500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 334292999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3459711598 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11429637219 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 551500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 522312750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 7112534872 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 83500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 334292999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3459711598 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11429637219 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 20881 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 5364 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 554007 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 253220 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 15710 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 4324 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 439275 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 121345 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1414126 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 583269 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 583269 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5843 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4241 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10084 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 787 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 745 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1532 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 159668 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 90188 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249856 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 20881 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 5364 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 554007 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 412888 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 15710 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 4324 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 439275 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 211533 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1663982 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 20881 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 5364 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 554007 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 412888 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 15710 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 4324 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 439275 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 211533 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1663982 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000383 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000373 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013050 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.039085 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000064 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010731 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017355 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016942 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.771693 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.910870 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.830226 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.655654 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.842953 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.746736 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.589536 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.506032 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.559394 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000383 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000373 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013050 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.251950 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000064 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010731 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.225705 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098394 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000383 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000373 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013050 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.251950 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000064 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010731 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.225705 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098394 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 68937.500000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72242.427386 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 74146.534000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70914.934026 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78398.859924 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 73308.581476 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2504.993347 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3313.475019 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2878.042164 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3476.594961 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1781.770701 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2546.219406 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67764.863752 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72189.920658 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 69209.763494 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 68937.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 72242.427386 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 68372.007959 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 70914.934026 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 72463.798551 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 69809.542889 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 68937.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 72242.427386 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 68372.007959 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 70914.934026 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 72463.798551 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 69809.542889 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -610,168 +612,171 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66421 # number of writebacks -system.l2c.writebacks::total 66421 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 26 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 26 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 26 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 77 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6022 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6277 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 13 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6644 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6323 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25294 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5736 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4455 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 10191 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 772 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 591 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1363 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63106 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76799 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139905 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6022 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69383 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6644 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83122 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165199 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6022 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69383 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6644 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83122 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165199 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1113000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 281000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 361272500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 388267999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 860750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 400921250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 403426250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1556142749 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57546650 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44906373 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 102453023 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7730770 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5917089 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 13647859 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3559268136 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5010952970 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8570221106 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1113000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 281000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 361272500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3947536135 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 860750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 400921250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5414379220 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 10126363855 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1113000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 281000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 361272500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3947536135 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 860750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 400921250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5414379220 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 10126363855 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 7054750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12335372985 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3127500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154881187230 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167226742465 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1073385998 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16534155943 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17607541941 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7054750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13408758983 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3127500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171415343173 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184834284406 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000593 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036406 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010778 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030423 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017287 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.850408 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.839932 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.845796 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.786151 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776610 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.781985 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567500 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564669 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.565943 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000593 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244637 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010778 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.241745 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.096586 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000593 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244637 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010778 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.241745 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.096586 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61855.663374 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63802.981180 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61522.208785 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10032.540098 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10079.993939 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10053.284565 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.950777 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.994924 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.102715 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56401.421988 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65247.633042 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61257.432586 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56894.860917 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65137.739949 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61297.973081 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56894.860917 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65137.739949 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61297.973081 # average overall mshr miss latency +system.l2c.writebacks::writebacks 65464 # number of writebacks +system.l2c.writebacks::total 65464 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 28 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 12 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 28 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 28 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 60 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7221 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 9869 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4704 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 2094 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23898 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 4509 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3863 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8372 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 516 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 628 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1144 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 94130 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 45638 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139768 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7221 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 103999 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4704 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 47732 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 163666 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 7221 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 103999 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4704 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 47732 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 163666 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 395000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 431252250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 608078747 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 71000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 274798249 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 138281999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1453002245 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 45149974 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38756824 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 83906798 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5160516 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 6295125 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 11455641 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5201483861 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2728717885 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7930201746 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 395000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 431252250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5809562608 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 71000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 274798249 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2866999884 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9383203991 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 395000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 431252250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5809562608 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 71000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 274798249 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2866999884 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9383203991 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 176335500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12626197496 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3342000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154644756250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167450631246 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16805961075 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 475202500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17281163575 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 176335500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 29432158571 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3342000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155119958750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184731794821 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000335 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000373 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013034 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038974 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000064 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010709 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017257 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016899 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.771693 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.910870 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.830226 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.655654 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.842953 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.746736 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.589536 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.506032 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559394 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000335 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000373 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013034 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.251882 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000064 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010709 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.225648 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098358 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000335 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013034 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.251882 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000064 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010709 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.225648 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098358 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61615.031614 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58417.995111 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66037.248806 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60800.160892 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.300954 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.830443 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10022.312231 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10024.084395 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.672203 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55258.513343 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59790.479096 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56738.321690 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55861.716055 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58417.995111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60064.524512 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57331.418810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55861.716055 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58417.995111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60064.524512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57331.418810 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -792,64 +797,66 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58770672 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2743232 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2743231 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 769183 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 769183 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 583097 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35011 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18701 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53712 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 259154 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 259154 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 799809 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073837 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14034 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 57985 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1233533 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820063 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15283 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75701 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8090245 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25576064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34728353 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18500 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39453888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48201112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 22492 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148227457 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148227457 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4884572 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4922251450 # Layer occupancy (ticks) +system.toL2Bus.throughput 57560286 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2682607 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2682607 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 768463 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 768463 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 583269 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 27558 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17275 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 44833 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 261997 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 261997 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1115277 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2956767 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14518 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50368 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 879187 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2909426 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 12099 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 38611 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7976253 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 35510400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53724619 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83524 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 28114656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 29015778 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 17296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 62840 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146550569 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146550569 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4352184 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4888594820 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1802620121 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2503079453 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1515652575 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2482730980 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9436941 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9171959 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34537141 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 29595779 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2778792830 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 1980581418 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 3257203486 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 2244583247 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 9681453 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.occupancy 7797450 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 42845398 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 22968355 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47405592 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322915 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322915 # Transaction distribution +system.iobus.throughput 47108999 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322906 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322906 # Transaction distribution system.iobus.trans_dist::WriteReq 8083 # Transaction distribution system.iobus.trans_dist::WriteResp 8083 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8836 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8814 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1034 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) @@ -869,14 +876,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384346 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32661996 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32661978 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17672 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17628 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) @@ -896,18 +903,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2392641 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123503205 # Total data (bytes) +system.iobus.tot_pkt_size::total 123503169 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123503169 # Total data (bytes) system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4424000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4413000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 523000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -949,19 +956,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376281000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2376263000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38152801849 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38168032303 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6193187 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4738042 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296192 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3876930 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2986045 # Number of BTB hits +system.cpu0.branchPred.lookups 8682194 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6490987 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 415813 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 5217710 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4131218 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.020864 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 687525 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28310 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 79.176842 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 908190 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 19748 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -985,25 +992,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8977307 # DTB read hits -system.cpu0.dtb.read_misses 29619 # DTB read misses -system.cpu0.dtb.write_hits 5215302 # DTB write hits -system.cpu0.dtb.write_misses 5680 # DTB write misses +system.cpu0.dtb.read_hits 10917771 # DTB read hits +system.cpu0.dtb.read_misses 23643 # DTB read misses +system.cpu0.dtb.write_hits 7767808 # DTB write hits +system.cpu0.dtb.write_misses 8146 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1732 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 993 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1721 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 163 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 620 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9006926 # DTB read accesses -system.cpu0.dtb.write_accesses 5220982 # DTB write accesses +system.cpu0.dtb.perms_faults 598 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 10941414 # DTB read accesses +system.cpu0.dtb.write_accesses 7775954 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14192609 # DTB hits -system.cpu0.dtb.misses 35299 # DTB misses -system.cpu0.dtb.accesses 14227908 # DTB accesses +system.cpu0.dtb.hits 18685579 # DTB hits +system.cpu0.dtb.misses 31789 # DTB misses +system.cpu0.dtb.accesses 18717368 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1025,8 +1032,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 4299863 # ITB inst hits -system.cpu0.itb.inst_misses 5195 # ITB inst misses +system.cpu0.itb.inst_hits 16449037 # ITB inst hits +system.cpu0.itb.inst_misses 5743 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1035,580 +1042,593 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1219 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1206 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1331 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2114 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4305058 # ITB inst accesses -system.cpu0.itb.hits 4299863 # DTB hits -system.cpu0.itb.misses 5195 # DTB misses -system.cpu0.itb.accesses 4305058 # DTB accesses -system.cpu0.numCycles 69478980 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 16454780 # ITB inst accesses +system.cpu0.itb.hits 16449037 # DTB hits +system.cpu0.itb.misses 5743 # DTB misses +system.cpu0.itb.accesses 16454780 # DTB accesses +system.cpu0.numCycles 110984158 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11944453 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32774113 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6193187 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3673570 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7678957 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1502530 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 63317 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19508655 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 6049 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47760 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1413705 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 248 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4298413 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 159366 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2185 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41753011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.013655 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.394447 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 29010417 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 51007104 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 8682194 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5039408 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 76702951 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1090474 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 80643 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 23949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 71996 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1961272 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 16450117 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 242573 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2510 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 108396478 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.561251 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.057421 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34081524 81.63% 81.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 576095 1.38% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 828597 1.98% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 688423 1.65% 86.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 783359 1.88% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 570610 1.37% 89.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 698382 1.67% 91.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 360373 0.86% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3165648 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 80471532 74.24% 74.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 9354408 8.63% 82.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 4228353 3.90% 86.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 14342185 13.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41753011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.089138 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471713 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12274082 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20961054 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7066192 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 425731 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1025952 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 955706 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 65065 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40945366 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213036 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1025952 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12760478 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 3004976 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13648632 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 7041602 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4271371 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39802599 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1199 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1526731 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1438820 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1837389 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 522 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40279465 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 182145305 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 165318292 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4116 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31479900 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8799564 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 460456 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 417031 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4293085 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7837564 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5796369 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1159621 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1213862 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37649045 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 906994 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37770468 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 93887 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6620221 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14342287 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 258409 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41753011 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904617 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.539726 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 108396478 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.078229 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.459589 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 24273364 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 59696324 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 21865637 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 2148424 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 412729 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1100967 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 134603 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56048449 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 1161275 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 412729 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 26181144 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 23163659 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 11818847 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 22001270 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 24818829 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54863842 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 371818 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 4330145 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2622839 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 9842391 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 13156385 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 58083982 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 254404471 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 69151408 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3820 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 54276662 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 3807314 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 540800 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 442723 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4591136 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9492850 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 8297955 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 506397 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 589876 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53569882 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 859573 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 55433156 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 105167 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 2762956 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 5503873 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 84823 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 108396478 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.511393 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.864824 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26686839 63.92% 63.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5690671 13.63% 77.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3035101 7.27% 84.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2408430 5.77% 90.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2094356 5.02% 95.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 953036 2.28% 97.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 611124 1.46% 99.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 212675 0.51% 99.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 60779 0.15% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74367725 68.61% 68.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 17769290 16.39% 85.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 11558620 10.66% 95.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 4256755 3.93% 99.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 444079 0.41% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41753011 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 108396478 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29050 2.58% 2.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 460 0.04% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 862862 76.64% 79.26% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 233562 20.74% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3788078 33.87% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 172 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 3595287 32.14% 66.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3801407 33.99% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14549 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22728130 60.17% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48220 0.13% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9442602 25.00% 85.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5536256 14.66% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14948 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35826739 64.63% 64.66% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 64782 0.12% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 722 0.00% 64.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 64.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 11302035 20.39% 85.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 8223930 14.84% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37770468 # Type of FU issued -system.cpu0.iq.rate 0.543624 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1125934 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.029810 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 118540397 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45184408 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34905571 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8382 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38877516 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4337 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 330330 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 55433156 # Type of FU issued +system.cpu0.iq.rate 0.499469 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11184944 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.201774 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 230540772 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57191232 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 52885161 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12129 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66595213 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7939 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 146965 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1458060 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2363 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13414 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 565962 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 634189 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 3442 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 242149 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2141820 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5981 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1082260 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 1003693 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1025952 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2385802 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 275075 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38676599 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 76106 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7837564 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5796369 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 579111 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 58653 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 199282 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13414 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149919 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118426 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 268345 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37387044 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9294285 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 383424 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 412729 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7302695 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6441595 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 54523303 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9492850 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 8297955 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 524870 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 12318 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6420937 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 3442 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 134210 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 165432 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 299642 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 55026621 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 11133456 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 374843 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 120560 # number of nop insts executed -system.cpu0.iew.exec_refs 14782259 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4971290 # Number of branches executed -system.cpu0.iew.exec_stores 5487974 # Number of stores executed -system.cpu0.iew.exec_rate 0.538106 # Inst execution rate -system.cpu0.iew.wb_sent 37190474 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34909443 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18996365 # num instructions producing a value -system.cpu0.iew.wb_consumers 36943291 # num instructions consuming a value +system.cpu0.iew.exec_nop 93848 # number of nop insts executed +system.cpu0.iew.exec_refs 19301977 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7332190 # Number of branches executed +system.cpu0.iew.exec_stores 8168521 # Number of stores executed +system.cpu0.iew.exec_rate 0.495806 # Inst execution rate +system.cpu0.iew.wb_sent 54039254 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 52888999 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25110485 # num instructions producing a value +system.cpu0.iew.wb_consumers 37735585 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.502446 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.514203 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.476545 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.665433 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6443412 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 648585 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232277 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40727059 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.780301 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.748318 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 2480238 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 774750 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 283305 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 107840192 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.477624 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.224539 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28935599 71.05% 71.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5796697 14.23% 85.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1842943 4.53% 89.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1067095 2.62% 92.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 737891 1.81% 94.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 511993 1.26% 95.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 448684 1.10% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 197374 0.48% 97.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1188783 2.92% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 82912194 76.88% 76.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 14339479 13.30% 90.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 5152045 4.78% 94.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1572745 1.46% 96.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1370622 1.27% 97.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 690625 0.64% 98.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 401555 0.37% 98.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 407085 0.38% 99.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 993842 0.92% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40727059 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24067678 # Number of instructions committed -system.cpu0.commit.committedOps 31779383 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 107840192 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 43173906 # Number of instructions committed +system.cpu0.commit.committedOps 51507078 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11609911 # Number of memory references committed -system.cpu0.commit.loads 6379504 # Number of loads committed -system.cpu0.commit.membars 231786 # Number of memory barriers committed -system.cpu0.commit.branches 4350837 # Number of branches committed +system.cpu0.commit.refs 16914467 # Number of memory references committed +system.cpu0.commit.loads 8858661 # Number of loads committed +system.cpu0.commit.membars 263890 # Number of memory barriers committed +system.cpu0.commit.branches 7043091 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28125415 # Number of committed integer instructions. -system.cpu0.commit.function_calls 498912 # Number of function calls committed. +system.cpu0.commit.int_insts 45505753 # Number of committed integer instructions. +system.cpu0.commit.function_calls 666034 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 20129006 63.34% 63.34% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 39786 0.13% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 6379504 20.07% 83.54% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5230407 16.46% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 34530023 67.04% 67.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 61866 0.12% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 722 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8858661 17.20% 84.36% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 8055806 15.64% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 31779383 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1188783 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 51507078 # Class of committed instruction +system.cpu0.commit.bw_lim_events 993842 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 76892389 # The number of ROB reads -system.cpu0.rob.rob_writes 77473478 # The number of ROB writes -system.cpu0.timesIdled 368167 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27725969 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5140969387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23986936 # Number of Instructions Simulated -system.cpu0.committedOps 31698641 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.896534 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.896534 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.345240 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.345240 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174527841 # number of integer regfile reads -system.cpu0.int_regfile_writes 34672219 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3319 # number of floating regfile reads -system.cpu0.fp_regfile_writes 920 # number of floating regfile writes -system.cpu0.misc_regfile_reads 78617689 # number of misc regfile reads -system.cpu0.misc_regfile_writes 500675 # number of misc regfile writes -system.cpu0.icache.tags.replacements 399525 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.581560 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3866760 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 400037 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.666006 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6951542250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.581560 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999183 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999183 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 159811836 # The number of ROB reads +system.cpu0.rob.rob_writes 108530018 # The number of ROB writes +system.cpu0.timesIdled 338876 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2587680 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5132257518 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 43093164 # Number of Instructions Simulated +system.cpu0.committedOps 51426336 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.575447 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.575447 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.388282 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.388282 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67127966 # number of integer regfile reads +system.cpu0.int_regfile_writes 33211893 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads +system.cpu0.fp_regfile_writes 840 # number of floating regfile writes +system.cpu0.cc_regfile_reads 191848471 # number of cc regfile reads +system.cpu0.cc_regfile_writes 22040987 # number of cc regfile writes +system.cpu0.misc_regfile_reads 169210728 # number of misc regfile reads +system.cpu0.misc_regfile_writes 593502 # number of misc regfile writes +system.cpu0.icache.tags.replacements 554010 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.387606 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 15866984 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 554522 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.613804 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 18806389250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.387606 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998804 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998804 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 4698333 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 4698333 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 3866760 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3866760 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3866760 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3866760 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3866760 # number of overall hits -system.cpu0.icache.overall_hits::total 3866760 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 431519 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 431519 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 431519 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 431519 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 431519 # number of overall misses -system.cpu0.icache.overall_misses::total 431519 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5963742706 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5963742706 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5963742706 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5963742706 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5963742706 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5963742706 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4298279 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4298279 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4298279 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4298279 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4298279 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4298279 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100393 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100393 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100393 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100393 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100393 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100393 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13820.347901 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13820.347901 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13820.347901 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13820.347901 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13820.347901 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13820.347901 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4778 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 17001271 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 17001271 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 15866984 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 15866984 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 15866984 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 15866984 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 15866984 # number of overall hits +system.cpu0.icache.overall_hits::total 15866984 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 579761 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 579761 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 579761 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 579761 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 579761 # number of overall misses +system.cpu0.icache.overall_misses::total 579761 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8029558142 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8029558142 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 8029558142 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8029558142 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 8029558142 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8029558142 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 16446745 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 16446745 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 16446745 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 16446745 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 16446745 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 16446745 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.035251 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.035251 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.035251 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.035251 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.035251 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.035251 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13849.772824 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13849.772824 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13849.772824 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13849.772824 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13849.772824 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13849.772824 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 739 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 55 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.493827 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.436364 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31464 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31464 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31464 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31464 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31464 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31464 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400055 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 400055 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 400055 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 400055 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 400055 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 400055 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4860147872 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4860147872 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4860147872 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4860147872 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4860147872 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4860147872 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9713500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9713500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9713500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 9713500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093073 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093073 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093073 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093073 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093073 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093073 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12148.699234 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12148.699234 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12148.699234 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12148.699234 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12148.699234 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12148.699234 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 25235 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 25235 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 25235 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 25235 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 25235 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 25235 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 554526 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 554526 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 554526 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 554526 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 554526 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 554526 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6629844046 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6629844046 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6629844046 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6629844046 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6629844046 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6629844046 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 226658500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 226658500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 226658500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 226658500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033716 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033716 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033716 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11955.875912 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11955.875912 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11955.875912 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 275167 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.361699 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9408418 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 275679 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.128164 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 42907250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.361699 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938206 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938206 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 409126 # number of replacements +system.cpu0.dcache.tags.tagsinuse 483.194796 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12942599 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 409638 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.595211 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 271704250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.194796 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.943740 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.943740 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 45804428 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 45804428 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5867272 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5867272 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3220606 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3220606 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139465 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139465 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137168 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137168 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9087878 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9087878 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9087878 # number of overall hits -system.cpu0.dcache.overall_hits::total 9087878 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 403110 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 403110 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1588797 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1588797 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8920 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8920 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7758 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7758 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1991907 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1991907 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1991907 # number of overall misses -system.cpu0.dcache.overall_misses::total 1991907 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5653636758 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5653636758 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74855868606 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 74855868606 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91362982 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 91362982 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50049767 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 50049767 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 80509505364 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 80509505364 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 80509505364 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 80509505364 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6270382 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6270382 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4809403 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4809403 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148385 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 148385 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144926 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144926 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11079785 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11079785 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11079785 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11079785 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064288 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.064288 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330352 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.330352 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060114 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060114 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053531 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053531 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179778 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.179778 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179778 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.179778 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14025.047153 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14025.047153 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47114.809888 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 47114.809888 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10242.486771 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10242.486771 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6451.374968 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6451.374968 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 40418.305355 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 40418.305355 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 40418.305355 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 40418.305355 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9294 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 6492 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 635 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 113 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.636220 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 57.451327 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 63030887 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63030887 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 8037454 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 8037454 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4509267 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4509267 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 46089 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 46089 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156971 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156971 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159079 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 159079 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12546721 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12546721 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12592810 # number of overall hits +system.cpu0.dcache.overall_hits::total 12592810 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 406720 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 406720 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2221250 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2221250 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 92142 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 92142 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10979 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 10979 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7659 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7659 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2627970 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2627970 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2720112 # number of overall misses +system.cpu0.dcache.overall_misses::total 2720112 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5668958645 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5668958645 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 107130503686 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 107130503686 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114563996 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 114563996 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44413016 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44413016 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 112799462331 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 112799462331 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 112799462331 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 112799462331 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8444174 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8444174 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6730517 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6730517 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 138231 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 138231 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167950 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 167950 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166738 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166738 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 15174691 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15174691 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 15312922 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15312922 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048166 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.048166 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330027 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330027 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.666580 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.666580 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065371 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065371 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.045934 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.045934 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173181 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.173181 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177635 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.177635 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.234277 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.234277 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48229.827208 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 48229.827208 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10434.829766 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10434.829766 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5798.800888 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5798.800888 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 42922.659821 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 42922.659821 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41468.683029 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41468.683029 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 14275 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1041 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.712776 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255545 # number of writebacks -system.cpu0.dcache.writebacks::total 255545 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 213826 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 213826 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457949 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1457949 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 469 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 469 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1671775 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1671775 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1671775 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1671775 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189284 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189284 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130848 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130848 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8451 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8451 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7758 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7758 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320132 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320132 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320132 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320132 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2416725188 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2416725188 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5154000431 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5154000431 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69605516 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69605516 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34529233 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34529233 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7570725619 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7570725619 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7570725619 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7570725619 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434660545 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434660545 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206058380 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206058380 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640718925 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640718925 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030187 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030187 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056953 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056953 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053531 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053531 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028893 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028893 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12767.720399 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12767.720399 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39389.218261 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39389.218261 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8236.364454 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8236.364454 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4450.790539 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4450.790539 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 375988 # number of writebacks +system.cpu0.dcache.writebacks::total 375988 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 193747 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 193747 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2045363 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2045363 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1054 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1054 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2239110 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2239110 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2239110 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2239110 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212973 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 212973 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175887 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 175887 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 54623 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 54623 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7659 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7659 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 388860 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 388860 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 443483 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 443483 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2487825853 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2487825853 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7369362883 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7369362883 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1035896777 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1035896777 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82981003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 82981003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29093984 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29093984 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9857188736 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9857188736 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10893085513 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10893085513 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13737621002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13737621002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 26275689041 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26275689041 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 40013310043 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 40013310043 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025221 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025221 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026133 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026133 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.395157 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.395157 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059095 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059095 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.045934 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.045934 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025626 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025626 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028961 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028961 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11681.414325 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11681.414325 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41898.280618 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41898.280618 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18964.479743 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.479743 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8360.806348 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8360.806348 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3798.666144 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3798.666144 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25348.939814 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25348.939814 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24562.577400 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24562.577400 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1616,15 +1636,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9402679 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7728805 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 418099 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6037829 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5108046 # Number of BTB hits +system.cpu1.branchPred.lookups 5001209 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3530067 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 291977 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3184313 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2141032 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.600707 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 802186 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 44176 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 67.236858 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 582225 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 13211 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1648,25 +1668,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42878527 # DTB read hits -system.cpu1.dtb.read_misses 38253 # DTB read misses -system.cpu1.dtb.write_hits 6985734 # DTB write hits -system.cpu1.dtb.write_misses 10793 # DTB write misses +system.cpu1.dtb.read_hits 21293354 # DTB read hits +system.cpu1.dtb.read_misses 17527 # DTB read misses +system.cpu1.dtb.write_hits 4063342 # DTB write hits +system.cpu1.dtb.write_misses 3266 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1922 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2963 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1908 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 789 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 687 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42916780 # DTB read accesses -system.cpu1.dtb.write_accesses 6996527 # DTB write accesses +system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 21310881 # DTB read accesses +system.cpu1.dtb.write_accesses 4066608 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49864261 # DTB hits -system.cpu1.dtb.misses 49046 # DTB misses -system.cpu1.dtb.accesses 49913307 # DTB accesses +system.cpu1.dtb.hits 25356696 # DTB hits +system.cpu1.dtb.misses 20793 # DTB misses +system.cpu1.dtb.accesses 25377489 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1688,8 +1708,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7755980 # ITB inst hits -system.cpu1.itb.inst_misses 5491 # ITB inst misses +system.cpu1.itb.inst_hits 8626509 # ITB inst hits +system.cpu1.itb.inst_misses 4363 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1698,579 +1718,595 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1362 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1319 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1507 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2055 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7761471 # ITB inst accesses -system.cpu1.itb.hits 7755980 # DTB hits -system.cpu1.itb.misses 5491 # DTB misses -system.cpu1.itb.accesses 7761471 # DTB accesses -system.cpu1.numCycles 413132210 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8630872 # ITB inst accesses +system.cpu1.itb.hits 8626509 # DTB hits +system.cpu1.itb.misses 4363 # DTB misses +system.cpu1.itb.accesses 8630872 # DTB accesses +system.cpu1.numCycles 396849081 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19420388 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 61788688 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9402679 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5910232 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13466568 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3411318 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 67616 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77041165 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5941 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42813 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1523639 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7754163 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 555305 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2851 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 113918823 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.663934 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.994464 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18444788 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 25760845 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 5001209 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2723257 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 375027882 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 802688 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 60706 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 28139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 75697 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1303305 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.CacheLines 8624270 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 181619 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1774 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 395341861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.079415 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 0.442124 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100459727 88.19% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 820479 0.72% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 969052 0.85% 89.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1718827 1.51% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1427854 1.25% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 590556 0.52% 93.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1988498 1.75% 94.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 426289 0.37% 95.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5517541 4.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 380851246 96.33% 96.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4867429 1.23% 97.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2340779 0.59% 98.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 7282407 1.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 113918823 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022759 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.149562 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20573629 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78271180 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12141436 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 681674 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2250904 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1146333 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 101070 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 71648546 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 337709 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2250904 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21753755 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 11785871 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 44839476 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11758144 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 21530673 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 67615561 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 613 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 15671923 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18336953 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1545811 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 1295 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 71310682 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 315205355 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 288681323 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6622 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50413608 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20897074 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 766814 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 706637 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7207016 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12951593 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8155935 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1106689 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1533453 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 62295252 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1184366 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 88905891 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 106644 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13983630 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 37714490 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 285025 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 113918823 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780432 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.530885 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 395341861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.012602 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.064913 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15111141 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 368322319 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9619404 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1988623 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 300374 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 680085 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 102949 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 27336312 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 828595 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 300374 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16508550 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 196017158 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 17889321 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 9851688 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 154774770 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 26427025 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 243114 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 56891125 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 39780893 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 150628157 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 2138867 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 27113530 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 124075273 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 31437770 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6241 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 24483458 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2630072 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 642693 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 559165 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4862604 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 5657845 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 4330093 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 343073 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 498131 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 25260320 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 861912 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 41442639 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 78274 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1902061 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 3789747 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 92749 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 395341861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.104827 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.383209 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83813472 73.57% 73.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8528665 7.49% 81.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3988574 3.50% 84.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3433815 3.01% 87.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10704573 9.40% 96.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1891022 1.66% 98.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1169449 1.03% 99.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 305487 0.27% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 83766 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 362283147 91.64% 91.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 26570133 6.72% 98.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4792582 1.21% 99.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1496663 0.38% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 199327 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 113918823 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 395341861 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 34951 0.44% 0.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 989 0.01% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7593663 95.44% 95.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 326577 4.10% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1195141 5.96% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 685 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 16909984 84.32% 90.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1947822 9.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 14267 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37698483 42.40% 42.42% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61348 0.07% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43772925 49.24% 91.72% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7357130 8.28% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13868 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 15563362 37.55% 37.59% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 33954 0.08% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1648 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 21553207 52.01% 89.68% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 4276600 10.32% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 88905891 # Type of FU issued -system.cpu1.iq.rate 0.215200 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7956180 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089490 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 299826864 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 77472999 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54370047 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15424 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8128 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6867 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96839621 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8183 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 371805 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 41442639 # Type of FU issued +system.cpu1.iq.rate 0.104429 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 20053632 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.483889 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 498337881 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 28019357 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 25018416 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 21164 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7936 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6759 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 61468547 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 13856 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 72058 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2971595 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3826 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 18443 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1153168 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 455146 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 306 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3014 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 163146 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31846626 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 675699 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 15996057 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1487 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2250904 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 9489416 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1235015 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63585663 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 104803 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12951593 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8155935 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 886916 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 232294 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 885959 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 18443 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 206591 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 158855 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 365446 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87166570 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43262018 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1739321 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 300374 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 87167513 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 92299631 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 26204459 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 5657845 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 4330093 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 630570 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 9334 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 92232105 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3014 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 83298 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 118271 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 201569 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 41178523 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 21441390 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 243431 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 106045 # number of nop insts executed -system.cpu1.iew.exec_refs 50553896 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7398817 # Number of branches executed -system.cpu1.iew.exec_stores 7291878 # Number of stores executed -system.cpu1.iew.exec_rate 0.210990 # Inst execution rate -system.cpu1.iew.wb_sent 86399299 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54376914 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30829889 # num instructions producing a value -system.cpu1.iew.wb_consumers 55266228 # num instructions consuming a value +system.cpu1.iew.exec_nop 82227 # number of nop insts executed +system.cpu1.iew.exec_refs 25682989 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3899404 # Number of branches executed +system.cpu1.iew.exec_stores 4241599 # Number of stores executed +system.cpu1.iew.exec_rate 0.103764 # Inst execution rate +system.cpu1.iew.wb_sent 41086324 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 25025175 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 11348419 # num instructions producing a value +system.cpu1.iew.wb_consumers 16538487 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131621 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.557843 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.063060 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.686182 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13879712 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899341 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 318567 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111667919 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.440684 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.404622 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1702265 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 769163 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 191007 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 394940200 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.061056 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 0.422241 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 93786179 83.99% 83.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9487781 8.50% 92.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2098555 1.88% 94.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1338170 1.20% 95.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 960614 0.86% 96.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 571645 0.51% 96.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1030883 0.92% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 527820 0.47% 98.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1866272 1.67% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 381244473 96.53% 96.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9114140 2.31% 98.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2236589 0.57% 99.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 955406 0.24% 99.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 446570 0.11% 99.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 403381 0.10% 99.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 181575 0.05% 99.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 97100 0.02% 99.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 260966 0.07% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111667919 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38872746 # Number of instructions committed -system.cpu1.commit.committedOps 49210296 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 394940200 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 19609371 # Number of instructions committed +system.cpu1.commit.committedOps 24113599 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16982765 # Number of memory references committed -system.cpu1.commit.loads 9979998 # Number of loads committed -system.cpu1.commit.membars 195533 # Number of memory barriers committed -system.cpu1.commit.branches 6424967 # Number of branches committed -system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43922606 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553368 # Number of function calls committed. +system.cpu1.commit.refs 9369646 # Number of memory references committed +system.cpu1.commit.loads 5202699 # Number of loads committed +system.cpu1.commit.membars 162322 # Number of memory barriers committed +system.cpu1.commit.branches 3698878 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 21204966 # Number of committed integer instructions. +system.cpu1.commit.function_calls 385194 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 32167564 65.37% 65.37% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 58261 0.12% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 1706 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 9979998 20.28% 85.77% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 7002767 14.23% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 14709151 61.00% 61.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 33154 0.14% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 1648 0.01% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 5202699 21.58% 82.72% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 4166947 17.28% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 49210296 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1866272 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 24113599 # Class of committed instruction +system.cpu1.commit.bw_lim_events 260966 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 171825162 # The number of ROB reads -system.cpu1.rob.rob_writes 128514038 # The number of ROB writes -system.cpu1.timesIdled 1427088 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 299213387 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4796716848 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38803107 # Number of Instructions Simulated -system.cpu1.committedOps 49140657 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 10.646885 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.646885 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.093924 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.093924 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 391718305 # number of integer regfile reads -system.cpu1.int_regfile_writes 56505033 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5108 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes -system.cpu1.misc_regfile_reads 199117817 # number of misc regfile reads -system.cpu1.misc_regfile_writes 722972 # number of misc regfile writes -system.cpu1.icache.tags.replacements 616464 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.721065 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7090163 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 616976 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.491797 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74744507500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.721065 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974065 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974065 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 419589246 # The number of ROB reads +system.cpu1.rob.rob_writes 52032512 # The number of ROB writes +system.cpu1.timesIdled 248745 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1507220 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4845699469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 19539732 # Number of Instructions Simulated +system.cpu1.committedOps 24043960 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 20.309853 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 20.309853 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.049237 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.049237 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 45343306 # number of integer regfile reads +system.cpu1.int_regfile_writes 15599183 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5046 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes +system.cpu1.cc_regfile_reads 139131439 # number of cc regfile reads +system.cpu1.cc_regfile_writes 9348976 # number of cc regfile writes +system.cpu1.misc_regfile_reads 454367618 # number of misc regfile reads +system.cpu1.misc_regfile_writes 623445 # number of misc regfile writes +system.cpu1.icache.tags.replacements 439266 # number of replacements +system.cpu1.icache.tags.tagsinuse 497.815366 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 8166304 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 439778 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 18.569151 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 119618152250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 497.815366 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.972296 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.972296 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 8371129 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 8371129 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 7090163 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7090163 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7090163 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7090163 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7090163 # number of overall hits -system.cpu1.icache.overall_hits::total 7090163 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 663949 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 663949 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 663949 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 663949 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 663949 # number of overall misses -system.cpu1.icache.overall_misses::total 663949 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9003300184 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9003300184 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9003300184 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9003300184 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9003300184 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9003300184 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7754112 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7754112 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7754112 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7754112 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7754112 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7754112 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085625 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.085625 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085625 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.085625 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085625 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.085625 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13560.228548 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13560.228548 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13560.228548 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13560.228548 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3101 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 648 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 217 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.290323 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 648 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 9063984 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 9063984 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 8166304 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8166304 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8166304 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8166304 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8166304 # number of overall hits +system.cpu1.icache.overall_hits::total 8166304 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 457900 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 457900 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 457900 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 457900 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 457900 # number of overall misses +system.cpu1.icache.overall_misses::total 457900 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6264180115 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6264180115 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6264180115 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6264180115 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6264180115 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6264180115 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8624204 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8624204 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8624204 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8624204 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8624204 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8624204 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.053095 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.053095 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.053095 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.053095 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.053095 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.053095 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13680.236111 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13680.236111 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13680.236111 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13680.236111 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 882 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 53 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.641509 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46932 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 46932 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 46932 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 46932 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 46932 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 46932 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 617017 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 617017 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 617017 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 617017 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 617017 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 617017 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7343865656 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7343865656 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7343865656 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7343865656 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7343865656 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7343865656 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4135000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4135000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4135000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 4135000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079573 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.079573 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.079573 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11902.209592 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 18120 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 18120 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 18120 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 18120 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 18120 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 18120 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 439780 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 439780 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 439780 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 439780 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 439780 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 439780 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5188034078 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5188034078 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5188034078 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5188034078 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5188034078 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5188034078 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4304000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4304000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4304000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 4304000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.050994 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.050994 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.050994 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11796.884983 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 363234 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.053035 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 13011922 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 363603 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.786069 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70837218250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.053035 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947369 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.947369 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 369 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.720703 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 60324528 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 60324528 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 8516413 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8516413 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4259216 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4259216 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99616 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 99616 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97058 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 97058 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12775629 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12775629 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12775629 # number of overall hits -system.cpu1.dcache.overall_hits::total 12775629 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 409488 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 409488 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1576995 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1576995 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14210 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14210 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10944 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10944 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1986483 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1986483 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1986483 # number of overall misses -system.cpu1.dcache.overall_misses::total 1986483 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6227092173 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6227092173 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 74233295889 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 74233295889 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131030244 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 131030244 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58441088 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 58441088 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 80460388062 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 80460388062 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 80460388062 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 80460388062 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8925901 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8925901 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5836211 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5836211 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113826 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 113826 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108002 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 108002 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14762112 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14762112 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14762112 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14762112 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045876 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045876 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.270209 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.270209 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124840 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124840 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101331 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101331 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134566 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.134566 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134566 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134566 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15207.019920 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15207.019920 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47072.626032 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 47072.626032 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9220.988318 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9220.988318 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5340.011696 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5340.011696 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 40503.939909 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 40503.939909 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 30714 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 17665 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3287 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 190 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.344083 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 92.973684 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 227040 # number of replacements +system.cpu1.dcache.tags.tagsinuse 492.830733 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7082160 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 227406 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 31.143242 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 99092137500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.830733 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.962560 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.962560 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 32684037 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 32684037 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3792757 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3792757 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3094601 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3094601 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 14161 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 14161 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 75622 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 75622 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 75613 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 75613 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6887358 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6887358 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6901519 # number of overall hits +system.cpu1.dcache.overall_hits::total 6901519 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 187422 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 187422 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 806941 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 806941 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 41483 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 41483 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10414 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10414 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9617 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9617 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 994363 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 994363 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1035846 # number of overall misses +system.cpu1.dcache.overall_misses::total 1035846 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2444126213 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2444126213 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 27779707617 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 27779707617 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 86490246 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 86490246 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53209125 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53209125 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 14000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 14000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 30223833830 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 30223833830 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 30223833830 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 30223833830 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3980179 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3980179 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3901542 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3901542 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 55644 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 55644 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86036 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 86036 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85230 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 85230 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7881721 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7881721 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7937365 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7937365 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047089 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.047089 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.206826 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.206826 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.745507 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.745507 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121042 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121042 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112836 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112836 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.126161 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.126161 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.130503 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.130503 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13040.764761 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13040.764761 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34425.946404 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34425.946404 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8305.189745 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8305.189745 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5532.819486 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5532.819486 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30395.171411 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 30395.171411 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29177.922037 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29177.922037 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 723 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 6.190871 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327552 # number of writebacks -system.cpu1.dcache.writebacks::total 327552 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178171 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 178171 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1413840 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1413840 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1455 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1455 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1592011 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1592011 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1592011 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1592011 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231317 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231317 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163155 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163155 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12755 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12755 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10944 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10944 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394472 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394472 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394472 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394472 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2894401946 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2894401946 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6921941032 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6921941032 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89586755 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89586755 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36550912 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36550912 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9816342978 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9816342978 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9816342978 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9816342978 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231628259 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231628259 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25874415734 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25874415734 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195106043993 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195106043993 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025915 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025915 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027956 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027956 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112057 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112057 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101331 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101331 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026722 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026722 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.707436 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.707436 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42425.552585 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42425.552585 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7023.657781 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7023.657781 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3339.812865 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3339.812865 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 207281 # number of writebacks +system.cpu1.dcache.writebacks::total 207281 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 70540 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 70540 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 693700 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 693700 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 500 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 500 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 764240 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 764240 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 764240 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 764240 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116882 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 116882 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 113241 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 113241 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23891 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23891 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9617 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9617 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 230123 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 230123 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254014 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254014 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203808322 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203808322 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3988299754 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3988299754 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 341716536 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 341716536 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 60834504 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 60834504 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 33974875 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 33974875 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 12000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 12000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5192108076 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5192108076 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5533824612 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5533824612 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168973544758 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168973544758 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 522517625 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 522517625 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 169496062383 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 169496062383 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029366 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029366 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029025 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029025 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.429354 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.429354 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.115231 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.115231 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112836 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112836 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029197 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029197 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032002 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032002 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10299.347393 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10299.347393 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35219.573776 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35219.573776 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14303.149136 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14303.149136 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6136.221908 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6136.221908 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3532.793491 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3532.793491 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22562.317004 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22562.317004 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21785.510295 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21785.510295 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2294,18 +2330,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1734300149849 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1734300149849 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736665659303 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736665659303 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42635 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 52427 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50404 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 40685 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 8259c3ed2..e77a65365 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525889 # Number of seconds simulated -sim_ticks 2525888859000 # Number of ticks simulated -final_tick 2525888859000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542203 # Number of seconds simulated +sim_ticks 2542202956000 # Number of ticks simulated +final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66506 # Simulator instruction rate (inst/s) -host_op_rate 85575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2785423099 # Simulator tick rate (ticks/s) -host_mem_usage 419792 # Number of bytes of host memory used -host_seconds 906.82 # Real time elapsed on the host -sim_insts 60309513 # Number of instructions simulated -sim_ops 77601128 # Number of ops (including micro ops) simulated +host_inst_rate 47189 # Simulator instruction rate (inst/s) +host_op_rate 56852 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1989066585 # Simulator tick rate (ticks/s) +host_mem_usage 412724 # Number of bytes of host memory used +host_seconds 1278.09 # Real time elapsed on the host +sim_insts 60311945 # Number of instructions simulated +sim_ops 72661478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094168 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory +system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142132 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096846 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 14991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15295607 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47324990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51242245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692556 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47324990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53934801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096846 # Number of read requests accepted -system.physmem.writeReqs 813159 # Number of write requests accepted -system.physmem.readBursts 15096846 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 961407104 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4791040 # Total number of bytes read from write queue -system.physmem.bytesWritten 6818432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129432216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 74860 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706594 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943526 # Per bank write bursts -system.physmem.perBankRdBursts::1 937990 # Per bank write bursts -system.physmem.perBankRdBursts::2 937469 # Per bank write bursts -system.physmem.perBankRdBursts::3 937431 # Per bank write bursts -system.physmem.perBankRdBursts::4 943079 # Per bank write bursts -system.physmem.perBankRdBursts::5 938170 # Per bank write bursts -system.physmem.perBankRdBursts::6 937203 # Per bank write bursts -system.physmem.perBankRdBursts::7 936910 # Per bank write bursts -system.physmem.perBankRdBursts::8 943866 # Per bank write bursts -system.physmem.perBankRdBursts::9 938107 # Per bank write bursts -system.physmem.perBankRdBursts::10 936563 # Per bank write bursts -system.physmem.perBankRdBursts::11 936045 # Per bank write bursts -system.physmem.perBankRdBursts::12 943886 # Per bank write bursts -system.physmem.perBankRdBursts::13 937531 # Per bank write bursts -system.physmem.perBankRdBursts::14 937186 # Per bank write bursts -system.physmem.perBankRdBursts::15 937024 # Per bank write bursts -system.physmem.perBankWrBursts::0 6617 # Per bank write bursts -system.physmem.perBankWrBursts::1 6376 # Per bank write bursts -system.physmem.perBankWrBursts::2 6529 # Per bank write bursts -system.physmem.perBankWrBursts::3 6558 # Per bank write bursts -system.physmem.perBankWrBursts::4 6459 # Per bank write bursts -system.physmem.perBankWrBursts::5 6705 # Per bank write bursts -system.physmem.perBankWrBursts::6 6711 # Per bank write bursts -system.physmem.perBankWrBursts::7 6649 # Per bank write bursts -system.physmem.perBankWrBursts::8 7036 # Per bank write bursts -system.physmem.perBankWrBursts::9 6794 # Per bank write bursts -system.physmem.perBankWrBursts::10 6454 # Per bank write bursts -system.physmem.perBankWrBursts::11 6111 # Per bank write bursts -system.physmem.perBankWrBursts::12 7073 # Per bank write bursts -system.physmem.perBankWrBursts::13 6679 # Per bank write bursts -system.physmem.perBankWrBursts::14 6963 # Per bank write bursts -system.physmem.perBankWrBursts::15 6824 # Per bank write bursts +system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47639992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51523292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1472436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15295607 # Number of read requests accepted +system.physmem.writeReqs 812506 # Number of write requests accepted +system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue +system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955786 # Per bank write bursts +system.physmem.perBankRdBursts::1 955478 # Per bank write bursts +system.physmem.perBankRdBursts::2 953003 # Per bank write bursts +system.physmem.perBankRdBursts::3 951059 # Per bank write bursts +system.physmem.perBankRdBursts::4 958601 # Per bank write bursts +system.physmem.perBankRdBursts::5 955602 # Per bank write bursts +system.physmem.perBankRdBursts::6 952653 # Per bank write bursts +system.physmem.perBankRdBursts::7 950407 # Per bank write bursts +system.physmem.perBankRdBursts::8 956154 # Per bank write bursts +system.physmem.perBankRdBursts::9 955874 # Per bank write bursts +system.physmem.perBankRdBursts::10 952889 # Per bank write bursts +system.physmem.perBankRdBursts::11 950148 # Per bank write bursts +system.physmem.perBankRdBursts::12 956166 # Per bank write bursts +system.physmem.perBankRdBursts::13 955918 # Per bank write bursts +system.physmem.perBankRdBursts::14 953918 # Per bank write bursts +system.physmem.perBankRdBursts::15 950940 # Per bank write bursts +system.physmem.perBankWrBursts::0 6546 # Per bank write bursts +system.physmem.perBankWrBursts::1 6352 # Per bank write bursts +system.physmem.perBankWrBursts::2 6488 # Per bank write bursts +system.physmem.perBankWrBursts::3 6518 # Per bank write bursts +system.physmem.perBankWrBursts::4 6421 # Per bank write bursts +system.physmem.perBankWrBursts::5 6701 # Per bank write bursts +system.physmem.perBankWrBursts::6 6665 # Per bank write bursts +system.physmem.perBankWrBursts::7 6611 # Per bank write bursts +system.physmem.perBankWrBursts::8 6966 # Per bank write bursts +system.physmem.perBankWrBursts::9 6759 # Per bank write bursts +system.physmem.perBankWrBursts::10 6421 # Per bank write bursts +system.physmem.perBankWrBursts::11 6055 # Per bank write bursts +system.physmem.perBankWrBursts::12 7037 # Per bank write bursts +system.physmem.perBankWrBursts::13 6645 # Per bank write bursts +system.physmem.perBankWrBursts::14 6920 # Per bank write bursts +system.physmem.perBankWrBursts::15 6806 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525887732500 # Total gap between requests +system.physmem.totGap 2542201638000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 38 # Read request sizes (log2) -system.physmem.readPktSize::3 14942208 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::2 18 # Read request sizes (log2) +system.physmem.readPktSize::3 15138826 # Read request sizes (log2) +system.physmem.readPktSize::4 3351 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154600 # Read request sizes (log2) +system.physmem.readPktSize::6 153412 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59141 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1057329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 995712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 953847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1057444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 956989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1015779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2635918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2545995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3318157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 125455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 108163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 99319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 95398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58488 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1110293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 964892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 965548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1076032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 973735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1036027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2680967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2587988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3368391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 111642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 103064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98734 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,28 +159,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -208,125 +208,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 995372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 972.727318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 907.205467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 202.336600 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22984 2.31% 2.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19752 1.98% 4.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8337 0.84% 5.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2265 0.23% 5.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2301 0.23% 5.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1840 0.18% 5.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8587 0.86% 6.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 978 0.10% 6.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 928328 93.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 995372 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2406.981894 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 114987.414706 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6237 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.070662 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.017388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.386394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3585 57.44% 57.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 32 0.51% 57.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1616 25.89% 83.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 845 13.54% 97.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 54 0.87% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 36 0.58% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 33 0.53% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 31 0.50% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.14% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads -system.physmem.totQLat 389024977250 # Total ticks spent queuing -system.physmem.totMemAccLat 670687214750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75109930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25897.04 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads +system.physmem.totQLat 395449280750 # Total ticks spent queuing +system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44647.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.99 # Data bus utilization in percentage -system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.02 # Data bus utilization in percentage +system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing -system.physmem.readRowHits 14042089 # Number of row buffer hits during reads -system.physmem.writeRowHits 91063 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing +system.physmem.readRowHits 14269193 # Number of row buffer hits during reads +system.physmem.writeRowHits 90708 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes -system.physmem.avgGap 158760.96 # Average gap between requests +system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes +system.physmem.avgGap 157821.19 # Average gap between requests system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2186215098000 # Time in different power states -system.physmem.memoryStateTime::REF 84344780000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states +system.physmem.memoryStateTime::REF 84889480000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 255323240750 # Time in different power states +system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54884184 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149487 # Transaction distribution -system.membus.trans_dist::ReadResp 16149487 # Transaction distribution -system.membus.trans_dist::WriteReq 763349 # Transaction distribution -system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59141 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution -system.membus.trans_dist::ReadExReq 131431 # Transaction distribution -system.membus.trans_dist::ReadExResp 131431 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55125441 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16348039 # Transaction distribution +system.membus.trans_dist::ReadResp 16348039 # Transaction distribution +system.membus.trans_dist::WriteReq 763357 # Transaction distribution +system.membus.trans_dist::WriteResp 763357 # Transaction distribution +system.membus.trans_dist::Writeback 58488 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution +system.membus.trans_dist::ReadExReq 131651 # Transaction distribution +system.membus.trans_dist::ReadExResp 131651 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272651 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157067 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390450 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16695648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19093686 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138631350 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138631350 # Total data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140140058 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486861000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3602500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17311099000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4710414902 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 36916757411 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -334,15 +334,15 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48271369 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125555 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125555 # Transaction distribution -system.iobus.trans_dist::WriteReq 8174 # Transaction distribution -system.iobus.trans_dist::WriteResp 8174 # Transaction distribution +system.iobus.throughput 48580309 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution +system.iobus.trans_dist::WriteReq 8176 # Transaction distribution +system.iobus.trans_dist::WriteResp 8176 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -362,14 +362,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -389,18 +389,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390450 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121928114 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121928114 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123501006 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -440,22 +440,22 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37649719589 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14910337 # Number of BP lookups -system.cpu.branchPred.condPredicted 11976867 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705848 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9580478 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7742107 # Number of BTB hits +system.cpu.branchPred.lookups 13201290 # Number of BP lookups +system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.811281 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1408303 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72648 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -479,25 +479,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51097792 # DTB read hits -system.cpu.dtb.read_misses 64987 # DTB read misses -system.cpu.dtb.write_hits 11709971 # DTB write hits -system.cpu.dtb.write_misses 15921 # DTB write misses +system.cpu.dtb.read_hits 31642294 # DTB read hits +system.cpu.dtb.read_misses 39524 # DTB read misses +system.cpu.dtb.write_hits 11381361 # DTB write hits +system.cpu.dtb.write_misses 10135 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3472 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2569 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 428 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51162779 # DTB read accesses -system.cpu.dtb.write_accesses 11725892 # DTB write accesses +system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 31681818 # DTB read accesses +system.cpu.dtb.write_accesses 11391496 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62807763 # DTB hits -system.cpu.dtb.misses 80908 # DTB misses -system.cpu.dtb.accesses 62888671 # DTB accesses +system.cpu.dtb.hits 43023655 # DTB hits +system.cpu.dtb.misses 49659 # DTB misses +system.cpu.dtb.accesses 43073314 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -519,8 +519,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11575507 # ITB inst hits -system.cpu.itb.inst_misses 11335 # ITB inst misses +system.cpu.itb.inst_hits 24159481 # ITB inst hits +system.cpu.itb.inst_misses 10516 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -529,607 +529,598 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2514 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2954 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11586842 # ITB inst accesses -system.cpu.itb.hits 11575507 # DTB hits -system.cpu.itb.misses 11335 # DTB misses -system.cpu.itb.accesses 11586842 # DTB accesses -system.cpu.numCycles 476238509 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 24169997 # ITB inst accesses +system.cpu.itb.hits 24159481 # DTB hits +system.cpu.itb.misses 10516 # DTB misses +system.cpu.itb.accesses 24169997 # DTB accesses +system.cpu.numCycles 499350041 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29789702 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91027179 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14910337 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9150410 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20302096 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4754274 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125108 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93772455 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2699 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88682 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2727734 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 553 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11572027 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 712397 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5390 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150113292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.756026 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.113644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 129826802 86.49% 86.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1312716 0.87% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1720953 1.15% 88.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2304331 1.54% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2116294 1.41% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1112529 0.74% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2605432 1.74% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 752346 0.50% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8361889 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150113292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031309 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.191138 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31268958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96222513 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18495001 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 992442 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3134378 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1970530 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172531 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 108153308 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572201 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3134378 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32906794 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14229038 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 56831984 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17995352 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25015746 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103064055 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1610 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17097046 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 19764397 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2757051 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 1781 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107250734 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 477314257 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 435890251 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10500 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727504 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28523229 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1172187 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1078501 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 11007211 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19896895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13369840 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2003415 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2457274 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95806828 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1986007 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122955094 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 190842 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19616274 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 49695395 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 503680 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150113292 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819082 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.543742 # Number of insts issued each cycle +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.548412 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106692829 71.07% 71.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13471343 8.97% 80.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6554897 4.37% 84.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5548193 3.70% 88.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12665338 8.44% 96.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2805396 1.87% 98.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723552 1.15% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 514218 0.34% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 137526 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 430558497 86.88% 86.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150113292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66740 0.75% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8421993 94.18% 94.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 453824 5.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58064867 47.22% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52433900 42.64% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12332230 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122955094 # Type of FU issued -system.cpu.iq.rate 0.258180 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8942563 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.072730 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 405214220 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117427083 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85619955 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23208 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131856805 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 652625 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued +system.cpu.iq.rate 0.188050 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4242114 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5511 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 31676 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1637740 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33981236 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 675243 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3134378 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11621778 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1344860 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98019144 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 177250 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19896895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13369840 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1412264 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 282212 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 925122 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 31676 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351157 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270951 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 622108 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120868290 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51786364 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2086804 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 226309 # number of nop insts executed -system.cpu.iew.exec_refs 64008543 # number of memory reference insts executed -system.cpu.iew.exec_branches 11843747 # Number of branches executed -system.cpu.iew.exec_stores 12222179 # Number of stores executed -system.cpu.iew.exec_rate 0.253798 # Inst execution rate -system.cpu.iew.wb_sent 119919333 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85630251 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47892202 # num instructions producing a value -system.cpu.iew.wb_consumers 88557277 # num instructions consuming a value +system.cpu.iew.exec_nop 176010 # number of nop insts executed +system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed +system.cpu.iew.exec_branches 10791342 # Number of branches executed +system.cpu.iew.exec_stores 11888889 # Number of stores executed +system.cpu.iew.exec_rate 0.186738 # Inst execution rate +system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back +system.cpu.iew.wb_producers 35465784 # num instructions producing a value +system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179805 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.540805 # average fanout of values written-back +system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19373634 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482327 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535963 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146978914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.528998 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.513466 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118714103 80.77% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14514329 9.88% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3718532 2.53% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2215097 1.51% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1629859 1.11% 95.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1057435 0.72% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1495738 1.02% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 696782 0.47% 98.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2937039 2.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146978914 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60459894 # Number of instructions committed -system.cpu.commit.committedOps 77751509 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60462326 # Number of instructions committed +system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386881 # Number of memory references committed -system.cpu.commit.loads 15654781 # Number of loads committed -system.cpu.commit.membars 403574 # Number of memory barriers committed -system.cpu.commit.branches 10306383 # Number of branches committed +system.cpu.commit.refs 25244569 # Number of memory references committed +system.cpu.commit.loads 13512926 # Number of loads committed +system.cpu.commit.membars 403660 # Number of memory barriers committed +system.cpu.commit.branches 10308073 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69191543 # Number of committed integer instructions. -system.cpu.commit.function_calls 991261 # Number of function calls committed. +system.cpu.commit.int_insts 64250122 # Number of committed integer instructions. +system.cpu.commit.function_calls 991634 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 50274580 64.66% 64.66% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 15654781 20.13% 84.91% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11732100 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 77751509 # Class of committed instruction -system.cpu.commit.bw_lim_events 2937039 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction +system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239318561 # The number of ROB reads -system.cpu.rob.rob_writes 197472000 # The number of ROB writes -system.cpu.timesIdled 1764819 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 326125217 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575456172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309513 # Number of Instructions Simulated -system.cpu.committedOps 77601128 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.896574 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.896574 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126637 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126637 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548833940 # number of integer regfile reads -system.cpu.int_regfile_writes 87707844 # number of integer regfile writes -system.cpu.fp_regfile_reads 8328 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 264312368 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173237 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58892733 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607940 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5797376 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30926 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128827 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7919103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85556470 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148561726 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148561726 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 194772 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129487727 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 568287463 # The number of ROB reads +system.cpu.rob.rob_writes 154414560 # The number of ROB writes +system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60311945 # Number of Instructions Simulated +system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads +system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 109116898 # number of integer regfile reads +system.cpu.int_regfile_writes 47012340 # number of integer regfile writes +system.cpu.fp_regfile_reads 8305 # number of floating regfile reads +system.cpu.fp_regfile_writes 2780 # number of floating regfile writes +system.cpu.cc_regfile_reads 320404185 # number of cc regfile reads +system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes +system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes +system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474700416 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1447056987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550487184 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2544187527 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20248986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 17686240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74797546 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 51535649 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980898 # number of replacements -system.cpu.icache.tags.tagsinuse 511.584882 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10510158 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981410 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.709243 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6868426250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.584882 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999189 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 959881 # number of replacements +system.cpu.icache.tags.tagsinuse 511.383361 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23149457 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 960393 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 24.104150 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 11344582250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.383361 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12553342 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12553342 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10510158 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10510158 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10510158 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10510158 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10510158 # number of overall hits -system.cpu.icache.overall_hits::total 10510158 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061739 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061739 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061739 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061739 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061739 # number of overall misses -system.cpu.icache.overall_misses::total 1061739 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14266290615 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14266290615 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14266290615 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14266290615 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14266290615 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14266290615 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11571897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11571897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11571897 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11571897 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11571897 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11571897 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091752 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091752 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091752 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091752 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091752 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091752 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13436.720903 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13436.720903 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13436.720903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13436.720903 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7331 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 116 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.883582 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 116 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 25115239 # Number of tag accesses +system.cpu.icache.tags.data_accesses 25115239 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23149457 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23149457 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23149457 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23149457 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23149457 # number of overall hits +system.cpu.icache.overall_hits::total 23149457 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1005369 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1005369 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1005369 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1005369 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1005369 # number of overall misses +system.cpu.icache.overall_misses::total 1005369 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13656038478 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13656038478 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13656038478 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13656038478 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13656038478 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13656038478 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24154826 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24154826 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24154826 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24154826 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24154826 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24154826 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13583.110756 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13583.110756 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 119 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.588235 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80293 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 80293 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 80293 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 80293 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 80293 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 80293 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981446 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981446 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981446 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981446 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981446 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981446 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11573178578 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11573178578 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11573178578 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11573178578 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11573178578 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11573178578 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8964000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8964000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8964000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8964000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084813 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.084813 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.084813 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11791.966729 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11791.966729 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44956 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 44956 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 44956 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 44956 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 44956 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 44956 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960413 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 960413 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 960413 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 960413 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 960413 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 960413 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283890760 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11283890760 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283890760 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11283890760 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283890760 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11283890760 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223026500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223026500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223026500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 223026500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039761 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.039761 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.039761 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64369 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51363.817213 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1888922 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129761 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.556932 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2490733870000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36937.336839 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 33.862464 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000252 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8170.435646 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6222.182012 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563619 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000517 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 63302 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51128.734687 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1829071 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 128690 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.213000 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2530789670500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37302.599889 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.814194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7723.154288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.165612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.569193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000104 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124671 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.094943 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783750 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65369 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3050 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54961 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997452 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18802940 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18802940 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54086 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10683 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967938 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387449 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1420156 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607940 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607940 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112904 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112904 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 54086 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10683 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967938 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500353 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1533060 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 54086 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10683 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967938 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500353 # number of overall hits -system.cpu.l2cache.overall_hits::total 1533060 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 48 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12347 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10729 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23125 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133201 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133201 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 48 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12347 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143930 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156326 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 48 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12347 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143930 # number of overall misses -system.cpu.l2cache.overall_misses::total 156326 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3943500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 83000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 890764250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 800380499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1695171249 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 583475 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 583475 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9778985980 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9778985980 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3943500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 83000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 890764250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10579366479 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11474157229 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3943500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 83000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 890764250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10579366479 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11474157229 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54134 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10684 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 980285 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 398178 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1443281 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607940 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607940 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246105 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54134 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10684 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 980285 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 644283 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1689386 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54134 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10684 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 980285 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 644283 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1689386 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000887 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000094 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012595 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026945 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016023 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985502 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985502 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.272727 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.272727 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541236 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541236 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000887 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000094 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012595 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223396 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092534 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000887 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000094 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012595 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223396 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092534 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 82156.250000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72144.184822 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74599.729611 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73304.702659 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 199.615121 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 199.615121 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73415.259495 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73415.259495 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 82156.250000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72144.184822 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73503.553665 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73398.905038 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 82156.250000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72144.184822 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73503.553665 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73398.905038 # average overall miss latency +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117846 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.093020 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.780163 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65381 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3024 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6221 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55835 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997635 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18316308 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18316308 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33888 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9476 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 947771 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 377103 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1368238 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 599976 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 599976 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113216 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113216 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 33888 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 9476 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 947771 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 490319 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1481454 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 33888 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 9476 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 947771 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 490319 # number of overall hits +system.cpu.l2cache.overall_hits::total 1481454 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 11654 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10148 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 21816 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2909 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133354 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133354 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 11 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 11654 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143502 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 155170 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 11 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 11654 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143502 # number of overall misses +system.cpu.l2cache.overall_misses::total 155170 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 830265249 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 761175750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1592469999 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 348485 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9338459797 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9338459797 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 830265249 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10099635547 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10930929796 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 830265249 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10099635547 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10930929796 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33899 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9479 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 959425 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 387251 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1390054 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 599976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 599976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2950 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246570 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246570 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33899 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 9479 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 959425 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 633821 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1636624 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33899 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 9479 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 959425 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 633821 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1636624 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000324 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000316 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012147 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026205 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015694 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986102 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986102 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540836 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.540836 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000324 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000316 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012147 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.226408 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.094811 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000324 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000316 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012147 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.226408 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.094811 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71840.909091 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79583.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71242.942252 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75007.464525 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72995.507838 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 119.795462 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 119.795462 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70027.594200 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70027.594200 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70444.865605 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70444.865605 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1138,109 +1129,104 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59141 # number of writebacks -system.cpu.l2cache.writebacks::total 59141 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 48 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12336 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10663 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133201 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133201 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 48 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12336 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143864 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156249 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 48 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12336 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143864 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156249 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3351000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 71000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 734971750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 663368999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1401762749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29236922 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29236922 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8137112520 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8137112520 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3351000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 71000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 734971750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8800481519 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9538875269 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3351000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 71000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 734971750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8800481519 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9538875269 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6435500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942048250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948483750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17498078150 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17498078150 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6435500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184440126400 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184446561900 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026779 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015969 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985502 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985502 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.272727 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541236 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541236 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092489 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092489 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59579.422017 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62212.229110 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60819.279287 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.368115 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.368115 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61088.974707 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61088.974707 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 58488 # number of writebacks +system.cpu.l2cache.writebacks::total 58488 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11640 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10108 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 21761 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133354 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133354 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 11640 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143462 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 155115 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 11640 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143462 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 155115 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 596250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 201250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 683475499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 632292750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1316565749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29106909 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29106909 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7676486703 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7676486703 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 596250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 201250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 683475499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8308779453 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8993052452 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 596250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 201250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 683475499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8308779453 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8993052452 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174348000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167014389750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167188737750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17147727018 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17147727018 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174348000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184162116768 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184336464768 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015655 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.094777 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.094777 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58717.826375 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62553.695093 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60501.160287 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.812650 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.812650 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57564.727740 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57564.727740 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1250,168 +1236,184 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643771 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993313 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21491250 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 644283 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.356848 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 42393250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993313 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 633309 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.949942 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19068560 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 633821 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.085087 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.949942 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101573451 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101573451 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13743815 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13743815 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7253892 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7253892 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242816 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242816 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 20997707 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20997707 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20997707 # number of overall hits -system.cpu.dcache.overall_hits::total 20997707 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 762201 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 762201 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2968429 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2968429 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13530 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13530 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3730630 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3730630 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3730630 # number of overall misses -system.cpu.dcache.overall_misses::total 3730630 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10170757825 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10170757825 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 136412874713 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 136412874713 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184826749 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184826749 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 180503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 180503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 146583632538 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 146583632538 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 146583632538 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 146583632538 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14506016 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14506016 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256346 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256346 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247609 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247609 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24728337 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24728337 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24728337 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24728337 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052544 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052544 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290387 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.290387 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052780 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052780 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.150865 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.150865 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.150865 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.150865 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13343.931358 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13343.931358 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45954.568802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45954.568802 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13660.513599 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13660.513599 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16409.363636 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16409.363636 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39291.924564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39291.924564 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33676 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 25542 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2667 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 316 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.626922 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 80.829114 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 91797001 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 91797001 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11311240 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11311240 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7209458 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7209458 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60823 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60823 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236444 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236444 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 18520698 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18520698 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18581521 # number of overall hits +system.cpu.dcache.overall_hits::total 18581521 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 573261 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 573261 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3012484 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3012484 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 126501 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 126501 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 12988 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 12988 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3585745 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3585745 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3712246 # number of overall misses +system.cpu.dcache.overall_misses::total 3712246 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7216358166 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7216358166 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126016512064 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126016512064 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 178185500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 178185500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133232870230 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133232870230 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133232870230 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133232870230 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 11884501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11884501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10221942 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10221942 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 187324 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 187324 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 249432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 22106443 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 22106443 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 22293767 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 22293767 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048236 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.048236 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675306 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.675306 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052070 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052070 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.162204 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.162204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.166515 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.166515 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12588.259390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12588.259390 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41831.429499 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41831.429499 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13719.240838 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13719.240838 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37156.259084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37156.259084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35890.097324 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35890.097324 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18826 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1227 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.343113 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607940 # number of writebacks -system.cpu.dcache.writebacks::total 607940 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 376141 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 376141 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2719425 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2719425 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3095566 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3095566 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3095566 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3095566 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386060 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386060 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249004 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249004 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635064 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635064 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635064 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635064 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4968476363 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4968476363 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11232028289 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11232028289 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145250501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145250501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 158497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 158497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16200504652 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16200504652 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16200504652 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16200504652 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26891357119 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26891357119 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047533 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047533 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 599976 # number of writebacks +system.cpu.dcache.writebacks::total 599976 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271755 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 271755 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763119 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2763119 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3034874 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3034874 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3034874 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3034874 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 301506 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249365 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249365 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74145 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 74145 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11755 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11755 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 550871 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 550871 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 625016 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 625016 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569781578 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569781578 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10783879319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10783879319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1231283000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1231283000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140188500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140188500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14353660897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14353660897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15584943897 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15584943897 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26599942575 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26599942575 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1435,16 +1437,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1711484214589 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index d741bed70..3b38aee5d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403860 # Number of seconds simulated -sim_ticks 2403859810000 # Number of ticks simulated -final_tick 2403859810000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.400983 # Number of seconds simulated +sim_ticks 2400982506000 # Number of ticks simulated +final_tick 2400982506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189252 # Simulator instruction rate (inst/s) -host_op_rate 243065 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7540617560 # Simulator tick rate (ticks/s) -host_mem_usage 419508 # Number of bytes of host memory used -host_seconds 318.79 # Real time elapsed on the host -sim_insts 60331162 # Number of instructions simulated -sim_ops 77486236 # Number of ops (including micro ops) simulated +host_inst_rate 112943 # Simulator instruction rate (inst/s) +host_op_rate 135898 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4496473277 # Simulator tick rate (ticks/s) +host_mem_usage 411684 # Number of bytes of host memory used +host_seconds 533.97 # Real time elapsed on the host +sim_insts 60307964 # Number of instructions simulated +sim_ops 72565708 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 510792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7044824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 493064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6826968 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 65024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 679232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 75520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 799936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 188416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1352768 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 510792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 65024 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu2.data 1451264 # Number of bytes read from this memory +system.physmem.bytes_read::total 124655200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 493064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 75520 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 188416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 764232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3745216 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298452 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558108 # Number of bytes written to this memory -system.physmem.bytes_written::total 6761032 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 757000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3741312 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1144164 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159264 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1712388 # Number of bytes written to this memory +system.physmem.bytes_written::total 6757128 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14193 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110111 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 106697 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1016 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1180 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 2944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21137 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512414 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58519 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324613 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39814 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389527 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812473 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47764463 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.data 22676 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512311 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58458 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 286041 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39816 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 428097 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812412 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47821703 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 212488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2930630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 205359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2843406 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 27050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 78381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 562748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51858745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 212488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 27050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 78381 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1558001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66250 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812573 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1558001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47764463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 31454 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 333170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 78475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 604446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51918412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 31454 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 78475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1558242 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 476540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66333 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 713203 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2814318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1558242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47821703 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 212488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3470783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3319946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 27050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 78381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1210918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54671318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13444811 # Number of read requests accepted -system.physmem.writeReqs 446538 # Number of write requests accepted -system.physmem.readBursts 13444811 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446538 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860467840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue -system.physmem.bytesWritten 2823232 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109558976 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2817972 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 402393 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2368 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835670 # Per bank write bursts -system.physmem.perBankRdBursts::1 835346 # Per bank write bursts -system.physmem.perBankRdBursts::2 835517 # Per bank write bursts -system.physmem.perBankRdBursts::3 836010 # Per bank write bursts -system.physmem.perBankRdBursts::4 837094 # Per bank write bursts -system.physmem.perBankRdBursts::5 837780 # Per bank write bursts -system.physmem.perBankRdBursts::6 837922 # Per bank write bursts -system.physmem.perBankRdBursts::7 839142 # Per bank write bursts -system.physmem.perBankRdBursts::8 840618 # Per bank write bursts -system.physmem.perBankRdBursts::9 843327 # Per bank write bursts -system.physmem.perBankRdBursts::10 843373 # Per bank write bursts -system.physmem.perBankRdBursts::11 843894 # Per bank write bursts -system.physmem.perBankRdBursts::12 845193 # Per bank write bursts -system.physmem.perBankRdBursts::13 844981 # Per bank write bursts -system.physmem.perBankRdBursts::14 844356 # Per bank write bursts -system.physmem.perBankRdBursts::15 844587 # Per bank write bursts -system.physmem.perBankWrBursts::0 2683 # Per bank write bursts -system.physmem.perBankWrBursts::1 2536 # Per bank write bursts -system.physmem.perBankWrBursts::2 2524 # Per bank write bursts -system.physmem.perBankWrBursts::3 3040 # Per bank write bursts -system.physmem.perBankWrBursts::4 3434 # Per bank write bursts -system.physmem.perBankWrBursts::5 3138 # Per bank write bursts -system.physmem.perBankWrBursts::6 2510 # Per bank write bursts -system.physmem.perBankWrBursts::7 2271 # Per bank write bursts -system.physmem.perBankWrBursts::8 2160 # Per bank write bursts -system.physmem.perBankWrBursts::9 2378 # Per bank write bursts -system.physmem.perBankWrBursts::10 2319 # Per bank write bursts -system.physmem.perBankWrBursts::11 2803 # Per bank write bursts -system.physmem.perBankWrBursts::12 3771 # Per bank write bursts -system.physmem.perBankWrBursts::13 3447 # Per bank write bursts -system.physmem.perBankWrBursts::14 2601 # Per bank write bursts -system.physmem.perBankWrBursts::15 2498 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 31454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 399503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 78475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1317649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54732730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13448319 # Number of read requests accepted +system.physmem.writeReqs 485647 # Number of write requests accepted +system.physmem.readBursts 13448319 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 485647 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860692416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 3019520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109787968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3006628 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 438446 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2870 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 835559 # Per bank write bursts +system.physmem.perBankRdBursts::1 835684 # Per bank write bursts +system.physmem.perBankRdBursts::2 835582 # Per bank write bursts +system.physmem.perBankRdBursts::3 835955 # Per bank write bursts +system.physmem.perBankRdBursts::4 836860 # Per bank write bursts +system.physmem.perBankRdBursts::5 838029 # Per bank write bursts +system.physmem.perBankRdBursts::6 838426 # Per bank write bursts +system.physmem.perBankRdBursts::7 839444 # Per bank write bursts +system.physmem.perBankRdBursts::8 841128 # Per bank write bursts +system.physmem.perBankRdBursts::9 843519 # Per bank write bursts +system.physmem.perBankRdBursts::10 843777 # Per bank write bursts +system.physmem.perBankRdBursts::11 843721 # Per bank write bursts +system.physmem.perBankRdBursts::12 845312 # Per bank write bursts +system.physmem.perBankRdBursts::13 845603 # Per bank write bursts +system.physmem.perBankRdBursts::14 845260 # Per bank write bursts +system.physmem.perBankRdBursts::15 844460 # Per bank write bursts +system.physmem.perBankWrBursts::0 2621 # Per bank write bursts +system.physmem.perBankWrBursts::1 2605 # Per bank write bursts +system.physmem.perBankWrBursts::2 2850 # Per bank write bursts +system.physmem.perBankWrBursts::3 3117 # Per bank write bursts +system.physmem.perBankWrBursts::4 3557 # Per bank write bursts +system.physmem.perBankWrBursts::5 3522 # Per bank write bursts +system.physmem.perBankWrBursts::6 2837 # Per bank write bursts +system.physmem.perBankWrBursts::7 2549 # Per bank write bursts +system.physmem.perBankWrBursts::8 2654 # Per bank write bursts +system.physmem.perBankWrBursts::9 2632 # Per bank write bursts +system.physmem.perBankWrBursts::10 2402 # Per bank write bursts +system.physmem.perBankWrBursts::11 2522 # Per bank write bursts +system.physmem.perBankWrBursts::12 3817 # Per bank write bursts +system.physmem.perBankWrBursts::13 3843 # Per bank write bursts +system.physmem.perBankWrBursts::14 3141 # Per bank write bursts +system.physmem.perBankWrBursts::15 2511 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402823771000 # Total gap between requests +system.physmem.totGap 2398981428000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 13409088 # Read request sizes (log2) +system.physmem.readPktSize::3 13409008 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35723 # Read request sizes (log2) +system.physmem.readPktSize::6 39311 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429341 # Write request sizes (log2) +system.physmem.writePktSize::2 467913 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17197 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 877930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 852855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 852810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 941410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 861042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 915654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2398641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2321801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3038639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 92226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 84687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 80541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 77647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 16108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 28 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17734 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 878886 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 855155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 852902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 940592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 861312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 914649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2399113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2323436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3041002 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 84284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 79661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 76726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 16118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,42 +178,42 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -242,83 +242,84 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 865990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 996.883419 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 964.040735 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 145.863432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8417 0.97% 0.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8847 1.02% 1.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6111 0.71% 2.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 842 0.10% 2.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 894 0.10% 2.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 743 0.09% 2.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7672 0.89% 3.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 243 0.03% 3.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 832221 96.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 865990 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2416 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 5564.893626 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 258050.737776 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 2415 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 866402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 996.895132 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 964.187701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 145.697526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8320 0.96% 0.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8911 1.03% 1.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6111 0.71% 2.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 785 0.09% 2.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 956 0.11% 2.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 773 0.09% 2.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7768 0.90% 3.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 290 0.03% 3.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 832488 96.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 866402 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2583 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 5206.469222 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 249565.705681 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 2582 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2416 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2416 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.258692 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.106432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.116221 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 1 0.04% 0.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 2 0.08% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.08% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.04% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.04% 0.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 1 0.04% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 1 0.04% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 2 0.08% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 5 0.21% 0.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 486 20.12% 20.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 13 0.54% 21.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 855 35.39% 56.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 862 35.68% 92.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 56 2.32% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 20 0.83% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.83% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 33 1.37% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 16 0.66% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.25% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.25% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.17% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 7 0.29% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.25% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.17% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 4 0.17% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2416 # Writes before turning the bus around for reads -system.physmem.totQLat 346456254750 # Total ticks spent queuing -system.physmem.totMemAccLat 598546442250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67224050000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25768.77 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2583 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.265583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.091885 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.157240 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 3 0.12% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 1 0.04% 0.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.08% 0.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 2 0.08% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.04% 0.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 2 0.08% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 1 0.04% 0.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 3 0.12% 0.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 4 0.15% 0.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 537 20.79% 21.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.27% 21.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 754 29.19% 51.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1050 40.65% 91.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 100 3.87% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 31 1.20% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 20 0.77% 97.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 15 0.58% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.35% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.12% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.27% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.19% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.19% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 5 0.19% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 6 0.23% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 4 0.15% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 5 0.19% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2583 # Writes before turning the bus around for reads +system.physmem.totQLat 346447958000 # Total ticks spent queuing +system.physmem.totMemAccLat 598603939250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67241595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25761.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44518.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 357.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44511.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.25 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 8.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 5.37 # Average write queue length when enqueuing -system.physmem.readRowHits 12585053 # Number of row buffer hits during reads -system.physmem.writeRowHits 37880 # Number of row buffer hits during writes +system.physmem.avgRdQLen 7.91 # Average read queue length when enqueuing +system.physmem.avgWrQLen 2.57 # Average write queue length when enqueuing +system.physmem.readRowHits 12588353 # Number of row buffer hits during reads +system.physmem.writeRowHits 40744 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.81 # Row buffer hit rate for writes -system.physmem.avgGap 172972.67 # Average gap between requests +system.physmem.writeRowHitRate 86.32 # Row buffer hit rate for writes +system.physmem.avgGap 172167.88 # Average gap between requests system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2167576169750 # Time in different power states -system.physmem.memoryStateTime::REF 80270060000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2165142880250 # Time in different power states +system.physmem.memoryStateTime::REF 80173860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 156010779000 # Time in different power states +system.physmem.memoryStateTime::ACT 155659356000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -332,322 +333,323 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55668579 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13780402 # Transaction distribution -system.membus.trans_dist::ReadResp 13780402 # Transaction distribution -system.membus.trans_dist::WriteReq 432242 # Transaction distribution -system.membus.trans_dist::WriteResp 432242 # Transaction distribution -system.membus.trans_dist::Writeback 17197 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2368 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2368 # Transaction distribution -system.membus.trans_dist::ReadExReq 28083 # Transaction distribution -system.membus.trans_dist::ReadExResp 28083 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 732930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 952061 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1685211 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26818176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26818176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28503387 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 736825 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5104244 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5841509 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107272704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107272704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113114213 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133819459 # Total data (bytes) +system.membus.throughput 55731244 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13775425 # Transaction distribution +system.membus.trans_dist::ReadResp 13775425 # Transaction distribution +system.membus.trans_dist::WriteReq 471057 # Transaction distribution +system.membus.trans_dist::WriteResp 471057 # Transaction distribution +system.membus.trans_dist::Writeback 17734 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2870 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2870 # Transaction distribution +system.membus.trans_dist::ReadExReq 31339 # Transaction distribution +system.membus.trans_dist::ReadExResp 31339 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 722736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1037922 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1761100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26818016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26818016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28579116 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 726717 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5522532 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6250133 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107272064 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107272064 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113522197 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133809743 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 417666500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 411651000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 449000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14570118500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 14677819500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1595700088 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1677943291 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 33207877250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33210614750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63255 # number of replacements -system.l2c.tags.tagsinuse 50395.732810 # Cycle average of tags in use -system.l2c.tags.total_refs 1749595 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128654 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.599227 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375537274500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36859.250431 # Average occupied blocks per requestor +system.l2c.tags.replacements 63162 # number of replacements +system.l2c.tags.tagsinuse 50410.338960 # Cycle average of tags in use +system.l2c.tags.total_refs 1759139 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128553 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.684154 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2389834567500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36865.555388 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5225.740605 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3831.207928 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 514.351835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 694.414886 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.820575 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1674.526375 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1584.426715 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562428 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4868.284859 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3674.892610 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993335 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 794.582710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 806.547655 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832999 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1730.563101 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1659.086161 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562524 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079738 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058460 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074284 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.056074 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007848 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010596 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000165 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025551 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024176 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768978 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65393 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2636 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6462 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55911 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997818 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17684075 # Number of tag accesses -system.l2c.tags.data_accesses 17684075 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8753 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3188 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 465928 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 176871 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2616 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1178 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 130375 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64441 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18901 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4190 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 282805 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 131860 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291106 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597736 # number of Writeback hits -system.l2c.Writeback_hits::total 597736 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.012124 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012307 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000150 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.026406 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.025316 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.769201 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3043 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6074 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55872 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000168 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17759906 # Number of tag accesses +system.l2c.tags.data_accesses 17759906 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8189 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2843 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 435869 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 178927 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2011 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 887 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 119100 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 59229 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 19905 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 6074 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 331991 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 135602 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1300627 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597941 # number of Writeback hits +system.l2c.Writeback_hits::total 597941 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 9 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 12 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61703 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18647 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33305 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113655 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8753 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3188 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 465928 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 238574 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2616 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1178 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 130375 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 83088 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18901 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4190 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 282805 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 165165 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404761 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8753 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3188 # number of overall hits -system.l2c.overall_hits::cpu0.inst 465928 # number of overall hits -system.l2c.overall_hits::cpu0.data 238574 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2616 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1178 # number of overall hits -system.l2c.overall_hits::cpu1.inst 130375 # number of overall hits -system.l2c.overall_hits::cpu1.data 83088 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18901 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4190 # number of overall hits -system.l2c.overall_hits::cpu2.inst 282805 # number of overall hits -system.l2c.overall_hits::cpu2.data 165165 # number of overall hits -system.l2c.overall_hits::total 1404761 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 27 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 52345 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 17186 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 43999 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113530 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8189 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2843 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 435869 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 231272 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2011 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 887 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 119100 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 76415 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 19905 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 6074 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 331991 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 179601 # number of demand (read+write) hits +system.l2c.demand_hits::total 1414157 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8189 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2843 # number of overall hits +system.l2c.overall_hits::cpu0.inst 435869 # number of overall hits +system.l2c.overall_hits::cpu0.data 231272 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2011 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 887 # number of overall hits +system.l2c.overall_hits::cpu1.inst 119100 # number of overall hits +system.l2c.overall_hits::cpu1.data 76415 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 19905 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 6074 # number of overall hits +system.l2c.overall_hits::cpu2.inst 331991 # number of overall hits +system.l2c.overall_hits::cpu2.data 179601 # number of overall hits +system.l2c.overall_hits::total 1414157 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7567 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6458 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7290 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6276 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1016 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1126 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2945 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2552 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21680 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1411 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu1.inst 1180 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1222 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 11 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2947 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2622 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21552 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1087 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 481 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 1014 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2906 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 104401 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9756 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 19200 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133357 # number of ReadExReq misses +system.l2c.UpgradeReq_misses::cpu2.data 1336 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 101003 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 11529 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 20863 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133395 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7567 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 110859 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7290 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 107279 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1016 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10882 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2945 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 21752 # number of demand (read+write) misses -system.l2c.demand_misses::total 155037 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1180 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12751 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 11 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2947 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 23485 # number of demand (read+write) misses +system.l2c.demand_misses::total 154947 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7567 # number of overall misses -system.l2c.overall_misses::cpu0.data 110859 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7290 # number of overall misses +system.l2c.overall_misses::cpu0.data 107279 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1016 # number of overall misses -system.l2c.overall_misses::cpu1.data 10882 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2945 # number of overall misses -system.l2c.overall_misses::cpu2.data 21752 # number of overall misses -system.l2c.overall_misses::total 155037 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1180 # number of overall misses +system.l2c.overall_misses::cpu1.data 12751 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 11 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2947 # number of overall misses +system.l2c.overall_misses::cpu2.data 23485 # number of overall misses +system.l2c.overall_misses::total 154947 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 71823500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 85564250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 881750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 224313750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 195090250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 577748000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 93996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 139494 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 233490 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 706910231 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1411869896 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2118780127 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 84908250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 91869750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 850000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 219075000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 202750495 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 599527995 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 46998 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 162493 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 209491 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 821599498 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1528087699 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2349687197 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 71823500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 792474481 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 881750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 224313750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1606960146 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2696528127 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 84908250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 913469248 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 850000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 219075000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1730838194 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2949215192 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 71823500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 792474481 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 881750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 224313750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1606960146 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2696528127 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8754 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3190 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 473495 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 183329 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2617 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1178 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 131391 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 65567 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 18913 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 4190 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 285750 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 134412 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1312786 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597736 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597736 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1425 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 84908250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 913469248 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 850000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 219075000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1730838194 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2949215192 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8190 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2845 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 443159 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 185203 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2012 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 887 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 120280 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 60451 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 19916 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 6074 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 334938 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 138224 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1322179 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597941 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597941 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1096 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 485 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1026 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2936 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166104 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 28403 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 52505 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247012 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8754 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3190 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 473495 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 349433 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2617 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1178 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 131391 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 93970 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 18913 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 4190 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 285750 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 186917 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1559798 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8754 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3190 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 473495 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 349433 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2617 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1178 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 131391 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 93970 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 18913 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 4190 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 285750 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 186917 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1559798 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000627 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015981 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.035226 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000382 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007733 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.017173 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000634 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.010306 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.018986 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016514 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990175 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_accesses::cpu2.data 1350 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2931 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 153348 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28715 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 64862 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246925 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8190 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2845 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 443159 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 338551 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2012 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 887 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 120280 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 89166 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 19916 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 6074 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 334938 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 203086 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1569104 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8190 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2845 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 443159 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 338551 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2012 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 887 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 120280 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 89166 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 19916 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 6074 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 334938 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 203086 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1569104 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000122 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000703 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016450 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.033887 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000497 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009810 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.020215 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000552 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.008799 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.018969 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016300 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991788 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991753 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.988304 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989782 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.628528 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.343485 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.365679 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539881 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000627 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015981 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.317254 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000382 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007733 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.115803 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000634 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.010306 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.116373 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.099396 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000627 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015981 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.317254 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000382 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007733 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.115803 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000634 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.010306 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.116373 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.099396 # miss rate for overall accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.989630 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.990788 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.658652 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.401497 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.321652 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.540225 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000122 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000703 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016450 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.316877 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000497 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009810 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.143003 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000552 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.008799 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.115641 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098749 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000122 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000703 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016450 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.316877 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000497 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009810 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.143003 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000552 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.008799 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.115641 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098749 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70692.421260 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75989.564831 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 73479.166667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76167.657046 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 76446.022727 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 26648.892989 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 195.417879 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 137.568047 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 80.347557 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72459.023268 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73534.890417 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 15888.030827 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71956.144068 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 75179.828151 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 77272.727273 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 74338.310146 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 77326.657132 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 27817.742901 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 97.708940 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 121.626497 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 72.138774 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71263.726082 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73243.910224 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 17614.507268 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 70692.421260 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 72824.341206 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 73479.166667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 76167.657046 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 73876.431868 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 17392.803827 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 71956.144068 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71639.028155 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 77272.727273 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 74338.310146 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 73699.731488 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 19033.703086 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 70692.421260 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 72824.341206 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 73479.166667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 76167.657046 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 73876.431868 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 17392.803827 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 71956.144068 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71639.028155 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 77272.727273 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 74338.310146 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 73699.731488 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 19033.703086 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -656,134 +658,134 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58519 # number of writebacks -system.l2c.writebacks::total 58519 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits +system.l2c.writebacks::writebacks 58458 # number of writebacks +system.l2c.writebacks::total 58458 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.data 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1016 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1126 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 12 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1180 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1222 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 11 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.inst 2944 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2541 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7640 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2614 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7972 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 481 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 1014 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1495 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9756 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 19200 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 28956 # number of ReadExReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 1336 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1817 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 11529 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 20863 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 32392 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1016 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10882 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 12 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1180 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 12751 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 11 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.inst 2944 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 21741 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 36596 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 23477 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40364 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1016 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10882 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 12 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1180 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 12751 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 11 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.inst 2944 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 21741 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 36596 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 23477 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40364 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 58931500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 71567750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 736250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 187351500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 162682500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 481332000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 69967750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 76634250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 715000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 182019500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 169748495 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 499147495 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4810481 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10143513 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14953994 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 583452269 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1173703604 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1757155873 # number of ReadExReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 13374835 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 18185316 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 675391502 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1269014301 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1944405803 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 58931500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 655020019 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 736250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 187351500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1336386104 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 2238487873 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 69967750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 752025752 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 715000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 182019500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1438762796 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2443553298 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 58931500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 655020019 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 736250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 187351500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1336386104 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 2238487873 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25035167000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26291907500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 51327074500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 936937545 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8534582000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9471519545 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25972104545 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34826489500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 60798594045 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007733 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017173 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000634 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010303 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018905 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.005820 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 69967750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 752025752 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 715000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 182019500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1438762796 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2443553298 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25042687500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 25560602500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 50603290000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 991271590 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9138698000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 10129969590 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26033959090 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34699300500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60733259590 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009810 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020215 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000552 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.008790 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018911 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006029 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991753 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.988304 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.509196 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.343485 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365679 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.117225 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007733 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.115803 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000634 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010303 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.116314 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023462 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007733 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.115803 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000634 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010303 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.116314 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023462 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.989630 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.619925 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.401497 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.321652 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.131182 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000497 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009810 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.143003 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000552 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.008790 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.115601 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.025724 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000497 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009810 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.143003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000552 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.008790 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.115601 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.025724 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63559.280639 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64023.022432 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63001.570681 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59294.703390 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62712.152209 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 65000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 61827.275815 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64938.215379 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62612.580908 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10003.464497 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.671572 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59804.455617 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61130.396042 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60683.653578 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10011.104042 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.429279 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58581.967387 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60826.070124 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60027.346351 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60192.980978 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61468.474495 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61167.555826 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59294.703390 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58977.786213 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 65000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 61827.275815 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61283.928781 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60537.937221 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60192.980978 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61468.474495 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61167.555826 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59294.703390 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58977.786213 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 65000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 61827.275815 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61283.928781 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60537.937221 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -800,52 +802,51 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58812389 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1022771 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1022770 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432242 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432242 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265826 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1511 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80908 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80908 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 834992 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2422460 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15408 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3325616 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26696960 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37444261 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64248813 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141273763 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 102976 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2181217728 # Layer occupancy (ticks) +system.toL2Bus.throughput 59108244 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1059674 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1059674 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 471057 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 471057 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 275568 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1835 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1835 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 93577 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 93577 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 911138 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2522746 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20145 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55378 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3509407 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29133952 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 38939733 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27844 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 68189241 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141801951 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 115908 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2288858155 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1881226404 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2052757055 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1849082178 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1915102818 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10054967 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13212439 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31351984 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 33686507 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48758810 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13772718 # Transaction distribution -system.iobus.trans_dist::ReadResp 13772718 # Transaction distribution -system.iobus.trans_dist::WriteReq 2835 # Transaction distribution -system.iobus.trans_dist::WriteResp 2835 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11646 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3040 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48817267 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13767391 # Transaction distribution +system.iobus.trans_dist::ReadResp 13767391 # Transaction distribution +system.iobus.trans_dist::WriteReq 2985 # Transaction distribution +system.iobus.trans_dist::WriteResp 2985 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 12256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 288 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 717678 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 706746 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -861,18 +862,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 732930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26818176 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26818176 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27551106 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 722736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26818016 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26818016 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27540752 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 16027 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 576 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 714003 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 703222 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -888,18 +889,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 736825 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107272704 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107272704 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108009529 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209343 # Total data (bytes) -system.iobus.reqLayer0.occupancy 8145000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 726717 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107272064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107272064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 107998781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209403 # Total data (bytes) +system.iobus.reqLayer0.occupancy 8657000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1520000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1570000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 144000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -907,7 +908,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 359342000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 353820000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -939,11 +940,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13409088000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13409008000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 730095000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 719751000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33780437750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33775984250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -968,25 +969,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7992228 # DTB read hits -system.cpu0.dtb.read_misses 6211 # DTB read misses -system.cpu0.dtb.write_hits 6585208 # DTB write hits -system.cpu0.dtb.write_misses 1983 # DTB write misses -system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 6543805 # DTB read hits +system.cpu0.dtb.read_misses 5435 # DTB read misses +system.cpu0.dtb.write_hits 6063639 # DTB write hits +system.cpu0.dtb.write_misses 1808 # DTB write misses +system.cpu0.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5702 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 493 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 23 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5223 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 117 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 107 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7998439 # DTB read accesses -system.cpu0.dtb.write_accesses 6587191 # DTB write accesses +system.cpu0.dtb.perms_faults 162 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6549240 # DTB read accesses +system.cpu0.dtb.write_accesses 6065447 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14577436 # DTB hits -system.cpu0.dtb.misses 8194 # DTB misses -system.cpu0.dtb.accesses 14585630 # DTB accesses +system.cpu0.dtb.hits 12607444 # DTB hits +system.cpu0.dtb.misses 7243 # DTB misses +system.cpu0.dtb.accesses 12614687 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1008,468 +1009,486 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32348466 # ITB inst hits -system.cpu0.itb.inst_misses 3468 # ITB inst misses +system.cpu0.itb.inst_hits 30119411 # ITB inst hits +system.cpu0.itb.inst_misses 2986 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2648 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 493 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 23 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2362 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32351934 # ITB inst accesses -system.cpu0.itb.hits 32348466 # DTB hits -system.cpu0.itb.misses 3468 # DTB misses -system.cpu0.itb.accesses 32351934 # DTB accesses -system.cpu0.numCycles 113676157 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30122397 # ITB inst accesses +system.cpu0.itb.hits 30119411 # DTB hits +system.cpu0.itb.misses 2986 # DTB misses +system.cpu0.itb.accesses 30122397 # DTB accesses +system.cpu0.numCycles 109377986 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31863567 # Number of instructions committed -system.cpu0.committedOps 42010857 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37388293 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses -system.cpu0.num_func_calls 1197302 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4248978 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37388293 # number of integer instructions -system.cpu0.num_fp_insts 5018 # number of float instructions -system.cpu0.num_int_register_reads 193803982 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39520708 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written -system.cpu0.num_mem_refs 15242780 # number of memory refs -system.cpu0.num_load_insts 8359522 # Number of load instructions -system.cpu0.num_store_insts 6883258 # Number of store instructions -system.cpu0.num_idle_cycles 110978931.176812 # Number of idle cycles -system.cpu0.num_busy_cycles 2697225.823188 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023727 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976273 # Percentage of idle cycles -system.cpu0.Branches 5616963 # Number of branches fetched -system.cpu0.op_class::No_OpClass 14526 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 26777156 63.63% 63.66% # Class of executed instruction -system.cpu0.op_class::IntMult 49712 0.12% 63.78% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1435 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::MemRead 8359522 19.86% 83.64% # Class of executed instruction -system.cpu0.op_class::MemWrite 6883258 16.36% 100.00% # Class of executed instruction +system.cpu0.committedInsts 29708958 # Number of instructions committed +system.cpu0.committedOps 36436691 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 32091710 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4289 # Number of float alu accesses +system.cpu0.num_func_calls 1119227 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3806697 # number of instructions that are conditional controls +system.cpu0.num_int_insts 32091710 # number of integer instructions +system.cpu0.num_fp_insts 4289 # number of float instructions +system.cpu0.num_int_register_reads 59433720 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21150393 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3327 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 964 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 109113758 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 14198144 # number of times the CC registers were written +system.cpu0.num_mem_refs 13068134 # number of memory refs +system.cpu0.num_load_insts 6718957 # Number of load instructions +system.cpu0.num_store_insts 6349177 # Number of store instructions +system.cpu0.num_idle_cycles 107075141.411044 # Number of idle cycles +system.cpu0.num_busy_cycles 2302844.588956 # Number of busy cycles +system.cpu0.not_idle_fraction 0.021054 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.978946 # Percentage of idle cycles +system.cpu0.Branches 5297571 # Number of branches fetched +system.cpu0.op_class::No_OpClass 11842 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 23375924 64.04% 64.07% # Class of executed instruction +system.cpu0.op_class::IntMult 45526 0.12% 64.20% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1430 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::MemRead 6718957 18.41% 82.61% # Class of executed instruction +system.cpu0.op_class::MemWrite 6349177 17.39% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 42085609 # Class of executed instruction +system.cpu0.op_class::total 36502856 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891568 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.602608 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43675041 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 892080 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.958660 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8174940250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.966915 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.710732 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.924961 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964779 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.015060 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019385 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 82922 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 899179 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.616650 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41225487 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 899691 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 45.821829 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7765042250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.273634 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.912581 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.430435 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967331 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.011548 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020372 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999251 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45483451 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45483451 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31876897 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8043794 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3754350 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43675041 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31876897 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8043794 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3754350 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43675041 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31876897 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8043794 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3754350 # number of overall hits -system.cpu0.icache.overall_hits::total 43675041 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 474237 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 131660 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 310425 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916322 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 474237 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 131660 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 310425 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916322 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 474237 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 131660 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 310425 # number of overall misses -system.cpu0.icache.overall_misses::total 916322 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1777118000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4193284063 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5970402063 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1777118000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4193284063 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5970402063 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1777118000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4193284063 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5970402063 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32351134 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8175454 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4064775 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44591363 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32351134 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8175454 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4064775 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44591363 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32351134 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8175454 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4064775 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44591363 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014659 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016104 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076370 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020549 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014659 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016104 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076370 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020549 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014659 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016104 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076370 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020549 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13497.782166 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13508.203473 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6515.615758 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13497.782166 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13508.203473 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6515.615758 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13497.782166 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13508.203473 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6515.615758 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3442 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43052663 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43052663 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29678002 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7860593 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3686892 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41225487 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29678002 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7860593 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3686892 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41225487 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29678002 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7860593 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3686892 # number of overall hits +system.cpu0.icache.overall_hits::total 41225487 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 443773 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 120537 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 363173 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 927483 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 443773 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 120537 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 363173 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 927483 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 443773 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 120537 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 363173 # number of overall misses +system.cpu0.icache.overall_misses::total 927483 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1643390750 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4873068412 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6516459162 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1643390750 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4873068412 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6516459162 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1643390750 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4873068412 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6516459162 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30121775 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7981130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4050065 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 42152970 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30121775 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7981130 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4050065 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 42152970 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30121775 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7981130 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4050065 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42152970 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014733 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015103 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.089671 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022003 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014733 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015103 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089671 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022003 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014733 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015103 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089671 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.022003 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13633.911164 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13418.036065 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7025.960758 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13633.911164 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13418.036065 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7025.960758 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13633.911164 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13418.036065 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7025.960758 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3564 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 244 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.106557 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.423963 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24233 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 24233 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 24233 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 24233 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 24233 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 24233 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 131660 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 286192 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 417852 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 131660 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 286192 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 417852 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 131660 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 286192 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 417852 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1513402000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3408270326 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4921672326 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1513402000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3408270326 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4921672326 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1513402000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3408270326 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4921672326 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016104 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070408 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009371 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016104 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070408 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009371 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016104 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070408 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009371 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11494.774419 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11909.034236 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11778.506088 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11494.774419 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11909.034236 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11778.506088 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11494.774419 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11909.034236 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11778.506088 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 27790 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 27790 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 27790 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 27790 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 27790 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 27790 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 120537 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 335383 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 455920 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 120537 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 335383 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 455920 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 120537 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 335383 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 455920 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1401871250 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3957248170 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5359119420 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1401871250 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3957248170 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5359119420 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1401871250 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3957248170 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5359119420 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015103 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.082809 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010816 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015103 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.082809 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010816 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015103 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.082809 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010816 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11630.215204 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11799.191283 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11754.517064 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11630.215204 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11799.191283 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11754.517064 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11630.215204 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11799.191283 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11754.517064 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 629808 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997118 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23216736 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630320 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 36.833253 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.011918 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.087644 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.897556 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970726 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015796 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013472 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 630291 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997117 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21342473 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 630803 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.833817 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.608321 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 7.871908 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.516888 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971891 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015375 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012728 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 98838984 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 98838984 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6862400 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1819912 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4640111 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13322423 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5954558 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1318615 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2132591 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9405764 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131484 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33204 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73477 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238165 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137939 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34940 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74507 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247386 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12816958 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3138527 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6772702 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22728187 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12816958 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3138527 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6772702 # number of overall hits -system.cpu0.dcache.overall_hits::total 22728187 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 176874 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 63831 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 275088 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 515793 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167529 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 28888 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 614266 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 810683 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6455 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1736 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3758 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11949 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 344403 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 92719 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 889354 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326476 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 344403 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 92719 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 889354 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326476 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 908477250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3946035800 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4854513050 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 993858250 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 22101160686 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 23095018936 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22777000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 50452248 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 73229248 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1902335500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 26047196486 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 27949531986 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1902335500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 26047196486 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 27949531986 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7039274 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1883743 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4915199 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13838216 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6122087 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1347503 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2746857 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216447 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137939 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34940 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77235 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250114 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137939 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34940 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74510 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247389 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13161361 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3231246 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7662056 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24054663 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13161361 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3231246 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7662056 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24054663 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025127 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033885 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055967 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037273 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027365 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021438 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.223625 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.079351 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046796 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049685 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048657 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047774 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000040 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026168 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028695 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116073 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.055144 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026168 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028695 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.116073 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.055144 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14232.539832 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14344.630809 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9411.746670 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34403.844157 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 35979.788375 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 28488.347401 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13120.391705 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13425.292177 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6128.483388 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20517.213300 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 29287.771220 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21070.514646 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20517.213300 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 29287.771220 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21070.514646 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7838 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2641 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 847 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 52 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.253837 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 50.788462 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 92219903 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 92219903 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5361652 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1457794 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4730320 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11549766 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5493900 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1274863 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2443484 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9212247 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 53400 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 14515 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 23676 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 91591 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 122744 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 31335 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 84381 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238460 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 128815 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 32780 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 85814 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247409 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10855552 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 2732657 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 7173804 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 20762013 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10908952 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 2747172 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 7197480 # number of overall hits +system.cpu0.dcache.overall_hits::total 20853604 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 142161 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 45809 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 256649 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 444619 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 154444 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 29861 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 820607 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1004912 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 36971 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 17584 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 41738 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 96293 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6071 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1446 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 4461 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11978 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 296605 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 75670 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1077256 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1449531 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 333576 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 93254 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1118994 # number of overall misses +system.cpu0.dcache.overall_misses::total 1545824 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 618572999 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3601097882 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4219670881 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1127965983 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 26744225136 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 27872191119 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 19459500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 65741241 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 85200741 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1746538982 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 30345323018 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 32091862000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1746538982 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 30345323018 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 32091862000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5503813 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1503603 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4986969 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 11994385 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5648344 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1304724 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3264091 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10217159 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 90371 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 32099 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 65414 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 187884 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 128815 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 32781 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 88842 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250438 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 128815 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 32780 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 85814 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247409 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11152157 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2808327 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 8251060 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 22211544 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11242528 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2840426 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 8316474 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 22399428 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025830 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030466 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.051464 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037069 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027343 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.022887 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.251404 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.098355 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.409102 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.547805 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.638059 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.512513 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047130 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044111 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050213 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047828 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026596 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026945 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.130560 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.065260 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029671 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032831 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.134551 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.069012 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13503.307189 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14031.217273 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9490.532076 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37773.885101 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32590.783574 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 27735.952122 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13457.468880 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14736.884331 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7113.102438 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23080.996194 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28169.091672 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22139.479597 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18728.837176 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27118.396540 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 20760.359523 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 38637 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 6212 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 5775 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 192 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6.690390 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 32.354167 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597736 # number of writebacks -system.cpu0.dcache.writebacks::total 597736 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 143982 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 143982 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 560780 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 560780 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 407 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 407 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 704762 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 704762 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 704762 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 704762 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63831 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131106 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 194937 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28888 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53486 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82374 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1736 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3351 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5087 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 92719 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 184592 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 277311 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 92719 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 184592 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 277311 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 780623750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1700229865 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2480853615 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 933509750 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1853484745 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2786994495 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19304000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38850752 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58154752 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714133500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3553714610 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5267848110 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714133500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3553714610 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5267848110 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27350994000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28703901500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56054895500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1444132955 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13356723550 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14800856505 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28795126955 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42060625050 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70855752005 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033885 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026674 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021438 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019472 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008063 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049685 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043387 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020339 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028695 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011528 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028695 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011528 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12229.539722 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12968.360449 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.437849 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32314.793340 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34653.642916 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33833.424321 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.815668 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11593.778574 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11432.033025 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597941 # number of writebacks +system.cpu0.dcache.writebacks::total 597941 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 82 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146159 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 146241 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 661 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 754425 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 755086 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 467 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 467 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 743 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 900584 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 901327 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 743 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 900584 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 901327 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 45727 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 110490 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 156217 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29200 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 66182 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 95382 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 13278 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 23770 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 37048 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1446 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3994 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5440 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 74927 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 176672 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 251599 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 88205 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 200442 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 288647 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 526256000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1348662754 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1874918754 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1036082517 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2113089467 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3149171984 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 204786500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 440091753 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 644878253 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 16565500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 51817259 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68382759 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1562338517 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3461752221 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5024090738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1767125017 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3901843974 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5668968991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27358748000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 27904372000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55263120000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1501669410 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14569249955 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 16070919365 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28860417410 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42473621955 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71334039365 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030412 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.022156 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013024 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.022380 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.020276 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009335 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.413658 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.363378 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.197185 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044111 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044956 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.021722 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026680 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.021412 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011327 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031053 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024102 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.012886 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11508.649157 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12206.197430 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12002.014851 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35482.277979 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31928.461923 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33016.418024 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.992921 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18514.587842 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17406.560489 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11456.085754 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12973.775413 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12570.360110 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20851.475663 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19594.232368 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19968.643508 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20034.295301 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19466.199569 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19639.798754 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1503,25 +1522,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2096820 # DTB read hits -system.cpu1.dtb.read_misses 2107 # DTB read misses -system.cpu1.dtb.write_hits 1423125 # DTB write hits -system.cpu1.dtb.write_misses 370 # DTB write misses -system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 1746639 # DTB read hits +system.cpu1.dtb.read_misses 1917 # DTB read misses +system.cpu1.dtb.write_hits 1378449 # DTB write hits +system.cpu1.dtb.write_misses 367 # DTB write misses +system.cpu1.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1777 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 251 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 10 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1626 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 33 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2098927 # DTB read accesses -system.cpu1.dtb.write_accesses 1423495 # DTB write accesses +system.cpu1.dtb.perms_faults 77 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 1748556 # DTB read accesses +system.cpu1.dtb.write_accesses 1378816 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3519945 # DTB hits -system.cpu1.dtb.misses 2477 # DTB misses -system.cpu1.dtb.accesses 3522422 # DTB accesses +system.cpu1.dtb.hits 3125088 # DTB hits +system.cpu1.dtb.misses 2284 # DTB misses +system.cpu1.dtb.accesses 3127372 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1543,96 +1562,98 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8175454 # ITB inst hits -system.cpu1.itb.inst_misses 1196 # ITB inst misses +system.cpu1.itb.inst_hits 7981130 # ITB inst hits +system.cpu1.itb.inst_misses 1058 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 554 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 946 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 251 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 10 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 834 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8176650 # ITB inst accesses -system.cpu1.itb.hits 8175454 # DTB hits -system.cpu1.itb.misses 1196 # DTB misses -system.cpu1.itb.accesses 8176650 # DTB accesses -system.cpu1.numCycles 584791217 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7982188 # ITB inst accesses +system.cpu1.itb.hits 7981130 # DTB hits +system.cpu1.itb.misses 1058 # DTB misses +system.cpu1.itb.accesses 7982188 # DTB accesses +system.cpu1.numCycles 582833153 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7972563 # Number of instructions committed -system.cpu1.committedOps 10134873 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9111769 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2002 # Number of float alu accesses -system.cpu1.num_func_calls 305506 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1114419 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9111769 # number of integer instructions -system.cpu1.num_fp_insts 2002 # number of float instructions -system.cpu1.num_int_register_reads 53111503 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9891567 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1488 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_mem_refs 3688880 # number of memory refs -system.cpu1.num_load_insts 2190803 # Number of load instructions -system.cpu1.num_store_insts 1498077 # Number of store instructions -system.cpu1.num_idle_cycles 549443201.253140 # Number of idle cycles -system.cpu1.num_busy_cycles 35348015.746859 # Number of busy cycles -system.cpu1.not_idle_fraction 0.060446 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.939554 # Percentage of idle cycles -system.cpu1.Branches 1447411 # Number of branches fetched -system.cpu1.op_class::No_OpClass 5397 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 6618001 64.10% 64.15% # Class of executed instruction -system.cpu1.op_class::IntMult 11557 0.11% 64.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::MemRead 2190803 21.22% 85.49% # Class of executed instruction -system.cpu1.op_class::MemWrite 1498077 14.51% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7797141 # Number of instructions committed +system.cpu1.committedOps 9191219 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 8219243 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1689 # Number of float alu accesses +system.cpu1.num_func_calls 289029 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 993030 # number of instructions that are conditional controls +system.cpu1.num_int_insts 8219243 # number of integer instructions +system.cpu1.num_fp_insts 1689 # number of float instructions +system.cpu1.num_int_register_reads 14554839 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5500250 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1177 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 512 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 33218155 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 3793046 # number of times the CC registers were written +system.cpu1.num_mem_refs 3251661 # number of memory refs +system.cpu1.num_load_insts 1804549 # Number of load instructions +system.cpu1.num_store_insts 1447112 # Number of store instructions +system.cpu1.num_idle_cycles 548698663.963538 # Number of idle cycles +system.cpu1.num_busy_cycles 34134489.036462 # Number of busy cycles +system.cpu1.not_idle_fraction 0.058566 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.941434 # Percentage of idle cycles +system.cpu1.Branches 1360376 # Number of branches fetched +system.cpu1.op_class::No_OpClass 4595 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 6078995 65.05% 65.10% # Class of executed instruction +system.cpu1.op_class::IntMult 10163 0.11% 65.20% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 281 0.00% 65.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.21% # Class of executed instruction +system.cpu1.op_class::MemRead 1804549 19.31% 84.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 1447112 15.48% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 10324133 # Class of executed instruction +system.cpu1.op_class::total 9345695 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4844951 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3958364 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223288 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3209464 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2561917 # Number of BTB hits +system.cpu2.branchPred.lookups 5844133 # Number of BP lookups +system.cpu2.branchPred.condPredicted 4389690 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 248799 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3701982 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2861782 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.823827 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 415777 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21493 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 77.304050 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 588875 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15609 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1656,25 +1677,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10946099 # DTB read hits -system.cpu2.dtb.read_misses 23259 # DTB read misses -system.cpu2.dtb.write_hits 3358425 # DTB write hits -system.cpu2.dtb.write_misses 6569 # DTB write misses -system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 13926534 # DTB read hits +system.cpu2.dtb.read_misses 28241 # DTB read misses +system.cpu2.dtb.write_hits 3979346 # DTB write hits +system.cpu2.dtb.write_misses 9743 # DTB write misses +system.cpu2.dtb.flush_tlb 550 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2341 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 761 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 169 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 2739 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 445 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 255 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 490 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10969358 # DTB read accesses -system.cpu2.dtb.write_accesses 3364994 # DTB write accesses +system.cpu2.dtb.perms_faults 656 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 13954775 # DTB read accesses +system.cpu2.dtb.write_accesses 3989089 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14304524 # DTB hits -system.cpu2.dtb.misses 29828 # DTB misses -system.cpu2.dtb.accesses 14334352 # DTB accesses +system.cpu2.dtb.hits 17905880 # DTB hits +system.cpu2.dtb.misses 37984 # DTB misses +system.cpu2.dtb.accesses 17943864 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1696,329 +1717,329 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4066170 # ITB inst hits -system.cpu2.itb.inst_misses 4558 # ITB inst misses +system.cpu2.itb.inst_hits 4053038 # ITB inst hits +system.cpu2.itb.inst_misses 6578 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 550 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1650 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 2058 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 2441 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4070728 # ITB inst accesses -system.cpu2.itb.hits 4066170 # DTB hits -system.cpu2.itb.misses 4558 # DTB misses -system.cpu2.itb.accesses 4070728 # DTB accesses -system.cpu2.numCycles 88357644 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4059616 # ITB inst accesses +system.cpu2.itb.hits 4053038 # DTB hits +system.cpu2.itb.misses 6578 # DTB misses +system.cpu2.itb.accesses 4059616 # DTB accesses +system.cpu2.numCycles 88208146 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9387256 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32765333 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4844951 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2977694 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6914165 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1793026 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51157 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18399919 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 356 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 937 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 34522 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 732881 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4064781 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 291170 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36763653 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.071353 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.456601 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10487397 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32911643 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 5844133 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 3450657 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 74966701 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 679472 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 80302 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 630 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 972 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 72243 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 1263867 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 410 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4050067 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 153217 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2804 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 87212188 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 0.443226 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 1.629212 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 29854695 81.21% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 388351 1.06% 82.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 517738 1.41% 83.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 822514 2.24% 85.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 639820 1.74% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 344469 0.94% 88.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1061447 2.89% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 231777 0.63% 92.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2902842 7.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 79899565 91.62% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 625094 0.72% 92.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 698013 0.80% 93.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 764181 0.88% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 868461 1.00% 95.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 574503 0.66% 95.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 981504 1.13% 96.79% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 301305 0.35% 97.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2499562 2.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36763653 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.054833 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.370826 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9873812 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19124591 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6319657 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 254865 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1189808 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 613364 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53448 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 37275302 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 179889 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1189808 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10379118 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2802247 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11780210 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6098002 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 4513356 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35160533 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 386 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2869122 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 3154793 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 689173 # Number of times rename has blocked due to SQ full -system.cpu2.rename.FullRegisterEvents 383 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37744497 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 162187083 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 149521715 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3412 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26544575 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11199921 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 286052 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 262435 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 2598030 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6687505 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3927813 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 542106 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 758032 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32441943 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511673 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34839204 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 63540 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7431415 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19915523 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 154345 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36763653 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.947653 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.617979 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 87212188 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.066254 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.373113 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8569138 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 72587758 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 4831209 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 941079 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 281926 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 736866 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 58789 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34844703 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 196626 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 281926 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9031224 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 19204705 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13140033 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5253439 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 40299841 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33794581 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 74120 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 29618551 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 37683898 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1100267 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 36626919 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 154339316 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41664821 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4127 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 28795876 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 7831027 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 344066 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 286541 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 5082070 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6089915 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 4400227 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 719431 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1142118 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32029170 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 669683 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 38616590 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 44993 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 5567256 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12099893 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 238978 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 87212188 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.442789 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.239118 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24294475 66.08% 66.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3786923 10.30% 76.38% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2217252 6.03% 82.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1918473 5.22% 87.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2844306 7.74% 95.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 967223 2.63% 98.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 535277 1.46% 99.46% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 160435 0.44% 99.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 39289 0.11% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73763195 84.58% 84.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 4095516 4.70% 89.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2328743 2.67% 91.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2051674 2.35% 94.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2976748 3.41% 97.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 798764 0.92% 98.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 739781 0.85% 99.48% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 293068 0.34% 99.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 164699 0.19% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36763653 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 87212188 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19487 1.25% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1415927 90.74% 91.99% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 124952 8.01% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 122993 5.40% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1970586 86.46% 91.85% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 185678 8.15% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 8595 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19842102 56.95% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28105 0.08% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 10 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11432468 32.81% 89.87% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3527522 10.13% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 12081 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 20207276 52.33% 52.36% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 34218 0.09% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 404 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 14176555 36.71% 89.16% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 4186056 10.84% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34839204 # Type of FU issued -system.cpu2.iq.rate 0.394298 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1560367 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044788 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108088247 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 40390587 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28132113 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7428 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3949 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3288 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36387010 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3966 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 216264 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 38616590 # Type of FU issued +system.cpu2.iq.rate 0.437789 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2279258 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.059023 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 166760031 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 38278238 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29588244 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9588 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 5150 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4304 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 40878658 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5109 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 176007 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1592400 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1668 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9845 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 582754 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1107424 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2018 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 18033 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 469449 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5289504 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 343573 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5207867 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 3518142 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1189808 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2192287 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 292580 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 33037931 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 55534 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6687505 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3927813 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 368987 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 60475 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 207427 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9845 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107337 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89487 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196824 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33922204 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11159492 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 281926 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 17856855 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 716566 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32817404 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 57776 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6089915 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 4400227 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 491578 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 63121 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 616282 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 18033 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 121106 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 106258 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 227364 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 38297957 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 14051286 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 280797 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 84315 # number of nop insts executed -system.cpu2.iew.exec_refs 14652861 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3774133 # Number of branches executed -system.cpu2.iew.exec_stores 3493369 # Number of stores executed -system.cpu2.iew.exec_rate 0.383919 # Inst execution rate -system.cpu2.iew.wb_sent 33519345 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28135401 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16326972 # num instructions producing a value -system.cpu2.iew.wb_consumers 29693548 # num instructions consuming a value +system.cpu2.iew.exec_nop 118551 # number of nop insts executed +system.cpu2.iew.exec_refs 18186993 # number of memory reference insts executed +system.cpu2.iew.exec_branches 4220297 # Number of branches executed +system.cpu2.iew.exec_stores 4135707 # Number of stores executed +system.cpu2.iew.exec_rate 0.434177 # Inst execution rate +system.cpu2.iew.wb_sent 34852514 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 29592548 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17266310 # num instructions producing a value +system.cpu2.iew.wb_consumers 30698955 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.318426 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549849 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.335485 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.562440 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7376982 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357328 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 170683 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35573653 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.713892 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.756913 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 5479640 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 430705 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 190919 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 86342246 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.312843 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.237203 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 26733174 75.15% 75.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4358118 12.25% 87.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1232607 3.46% 90.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 662996 1.86% 92.73% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 505200 1.42% 94.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 312825 0.88% 95.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 424269 1.19% 96.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 302810 0.85% 97.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1041654 2.93% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 77364915 89.60% 89.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4177735 4.84% 94.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1290086 1.49% 95.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 753837 0.87% 96.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 490440 0.57% 97.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 381562 0.44% 97.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 374801 0.43% 98.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 197147 0.23% 98.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1311723 1.52% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35573653 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20550287 # Number of instructions committed -system.cpu2.commit.committedOps 25395761 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 86342246 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 22875674 # Number of instructions committed +system.cpu2.commit.committedOps 27011607 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8440164 # Number of memory references committed -system.cpu2.commit.loads 5095105 # Number of loads committed -system.cpu2.commit.membars 94591 # Number of memory barriers committed -system.cpu2.commit.branches 3237542 # Number of branches committed -system.cpu2.commit.fp_insts 3235 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22655353 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295831 # Number of function calls committed. +system.cpu2.commit.refs 8913269 # Number of memory references committed +system.cpu2.commit.loads 4982491 # Number of loads committed +system.cpu2.commit.membars 117220 # Number of memory barriers committed +system.cpu2.commit.branches 3644555 # Number of branches committed +system.cpu2.commit.fp_insts 4270 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 23908542 # Number of committed integer instructions. +system.cpu2.commit.function_calls 341319 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 16928638 66.66% 66.66% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 26577 0.10% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 382 0.00% 66.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5095105 20.06% 86.83% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3345059 13.17% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 18065773 66.88% 66.88% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 32161 0.12% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 404 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 4982491 18.45% 85.45% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3930778 14.55% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 25395761 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1041654 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 27011607 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1311723 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66778885 # The number of ROB reads -system.cpu2.rob.rob_writes 66779605 # The number of ROB writes -system.cpu2.timesIdled 362907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51593991 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3545947336 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20495032 # Number of Instructions Simulated -system.cpu2.committedOps 25340506 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 4.311174 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.311174 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.231955 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.231955 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157422880 # number of integer regfile reads -system.cpu2.int_regfile_writes 29963931 # number of integer regfile writes -system.cpu2.fp_regfile_reads 46839 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45210 # number of floating regfile writes -system.cpu2.misc_regfile_reads 66597785 # number of misc regfile reads -system.cpu2.misc_regfile_writes 297300 # number of misc regfile writes +system.cpu2.rob.rob_reads 116854146 # The number of ROB reads +system.cpu2.rob.rob_writes 65855440 # The number of ROB writes +system.cpu2.timesIdled 179134 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 995958 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3544369510 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 22801865 # Number of Instructions Simulated +system.cpu2.committedOps 26937798 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 3.868462 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 3.868462 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.258501 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.258501 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 45014030 # number of integer regfile reads +system.cpu2.int_regfile_writes 19144459 # number of integer regfile writes +system.cpu2.fp_regfile_reads 47113 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45464 # number of floating regfile writes +system.cpu2.cc_regfile_reads 130800569 # number of cc regfile reads +system.cpu2.cc_regfile_writes 12559359 # number of cc regfile writes +system.cpu2.misc_regfile_reads 124603397 # number of misc regfile reads +system.cpu2.misc_regfile_writes 350092 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2035,10 +2056,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1536043103750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1536043103750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536004079250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1536004079250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536004079250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1536004079250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 4b7f3d43e..055919fe9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,154 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550237 # Number of seconds simulated -sim_ticks 2550237191000 # Number of ticks simulated -final_tick 2550237191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.539697 # Number of seconds simulated +sim_ticks 2539696838000 # Number of ticks simulated +final_tick 2539696838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66377 # Simulator instruction rate (inst/s) -host_op_rate 85409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2806608319 # Simulator tick rate (ticks/s) -host_mem_usage 421988 # Number of bytes of host memory used -host_seconds 908.65 # Real time elapsed on the host -sim_insts 60314055 # Number of instructions simulated -sim_ops 77607027 # Number of ops (including micro ops) simulated +host_inst_rate 33216 # Simulator instruction rate (inst/s) +host_op_rate 40018 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1398403355 # Simulator tick rate (ticks/s) +host_mem_usage 411672 # Number of bytes of host memory used +host_seconds 1816.14 # Real time elapsed on the host +sim_insts 60325607 # Number of instructions simulated +sim_ops 72677421 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 507520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5298200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 292352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3795584 # Number of bytes read from this memory -system.physmem.bytes_read::total 131007192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 507520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 292352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786240 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521400 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494672 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802312 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 469568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3933400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 314240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5155776 # Number of bytes read from this memory +system.physmem.bytes_read::total 130985112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 469568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 314240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 783808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3774400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1328880 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1687192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6790472 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 35 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7930 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 82820 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4568 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 59306 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59160 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380350 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373668 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47489907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 878 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 61485 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 80559 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293132 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58975 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 332220 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 421798 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812993 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47687002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 353 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 199009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2077532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 114637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1488326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51370591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 199009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 114637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596572 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586091 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47489907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 184891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1548768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 123731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2030075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51575097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 184891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 123731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 308623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1486162 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 523244 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 664328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2673733 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1486162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47687002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 353 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 199009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2674104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 114637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2074417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54037916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293487 # Number of read requests accepted -system.physmem.writeReqs 813178 # Number of write requests accepted -system.physmem.readBursts 15293487 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813178 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 977052352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1730816 # Total number of bytes read from write queue -system.physmem.bytesWritten 6829312 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131007192 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6802312 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 27044 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706441 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4687 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955866 # Per bank write bursts -system.physmem.perBankRdBursts::1 953274 # Per bank write bursts -system.physmem.perBankRdBursts::2 953247 # Per bank write bursts -system.physmem.perBankRdBursts::3 953514 # Per bank write bursts -system.physmem.perBankRdBursts::4 955750 # Per bank write bursts -system.physmem.perBankRdBursts::5 953800 # Per bank write bursts -system.physmem.perBankRdBursts::6 953588 # Per bank write bursts -system.physmem.perBankRdBursts::7 953504 # Per bank write bursts -system.physmem.perBankRdBursts::8 956261 # Per bank write bursts -system.physmem.perBankRdBursts::9 953859 # Per bank write bursts -system.physmem.perBankRdBursts::10 953506 # Per bank write bursts -system.physmem.perBankRdBursts::11 952990 # Per bank write bursts -system.physmem.perBankRdBursts::12 956201 # Per bank write bursts -system.physmem.perBankRdBursts::13 953861 # Per bank write bursts -system.physmem.perBankRdBursts::14 953718 # Per bank write bursts -system.physmem.perBankRdBursts::15 953504 # Per bank write bursts -system.physmem.perBankWrBursts::0 6593 # Per bank write bursts -system.physmem.perBankWrBursts::1 6395 # Per bank write bursts -system.physmem.perBankWrBursts::2 6535 # Per bank write bursts -system.physmem.perBankWrBursts::3 6562 # Per bank write bursts -system.physmem.perBankWrBursts::4 6485 # Per bank write bursts -system.physmem.perBankWrBursts::5 6754 # Per bank write bursts -system.physmem.perBankWrBursts::6 6752 # Per bank write bursts -system.physmem.perBankWrBursts::7 6692 # Per bank write bursts -system.physmem.perBankWrBursts::8 7013 # Per bank write bursts -system.physmem.perBankWrBursts::9 6813 # Per bank write bursts -system.physmem.perBankWrBursts::10 6467 # Per bank write bursts -system.physmem.perBankWrBursts::11 6119 # Per bank write bursts -system.physmem.perBankWrBursts::12 7057 # Per bank write bursts -system.physmem.perBankWrBursts::13 6685 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 184891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2072011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 123731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2694403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54248831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293132 # Number of read requests accepted +system.physmem.writeReqs 812993 # Number of write requests accepted +system.physmem.readBursts 15293132 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812993 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 975241856 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3518592 # Total number of bytes read from write queue +system.physmem.bytesWritten 6826496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130985112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6790472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 54978 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706304 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4635 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 954958 # Per bank write bursts +system.physmem.perBankRdBursts::1 950647 # Per bank write bursts +system.physmem.perBankRdBursts::2 950811 # Per bank write bursts +system.physmem.perBankRdBursts::3 950999 # Per bank write bursts +system.physmem.perBankRdBursts::4 954856 # Per bank write bursts +system.physmem.perBankRdBursts::5 951881 # Per bank write bursts +system.physmem.perBankRdBursts::6 951736 # Per bank write bursts +system.physmem.perBankRdBursts::7 951699 # Per bank write bursts +system.physmem.perBankRdBursts::8 955454 # Per bank write bursts +system.physmem.perBankRdBursts::9 951840 # Per bank write bursts +system.physmem.perBankRdBursts::10 951452 # Per bank write bursts +system.physmem.perBankRdBursts::11 951010 # Per bank write bursts +system.physmem.perBankRdBursts::12 955349 # Per bank write bursts +system.physmem.perBankRdBursts::13 951888 # Per bank write bursts +system.physmem.perBankRdBursts::14 952124 # Per bank write bursts +system.physmem.perBankRdBursts::15 951450 # Per bank write bursts +system.physmem.perBankWrBursts::0 6588 # Per bank write bursts +system.physmem.perBankWrBursts::1 6390 # Per bank write bursts +system.physmem.perBankWrBursts::2 6534 # Per bank write bursts +system.physmem.perBankWrBursts::3 6563 # Per bank write bursts +system.physmem.perBankWrBursts::4 6471 # Per bank write bursts +system.physmem.perBankWrBursts::5 6764 # Per bank write bursts +system.physmem.perBankWrBursts::6 6747 # Per bank write bursts +system.physmem.perBankWrBursts::7 6681 # Per bank write bursts +system.physmem.perBankWrBursts::8 6996 # Per bank write bursts +system.physmem.perBankWrBursts::9 6810 # Per bank write bursts +system.physmem.perBankWrBursts::10 6454 # Per bank write bursts +system.physmem.perBankWrBursts::11 6114 # Per bank write bursts +system.physmem.perBankWrBursts::12 7081 # Per bank write bursts +system.physmem.perBankWrBursts::13 6669 # Per bank write bursts system.physmem.perBankWrBursts::14 6965 # Per bank write bursts -system.physmem.perBankWrBursts::15 6821 # Per bank write bursts +system.physmem.perBankWrBursts::15 6837 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550236004000 # Total gap between requests +system.physmem.totGap 2539695718000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 38 # Read request sizes (log2) -system.physmem.readPktSize::3 15138816 # Read request sizes (log2) +system.physmem.readPktSize::2 18 # Read request sizes (log2) +system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154633 # Read request sizes (log2) +system.physmem.readPktSize::6 154288 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59160 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1068642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1003556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 964678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1068028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 971433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1034228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2693278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2602966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3400925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 102170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 95874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 92374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58975 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1062531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1005454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1062790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 969024 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1031345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2691523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2602840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3403260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 99295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 93778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 90278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 18929 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,43 +161,43 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 265 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -225,96 +225,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1011151 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.031391 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 908.214038 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 201.586844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22832 2.26% 2.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19987 1.98% 4.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8899 0.88% 5.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2276 0.23% 5.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2117 0.21% 5.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1805 0.18% 5.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9141 0.90% 6.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 764 0.08% 6.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943330 93.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1011151 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2512.992263 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 47101.457482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6047 99.54% 99.54% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.56% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 7 0.12% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1008721 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.577780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.477346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.561203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22290 2.21% 2.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20048 1.99% 4.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8821 0.87% 5.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2154 0.21% 5.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2027 0.20% 5.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1663 0.16% 5.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9185 0.91% 6.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 821 0.08% 6.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 941712 93.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1008721 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2509.988470 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47472.970867 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6043 99.54% 99.54% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 3 0.05% 99.59% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 5 0.08% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 2 0.03% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.84% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6075 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.565103 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.376946 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.337614 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 6 0.10% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 5 0.08% 0.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.03% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 2 0.03% 0.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 4 0.07% 0.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 5 0.08% 0.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 2 0.03% 0.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 3 0.05% 0.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 3 0.05% 0.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 1 0.02% 0.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 4 0.07% 0.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 11 0.18% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2721 44.79% 45.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 38 0.63% 46.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1583 26.06% 72.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1297 21.35% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 91 1.50% 95.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 44 0.72% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 54 0.89% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 48 0.79% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 29 0.48% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 18 0.30% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 20 0.33% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 17 0.28% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 13 0.21% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 16 0.26% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 12 0.20% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.16% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 8 0.13% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads -system.physmem.totQLat 393209260500 # Total ticks spent queuing -system.physmem.totMemAccLat 679455066750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76332215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25756.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.569428 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.390583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.344347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 2 0.03% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 6 0.10% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 3 0.05% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 4 0.07% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 3 0.05% 0.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 1 0.02% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 3 0.05% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 4 0.07% 0.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 3 0.05% 0.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 1 0.02% 0.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 3 0.05% 0.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 10 0.16% 0.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2784 45.86% 46.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 49 0.81% 47.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1358 22.37% 69.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1417 23.34% 93.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 155 2.55% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 60 0.99% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 36 0.59% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.35% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 24 0.40% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.28% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 23 0.38% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 14 0.23% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 10 0.16% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 12 0.20% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 16 0.26% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 11 0.18% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 14 0.23% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads +system.physmem.totQLat 392019251500 # Total ticks spent queuing +system.physmem.totMemAccLat 677734639000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76190770000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25726.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44506.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44476.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 384.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.69 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.01 # Data bus utilization in percentage -system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.02 # Data bus utilization in percentage +system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.37 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.37 # Average write queue length when enqueuing -system.physmem.readRowHits 14270960 # Number of row buffer hits during reads -system.physmem.writeRowHits 91040 # Number of row buffer hits during writes +system.physmem.avgRdQLen 5.74 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.90 # Average write queue length when enqueuing +system.physmem.readRowHits 14244888 # Number of row buffer hits during reads +system.physmem.writeRowHits 91209 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.29 # Row buffer hit rate for writes -system.physmem.avgGap 158334.21 # Average gap between requests -system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2202305646000 # Time in different power states -system.physmem.memoryStateTime::REF 85157800000 # Time in different power states +system.physmem.writeRowHitRate 85.49 # Row buffer hit rate for writes +system.physmem.avgGap 157685.09 # Average gap between requests +system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2193828681000 # Time in different power states +system.physmem.memoryStateTime::REF 84806020000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262767276500 # Time in different power states +system.physmem.memoryStateTime::ACT 261061225250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory @@ -328,289 +328,280 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54978267 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346128 # Transaction distribution -system.membus.trans_dist::ReadResp 16346128 # Transaction distribution -system.membus.trans_dist::WriteReq 763361 # Transaction distribution -system.membus.trans_dist::WriteResp 763361 # Transaction distribution -system.membus.trans_dist::Writeback 59160 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4687 # Transaction distribution -system.membus.trans_dist::ReadExReq 131439 # Transaction distribution -system.membus.trans_dist::ReadExResp 131439 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383052 # Packet count per connected master and slave (bytes) +system.membus.throughput 55193080 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16345666 # Transaction distribution +system.membus.trans_dist::ReadResp 16345666 # Transaction distribution +system.membus.trans_dist::WriteReq 763357 # Transaction distribution +system.membus.trans_dist::WriteResp 763357 # Transaction distribution +system.membus.trans_dist::Writeback 58975 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4635 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4635 # Transaction distribution +system.membus.trans_dist::ReadExReq 131547 # Transaction distribution +system.membus.trans_dist::ReadExResp 131547 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272758 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1884913 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4271753 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550390 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390470 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34549385 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698976 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19097094 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16665056 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19063162 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140207622 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140207622 # Total data (bytes) +system.membus.tot_pkt_size::total 140173690 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140173690 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487194000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487406000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3622500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3427500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17516054500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17563315500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4714051227 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4754319520 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37455331951 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37450374673 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64405 # number of replacements -system.l2c.tags.tagsinuse 51448.142618 # Cycle average of tags in use -system.l2c.tags.total_refs 1904465 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129797 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.672643 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2540066144500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37002.110374 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 24.124150 # Average occupied blocks per requestor +system.l2c.tags.replacements 64063 # number of replacements +system.l2c.tags.tagsinuse 51393.584080 # Cycle average of tags in use +system.l2c.tags.total_refs 1901876 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129454 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.691520 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2528371598500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37072.406553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.476763 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4932.290143 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3309.962047 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.942781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3265.462064 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2905.250809 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564607 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000368 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5409.710973 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3302.260075 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.209843 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2641.050651 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2952.468970 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.565680 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075261 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050506 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000136 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049827 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044331 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.785036 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65365 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.082546 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050388 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000095 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040299 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.045051 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784204 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3060 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6878 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55034 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997391 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18931296 # Number of tag accesses -system.l2c.tags.data_accesses 18931296 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 32363 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6829 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 504085 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 191784 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30935 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6925 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 466764 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 195789 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435474 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608464 # number of Writeback hits -system.l2c.Writeback_hits::total 608464 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 26 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57858 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55192 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113050 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32363 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6829 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 504085 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 249642 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6925 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 466764 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 250981 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548524 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32363 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6829 # number of overall hits -system.l2c.overall_hits::cpu0.inst 504085 # number of overall hits -system.l2c.overall_hits::cpu0.data 249642 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30935 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6925 # number of overall hits -system.l2c.overall_hits::cpu1.inst 466764 # number of overall hits -system.l2c.overall_hits::cpu1.data 250981 # number of overall hits -system.l2c.overall_hits::total 1548524 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 35 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::1 438 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3140 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5952 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55810 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18903981 # Number of tag accesses +system.l2c.tags.data_accesses 18903981 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 27725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7459 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 477090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 174144 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 29829 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 8048 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 498641 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 211687 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1434623 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 606690 # number of Writeback hits +system.l2c.Writeback_hits::total 606690 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 55364 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57398 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112762 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 27725 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7459 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 477090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 229508 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 29829 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 8048 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 498641 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 269085 # number of demand (read+write) hits +system.l2c.demand_hits::total 1547385 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 27725 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7459 # number of overall hits +system.l2c.overall_hits::cpu0.inst 477090 # number of overall hits +system.l2c.overall_hits::cpu0.data 229508 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 29829 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 8048 # number of overall hits +system.l2c.overall_hits::cpu1.inst 498641 # number of overall hits +system.l2c.overall_hits::cpu1.data 269085 # number of overall hits +system.l2c.overall_hits::total 1547385 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7820 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6258 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4574 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4456 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23155 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1552 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1356 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 77511 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 55705 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133216 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 35 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 7229 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6022 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4914 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4504 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22694 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1367 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1538 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 56297 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76980 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133277 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7820 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 83769 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4574 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 60161 # number of demand (read+write) misses -system.l2c.demand_misses::total 156371 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 35 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7229 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 62319 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4914 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 81484 # number of demand (read+write) misses +system.l2c.demand_misses::total 155971 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7820 # number of overall misses -system.l2c.overall_misses::cpu0.data 83769 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4574 # number of overall misses -system.l2c.overall_misses::cpu1.data 60161 # number of overall misses -system.l2c.overall_misses::total 156371 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 3562250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 293000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 558840500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 462734249 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 914250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 333186000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 341954000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1701484249 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 257989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 490479 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5723904556 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3992494167 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9716398723 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 3562250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 293000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 558840500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 6186638805 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 914250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 333186000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4334448167 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11417882972 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 3562250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 293000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 558840500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 6186638805 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 914250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 333186000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4334448167 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11417882972 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 32398 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6830 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 511905 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 198042 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30946 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6925 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 471338 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 200245 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1458629 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608464 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608464 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1578 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1368 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2946 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 9 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 135369 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 110897 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246266 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 32398 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6830 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 511905 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 333411 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30946 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6925 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 471338 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 311142 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1704895 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 32398 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6830 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 511905 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 333411 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30946 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6925 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 471338 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 311142 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1704895 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001080 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000146 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015276 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.031599 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000355 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009704 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.022253 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015874 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.983523 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991228 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.987101 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.111111 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.111111 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.111111 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.572590 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.502313 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.540944 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001080 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000146 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015276 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.251248 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000355 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009704 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.193355 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091719 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001080 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000146 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015276 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.251248 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000355 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009704 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.193355 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091719 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 101778.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 293000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71462.979540 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73942.833014 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83113.636364 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72843.463052 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76740.125673 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 73482.368776 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 149.800258 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 190.257375 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 168.665406 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73846.351563 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71672.097065 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 72937.175137 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101778.571429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 293000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 71462.979540 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 73853.559252 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83113.636364 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72843.463052 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 72047.475391 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 73017.905954 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101778.571429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 293000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 71462.979540 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 73853.559252 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83113.636364 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72843.463052 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 72047.475391 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 73017.905954 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 7229 # number of overall misses +system.l2c.overall_misses::cpu0.data 62319 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4914 # number of overall misses +system.l2c.overall_misses::cpu1.data 81484 # number of overall misses +system.l2c.overall_misses::total 155971 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1336000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 518356500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 443449495 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 747000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 356901000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 338441743 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1659313738 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 162993 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 254989 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 417982 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4027199927 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5731646841 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9758846768 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1336000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 82000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 518356500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4470649422 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 747000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 356901000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6070088584 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11418160506 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1336000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 82000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 518356500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4470649422 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 747000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 356901000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6070088584 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11418160506 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 27739 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7460 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 484319 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 180166 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 29839 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 8048 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 503555 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 216191 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1457317 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 606690 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 606690 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1384 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1551 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2935 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111661 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 134378 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246039 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 27739 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7460 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 484319 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 291827 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 29839 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 8048 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 503555 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 350569 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1703356 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 27739 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7460 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 484319 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 291827 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 29839 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 8048 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 503555 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 350569 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1703356 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000505 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000134 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014926 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.033425 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000335 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009759 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.020833 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015572 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987717 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991618 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989779 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.504178 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.572862 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541691 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000505 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000134 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014926 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.213548 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000335 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009759 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.232434 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091567 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000505 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000134 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014926 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.213548 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000335 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009759 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.232434 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091567 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95428.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71705.145940 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 73638.242278 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74700 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72629.426129 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 75142.482904 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 73116.847537 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 119.234089 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 165.792588 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 143.883649 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71534.893991 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74456.311263 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 73222.287176 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95428.571429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 71705.145940 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 71738.144418 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74700 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 72629.426129 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 74494.239164 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 73206.945560 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95428.571429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 71705.145940 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 71738.144418 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74700 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 72629.426129 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 74494.239164 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 73206.945560 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -619,166 +610,154 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59160 # number of writebacks -system.l2c.writebacks::total 59160 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 43 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 22 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 43 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 22 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 43 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 22 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 35 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 58975 # number of writebacks +system.l2c.writebacks::total 58975 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 18 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 68 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7812 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6215 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4568 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4434 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23076 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1552 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1356 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2908 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 77511 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 55705 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133216 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 35 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7222 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5983 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4910 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4486 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22626 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1367 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1538 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2905 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 56297 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76980 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133277 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7812 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 83726 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4568 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 60139 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156292 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 35 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7222 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 62280 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4910 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 81466 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 155903 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7812 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 83726 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4568 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 60139 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156292 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3127750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 281000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 460062000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 382258249 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 778250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 275211250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 285303500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1407021999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15521552 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13562356 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29083908 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4769263944 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3305065333 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8074329277 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3127750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 281000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 460062000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 5151522193 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 778250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 275211250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3590368833 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9481351276 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3127750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 281000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 460062000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5151522193 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 778250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 275211250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3590368833 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9481351276 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6525500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83923690500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83019017000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166949233000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8966653586 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8434821998 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17401475584 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6525500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92890344086 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91453838998 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184350708584 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001080 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015261 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.031382 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000355 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009692 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022143 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015820 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.983523 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991228 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.987101 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.111111 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.111111 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.111111 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.572590 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.502313 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.540944 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001080 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015261 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.251119 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000355 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009692 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.193285 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091673 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001080 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015261 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.251119 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000355 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009692 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.193285 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61505.752051 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64344.497068 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60973.392226 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.737463 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.343879 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61530.156287 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59331.574060 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60610.807088 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61528.344756 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59701.172833 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 60664.341591 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61528.344756 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59701.172833 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60664.341591 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 7222 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 62280 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4910 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 81466 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 155903 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1163500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 427109500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 366125745 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 625000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 294835000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 281582243 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1371510988 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13679367 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15384538 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29063905 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3324764073 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4773094655 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8097858728 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1163500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 427109500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3690889818 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 625000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 294835000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5054676898 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9469369716 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1163500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 427109500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3690889818 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 625000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 294835000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5054676898 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9469369716 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6117750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83698669250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83244575500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166949362500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 7714617000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 9329751845 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17044368845 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6117750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91413286250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92574327345 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183993731345 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033208 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020750 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015526 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987717 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991618 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.989779 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.504178 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.572862 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541691 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.213414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.232382 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091527 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.213414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.232382 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091527 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61194.341467 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62769.113464 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60616.591002 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.852231 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.950585 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.786575 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59057.570972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62004.347298 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60759.611396 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59262.842293 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62046.459848 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60738.855032 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59262.842293 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62046.459848 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60738.855032 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -797,48 +776,48 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58447524 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676676 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676675 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763361 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763361 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608464 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2946 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2964 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246266 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246266 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967872 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798454 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37749 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149111 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7953186 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62935104 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85607366 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55020 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148850866 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148850866 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 204184 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4964883974 # Layer occupancy (ticks) +system.toL2Bus.throughput 58696725 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2675214 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2675214 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 606690 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2935 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2937 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246039 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246039 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1976942 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5792286 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42218 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136665 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7948111 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63231360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85355770 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148879474 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148879474 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 192412 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4956067661 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4433375902 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4453658755 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4485758372 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4478828129 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24044394 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 26774357 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86236537 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 79740148 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48427259 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322165 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322165 # Transaction distribution -system.iobus.trans_dist::WriteReq 8177 # Transaction distribution -system.iobus.trans_dist::WriteResp 8177 # Transaction distribution +system.iobus.throughput 48628247 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution +system.iobus.trans_dist::WriteReq 8176 # Transaction distribution +system.iobus.trans_dist::WriteResp 8176 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7932 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -858,14 +837,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -885,18 +864,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390470 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500998 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500998 # Total data (bytes) +system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123501006 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3971000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -938,19 +917,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374875000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38148865049 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38124261327 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7661485 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6126508 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 381527 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4905065 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3983490 # Number of BTB hits +system.cpu0.branchPred.lookups 7765284 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5771603 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 325703 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4845901 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3829041 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.211768 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 723596 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38982 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 79.016080 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 808445 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 22619 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -974,25 +953,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25785436 # DTB read hits -system.cpu0.dtb.read_misses 39736 # DTB read misses -system.cpu0.dtb.write_hits 6191742 # DTB write hits -system.cpu0.dtb.write_misses 10170 # DTB write misses -system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 27181562 # DTB read hits +system.cpu0.dtb.read_misses 37782 # DTB read misses +system.cpu0.dtb.write_hits 5596065 # DTB write hits +system.cpu0.dtb.write_misses 10098 # DTB write misses +system.cpu0.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5474 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1453 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5491 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 645 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 284 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 628 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25825172 # DTB read accesses -system.cpu0.dtb.write_accesses 6201912 # DTB write accesses +system.cpu0.dtb.perms_faults 704 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 27219344 # DTB read accesses +system.cpu0.dtb.write_accesses 5606163 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31977178 # DTB hits -system.cpu0.dtb.misses 49906 # DTB misses -system.cpu0.dtb.accesses 32027084 # DTB accesses +system.cpu0.dtb.hits 32777627 # DTB hits +system.cpu0.dtb.misses 47880 # DTB misses +system.cpu0.dtb.accesses 32825507 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1014,696 +993,712 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5958651 # ITB inst hits -system.cpu0.itb.inst_misses 7224 # ITB inst misses +system.cpu0.itb.inst_hits 5349242 # ITB inst hits +system.cpu0.itb.inst_misses 7594 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2573 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2439 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5965875 # ITB inst accesses -system.cpu0.itb.hits 5958651 # DTB hits -system.cpu0.itb.misses 7224 # DTB misses -system.cpu0.itb.accesses 5965875 # DTB accesses -system.cpu0.numCycles 242096947 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5356836 # ITB inst accesses +system.cpu0.itb.hits 5349242 # DTB hits +system.cpu0.itb.misses 7594 # DTB misses +system.cpu0.itb.accesses 5356836 # DTB accesses +system.cpu0.numCycles 234138431 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15548527 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 46430150 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7661485 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4707086 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10443980 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2504010 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 87505 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 47991707 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1669 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1947 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 50069 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1492171 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5956718 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 371320 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77361996 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.753757 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.110815 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 14733348 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 42294638 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7765284 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4637486 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 215157682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 899672 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 103093 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 978 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1882 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 100153 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1830103 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 127 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5346345 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 204670 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3021 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 232377075 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.216391 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.156919 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 66925381 86.51% 86.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 685980 0.89% 87.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 883677 1.14% 88.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1195178 1.54% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1096516 1.42% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 566437 0.73% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1314357 1.70% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 386846 0.50% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4307624 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 222728537 95.85% 95.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 885926 0.38% 96.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 959241 0.41% 96.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1030592 0.44% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1233052 0.53% 97.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 718062 0.31% 97.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1129349 0.49% 98.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 448984 0.19% 98.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3243332 1.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77361996 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031646 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.191783 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16313273 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49370536 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9491475 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 529288 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1655237 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1021533 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91523 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 55531280 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 303986 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1655237 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17162522 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7654348 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 28580121 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9244360 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 13063308 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 52889125 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1160 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 8605902 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 9933616 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1829408 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 705 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 54696180 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 245103090 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 223663577 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5274 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39761499 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14934681 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 590339 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 538925 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5812671 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10214201 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7053988 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1084092 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1355038 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49147671 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1004891 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62507144 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 106564 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10354652 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26208427 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256708 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77361996 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.807983 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.536259 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 232377075 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.033165 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.180639 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12160999 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 212353937 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6177683 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1309281 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 372986 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 974074 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 78107 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 45045632 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 258698 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 372986 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12774661 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 53419035 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 30524585 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6795741 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 128487965 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 43632543 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1343 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 95385189 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 124519108 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1934134 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 46283925 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 200651385 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 53129662 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5272 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36330469 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 9953456 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 576590 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 492282 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 7436987 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7977179 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6240861 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1088795 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1688387 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 41277277 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1012498 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 59014531 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 58753 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7256631 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 15830718 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 292140 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 232377075 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.253960 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.959343 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55228815 71.39% 71.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6921867 8.95% 80.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3371546 4.36% 84.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2828196 3.66% 88.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6343832 8.20% 96.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1429149 1.85% 98.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 903697 1.17% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 264810 0.34% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 70084 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 212079469 91.27% 91.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6238226 2.68% 93.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2924438 1.26% 95.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2416467 1.04% 96.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6166815 2.65% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1071194 0.46% 99.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 901941 0.39% 99.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 385048 0.17% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 193477 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77361996 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 232377075 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 34065 0.76% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4230863 93.99% 94.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 236461 5.25% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 114630 2.27% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4666706 92.48% 94.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 264598 5.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14977 0.02% 0.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29471794 47.15% 47.17% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48326 0.08% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1252 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26467836 42.34% 89.60% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6502932 10.40% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15012 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 25515552 43.24% 43.26% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47770 0.08% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 902 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 27508063 46.61% 89.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5927232 10.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62507144 # Type of FU issued -system.cpu0.iq.rate 0.258191 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4501391 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.072014 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 207022163 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60516960 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43741315 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11807 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6284 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5315 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66987291 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6267 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 331575 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 59014531 # Type of FU issued +system.cpu0.iq.rate 0.252050 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 5045937 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.085503 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 355498871 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 49563440 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 38260615 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11956 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6482 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 64039026 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6430 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 226085 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2258680 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16640 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 890724 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1459518 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2588 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 24632 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 672041 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17025951 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348422 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17098280 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 3147229 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1655237 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6199849 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 752551 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50264845 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10214201 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7053988 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 705061 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 147463 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 536075 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16640 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186895 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 147787 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 334682 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61435794 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26133192 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1071350 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 372986 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 50915247 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1803662 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 42401043 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 79571 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7977179 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6240861 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 734817 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 139591 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1596321 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 24632 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 160350 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 132588 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 292938 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 58604130 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 27345857 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 362682 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 112283 # number of nop insts executed -system.cpu0.iew.exec_refs 32576038 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6024055 # Number of branches executed -system.cpu0.iew.exec_stores 6442846 # Number of stores executed -system.cpu0.iew.exec_rate 0.253765 # Inst execution rate -system.cpu0.iew.wb_sent 60932314 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43746630 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24175990 # num instructions producing a value -system.cpu0.iew.wb_consumers 44857309 # num instructions consuming a value +system.cpu0.iew.exec_nop 111268 # number of nop insts executed +system.cpu0.iew.exec_refs 33208867 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5668977 # Number of branches executed +system.cpu0.iew.exec_stores 5863010 # Number of stores executed +system.cpu0.iew.exec_rate 0.250297 # Inst execution rate +system.cpu0.iew.wb_sent 55434698 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 38265806 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 21645924 # num instructions producing a value +system.cpu0.iew.wb_consumers 38521221 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.180699 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.538953 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.163432 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.561922 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10244306 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 748183 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 291383 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75706759 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.522606 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.501619 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7110536 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 720358 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 248726 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 231246727 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.150700 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 0.849611 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61320530 81.00% 81.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7333121 9.69% 90.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1910409 2.52% 93.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1174950 1.55% 94.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 814971 1.08% 95.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 569506 0.75% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 771340 1.02% 97.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 344904 0.46% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1467028 1.94% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 218753445 94.60% 94.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6297983 2.72% 97.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1708084 0.74% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1059115 0.46% 98.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 644957 0.28% 98.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 581299 0.25% 99.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 449364 0.19% 99.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 245033 0.11% 99.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1507447 0.65% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75706759 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30422123 # Number of instructions committed -system.cpu0.commit.committedOps 39564795 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 231246727 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29059194 # Number of instructions committed +system.cpu0.commit.committedOps 34848810 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14118785 # Number of memory references committed -system.cpu0.commit.loads 7955521 # Number of loads committed -system.cpu0.commit.membars 210845 # Number of memory barriers committed -system.cpu0.commit.branches 5215430 # Number of branches committed -system.cpu0.commit.fp_insts 5270 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35234514 # Number of committed integer instructions. -system.cpu0.commit.function_calls 505825 # Number of function calls committed. +system.cpu0.commit.refs 12086481 # Number of memory references committed +system.cpu0.commit.loads 6517661 # Number of loads committed +system.cpu0.commit.membars 192728 # Number of memory barriers committed +system.cpu0.commit.branches 4958536 # Number of branches committed +system.cpu0.commit.fp_insts 5174 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 30757342 # Number of committed integer instructions. +system.cpu0.commit.function_calls 472350 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 25399613 64.20% 64.20% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 45146 0.11% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 1251 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7955521 20.11% 84.42% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 6163264 15.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 22717072 65.19% 65.19% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 44355 0.13% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 902 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6517661 18.70% 84.02% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5568820 15.98% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 39564795 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1467028 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 34848810 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1507447 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123090455 # The number of ROB reads -system.cpu0.rob.rob_writes 101316686 # The number of ROB writes -system.cpu0.timesIdled 905863 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 164734951 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2248240039 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 30347856 # Number of Instructions Simulated -system.cpu0.committedOps 39490528 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 7.977399 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.977399 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.125354 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.125354 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 279159718 # number of integer regfile reads -system.cpu0.int_regfile_writes 44499662 # number of integer regfile writes -system.cpu0.fp_regfile_reads 45106 # number of floating regfile reads -system.cpu0.fp_regfile_writes 42408 # number of floating regfile writes -system.cpu0.misc_regfile_reads 136236681 # number of misc regfile reads -system.cpu0.misc_regfile_writes 579467 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983848 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.584983 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10572279 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984360 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.740257 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6906897250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 320.103204 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.481778 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.625202 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.373988 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 270795640 # The number of ROB reads +system.cpu0.rob.rob_writes 85052492 # The number of ROB writes +system.cpu0.timesIdled 264396 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1761356 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2270391996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 28992496 # Number of Instructions Simulated +system.cpu0.committedOps 34782112 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 8.075829 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.075829 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123826 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123826 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66468797 # number of integer regfile reads +system.cpu0.int_regfile_writes 24185826 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44758 # number of floating regfile reads +system.cpu0.fp_regfile_writes 41844 # number of floating regfile writes +system.cpu0.cc_regfile_reads 196782773 # number of cc regfile reads +system.cpu0.cc_regfile_writes 15711716 # number of cc regfile writes +system.cpu0.misc_regfile_reads 291428250 # number of misc regfile reads +system.cpu0.misc_regfile_writes 565781 # number of misc regfile writes +system.cpu0.icache.tags.replacements 988317 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.592753 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 9970376 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 988829 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.083013 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6654117250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 184.676713 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 326.916040 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.360697 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.638508 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999205 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12622728 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12622728 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5401219 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5171060 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10572279 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5401219 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5171060 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10572279 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5401219 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5171060 # number of overall hits -system.cpu0.icache.overall_hits::total 10572279 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 555378 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 510680 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1066058 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 555378 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 510680 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1066058 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 555378 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 510680 # number of overall misses -system.cpu0.icache.overall_misses::total 1066058 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7663232618 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6859208809 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14522441427 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7663232618 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6859208809 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14522441427 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7663232618 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6859208809 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14522441427 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5956597 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5681740 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11638337 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5956597 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5681740 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11638337 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5956597 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5681740 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11638337 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.093237 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089881 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.091599 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.093237 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089881 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.091599 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.093237 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089881 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.091599 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13798.228626 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13431.520343 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13622.562212 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13798.228626 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13431.520343 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13622.562212 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13798.228626 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13431.520343 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13622.562212 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6762 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 12025421 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 12025421 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 4823915 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5146461 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 9970376 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 4823915 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5146461 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 9970376 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 4823915 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5146461 # number of overall hits +system.cpu0.icache.overall_hits::total 9970376 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 522311 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 543898 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1066209 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 522311 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 543898 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1066209 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 522311 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 543898 # number of overall misses +system.cpu0.icache.overall_misses::total 1066209 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7237674573 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7341681631 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14579356204 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7237674573 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 7341681631 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14579356204 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7237674573 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 7341681631 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14579356204 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5346226 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5690359 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11036585 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5346226 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5690359 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11036585 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5346226 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5690359 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11036585 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097697 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.095582 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.096607 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097697 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.095582 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.096607 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097697 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.095582 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.096607 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13857.021148 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13498.269218 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13674.013448 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13857.021148 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13498.269218 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13674.013448 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13857.021148 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13498.269218 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13674.013448 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4158 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 376 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 274 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.984043 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.175182 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42863 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38803 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 81666 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 42863 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 38803 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 81666 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 42863 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 38803 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 81666 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 512515 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 471877 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984392 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 512515 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 471877 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984392 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 512515 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 471877 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984392 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6228172986 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5583639583 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11811812569 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6228172986 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5583639583 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11811812569 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6228172986 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5583639583 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11811812569 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8994500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8994500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8994500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8994500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086042 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.083051 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084582 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086042 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.083051 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.084582 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086042 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.083051 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.084582 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11999.094435 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11999.094435 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11999.094435 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37549 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39824 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 77373 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 37549 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39824 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 77373 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 37549 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39824 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 77373 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 484762 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 504074 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 988836 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 484762 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 504074 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 988836 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 484762 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 504074 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 988836 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5888564763 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5971220456 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11859785219 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5888564763 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5971220456 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11859785219 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5888564763 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5971220456 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11859785219 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8523250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8523250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8523250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8523250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090674 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.088584 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089596 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090674 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088584 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.089596 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090674 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.088584 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.089596 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11993.682693 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11993.682693 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11993.682693 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 644041 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993361 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21521749 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644553 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.390193 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 42479250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.642215 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.351146 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499301 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500686 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 641884 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993418 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19756750 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 642396 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.754784 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 42094250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 133.972457 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 378.020960 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.261665 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.738322 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101726761 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101726761 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7076892 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6698233 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13775125 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3751457 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3500966 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7252423 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118146 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 125300 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243446 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 120516 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 127110 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247626 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10828349 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10199199 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21027548 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10828349 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10199199 # number of overall hits -system.cpu0.dcache.overall_hits::total 21027548 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 365609 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 402058 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 767667 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1663469 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1307220 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2970689 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7411 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6147 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13558 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 9 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 9 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2029078 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1709278 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3738356 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2029078 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1709278 # number of overall misses -system.cpu0.dcache.overall_misses::total 3738356 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5771940837 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5897981485 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11669922322 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84085334445 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 56096709102 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 140182043547 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106232248 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 81884247 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 188116495 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 129501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 129501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 259002 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 89857275282 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 61994690587 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 151851965869 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 89857275282 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 61994690587 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 151851965869 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7442501 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7100291 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14542792 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5414926 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4808186 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223112 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125557 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 131447 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257004 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 120525 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 127119 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247644 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12857427 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11908477 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24765904 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12857427 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11908477 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24765904 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.049124 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.056626 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.052787 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.307201 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.271874 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.290586 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059025 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.046764 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052754 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000075 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000071 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000073 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.157814 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.143535 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.150948 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.157814 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.143535 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.150948 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15787.195712 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14669.479242 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15201.802763 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50548.182410 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42912.982591 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 47188.394190 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14334.401295 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13321.009761 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13874.944313 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14389 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 14389 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14389 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44284.781207 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 36269.518818 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 40619.985328 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44284.781207 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36269.518818 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 40619.985328 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36311 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 24635 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3444 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 311 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.543264 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 79.212219 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 95317436 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 95317436 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5857300 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6196947 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 12054247 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3502178 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3641154 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7143332 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 35246 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 29793 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 65039 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 110182 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 133190 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243372 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112371 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 135291 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247662 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9359478 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 9838101 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19197579 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9394724 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 9867894 # number of overall hits +system.cpu0.dcache.overall_hits::total 19262618 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 295687 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 396301 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 691988 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1362259 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1719020 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 3081279 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 73803 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 54706 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 128509 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6350 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6980 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13330 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1657946 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 2115321 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3773267 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1731749 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 2170027 # number of overall misses +system.cpu0.dcache.overall_misses::total 3901776 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4378228092 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5755162638 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 10133390730 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57860586634 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 86029827577 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 143890414211 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92678240 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94350988 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 187029228 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 62238814726 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 91784990215 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 154023804941 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 62238814726 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 91784990215 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 154023804941 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6152987 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6593248 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 12746235 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4864437 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5360174 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10224611 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 109049 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 84499 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 193548 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 116532 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 140170 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256702 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 112373 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 135291 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247664 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11017424 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11953422 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 22970846 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11126473 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12037921 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23164394 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048056 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060107 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.054290 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.280045 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.320702 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.301359 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.676787 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.647416 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.663964 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054491 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049797 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.051928 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000018 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150484 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.176964 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.164263 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.155642 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.180266 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.168439 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14806.968490 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14522.200645 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14643.882163 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42473.998435 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50045.856114 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 46698.275038 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14594.998425 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13517.333524 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14030.699775 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37539.711623 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 43390.572975 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 40819.747169 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35939.858909 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42296.704241 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39475.306871 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 204060 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 43131 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 27157 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 778 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.514085 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 55.438303 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608464 # number of writebacks -system.cpu0.dcache.writebacks::total 608464 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174205 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 207237 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 381442 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1526591 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1195009 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2721600 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 704 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 669 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1373 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1700796 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1402246 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3103042 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1700796 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1402246 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3103042 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191404 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 194821 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386225 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 136878 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 112211 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249089 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6707 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5478 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 9 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 9 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 18 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 328282 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 307032 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635314 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 328282 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 307032 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635314 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2672225710 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2597817092 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5270042802 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6526900100 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4738022235 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11264922335 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84662502 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63153752 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147816254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 111499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 111499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 222998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9199125810 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7335839327 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16534965137 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9199125810 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7335839327 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16534965137 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91653477500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90683023500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336501000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13720132000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13077337591 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26797469591 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105373609500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103760361091 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209133970591 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025718 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027438 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026558 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025278 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023337 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024365 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053418 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041675 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047412 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000075 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000071 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025653 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025653 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13961.180069 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13334.379210 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13645.006931 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47684.069756 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42224.222536 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45224.487372 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12623.006113 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11528.614823 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.001559 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12388.777778 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12388.777778 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12388.777778 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 606690 # number of writebacks +system.cpu0.dcache.writebacks::total 606690 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 164206 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 218384 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 382590 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1249257 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1583126 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2832383 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 616 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 758 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1374 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1413463 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1801510 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3214973 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1413463 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1801510 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3214973 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 131481 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 177917 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 309398 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 113002 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 135894 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248896 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 42994 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 32087 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 75081 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5734 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6222 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11956 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 244483 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 313811 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 558294 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 287477 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 345898 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 633375 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1725190273 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2222171472 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3947361745 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4787330436 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6538944348 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11326274784 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 807768256 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 644366504 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1452134760 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73471759 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72597010 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146068769 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6512520709 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8761115820 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15273636529 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7320288965 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9405482324 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16725771289 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91407551750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90929310002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336861752 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 11972132389 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14721058995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26693191384 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103379684139 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105650368997 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030053136 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021369 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026985 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024274 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023230 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025353 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.394263 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.379732 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.387919 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049205 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044389 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046575 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000018 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.022191 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026253 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024304 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025837 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028734 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027343 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13121.213506 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12489.933351 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12758.200586 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42365.006248 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48117.976864 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45506.053870 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18787.929851 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20081.855705 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19340.908619 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12813.351761 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11667.793314 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12217.193794 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26637.928645 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27918.447154 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27357.694206 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25463.911774 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27191.490914 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26407.375234 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1714,15 +1709,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7344792 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5924572 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 342317 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4758265 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3794052 # Number of BTB hits +system.cpu1.branchPred.lookups 8288231 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6165176 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 342380 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5156418 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4057157 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.736038 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 685317 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35371 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 78.681693 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 881950 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 23449 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1746,25 +1741,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25350014 # DTB read hits -system.cpu1.dtb.read_misses 36246 # DTB read misses -system.cpu1.dtb.write_hits 5533315 # DTB write hits -system.cpu1.dtb.write_misses 8540 # DTB write misses -system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 28293531 # DTB read hits +system.cpu1.dtb.read_misses 40544 # DTB read misses +system.cpu1.dtb.write_hits 6190636 # DTB write hits +system.cpu1.dtb.write_misses 14491 # DTB write misses +system.cpu1.dtb.flush_tlb 506 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5471 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1908 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5400 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 865 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 710 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25386260 # DTB read accesses -system.cpu1.dtb.write_accesses 5541855 # DTB write accesses +system.cpu1.dtb.perms_faults 723 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 28334075 # DTB read accesses +system.cpu1.dtb.write_accesses 6205127 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 30883329 # DTB hits -system.cpu1.dtb.misses 44786 # DTB misses -system.cpu1.dtb.accesses 30928115 # DTB accesses +system.cpu1.dtb.hits 34484167 # DTB hits +system.cpu1.dtb.misses 55035 # DTB misses +system.cpu1.dtb.accesses 34539202 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1786,329 +1781,329 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5683844 # ITB inst hits -system.cpu1.itb.inst_misses 6848 # ITB inst misses +system.cpu1.itb.inst_hits 5693555 # ITB inst hits +system.cpu1.itb.inst_misses 8207 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 506 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2653 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2675 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1514 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2702 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5690692 # ITB inst accesses -system.cpu1.itb.hits 5683844 # DTB hits -system.cpu1.itb.misses 6848 # DTB misses -system.cpu1.itb.accesses 5690692 # DTB accesses -system.cpu1.numCycles 235812118 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5701762 # ITB inst accesses +system.cpu1.itb.hits 5693555 # DTB hits +system.cpu1.itb.misses 8207 # DTB misses +system.cpu1.itb.accesses 5701762 # DTB accesses +system.cpu1.numCycles 237058963 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14488159 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45028124 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7344792 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4479369 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9950354 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2325910 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82893 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 46948697 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1099 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1893 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 45519 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1268155 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 161 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5681743 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 353393 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2950 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74402978 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.748631 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.104884 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15389347 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 44896719 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8288231 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4939107 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 217242159 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 949095 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 106364 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 1987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1943 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 92979 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 2091650 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5690360 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 215494 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3361 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 235400962 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.228809 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.188674 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64461074 86.64% 86.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 633258 0.85% 87.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 845202 1.14% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1118143 1.50% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1030578 1.39% 91.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 551741 0.74% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1296054 1.74% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 370486 0.50% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4096442 5.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 225085908 95.62% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 947634 0.40% 96.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1047135 0.44% 96.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1048515 0.45% 96.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1240998 0.53% 97.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 829745 0.35% 97.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1296822 0.55% 98.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 452969 0.19% 98.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3451236 1.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74402978 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031147 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190949 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15290128 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 48029788 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9010807 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 535995 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1534066 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 962796 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 84486 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53087117 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 281620 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1534066 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16089413 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6996685 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 28422508 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8819964 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 12538212 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50579819 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 715 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 8590875 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 9852379 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1395671 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 1301 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 52976488 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 233969396 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 213834273 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5207 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38971918 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14004569 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 583497 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 540607 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 5363476 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9768473 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6353478 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 903299 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1144541 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47001226 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 985413 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60595640 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 98989 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9593116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24473464 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 250944 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74402978 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.814425 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.533021 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 235400962 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.034963 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.189391 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 12590716 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 214453384 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 6500032 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1465156 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 389454 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1047596 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86470 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 48240012 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 288766 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 389454 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 13272686 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 54002992 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 31282477 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 7201814 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 129249426 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 46761611 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 1258 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 95572539 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 124561907 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 2450017 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 49620172 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 215588900 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 57377506 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 4944 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39615169 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 10004995 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 609511 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 515718 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8221045 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 8459299 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6818667 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1033426 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1557443 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 44314605 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1045489 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62743783 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 61525 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 7205140 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 16025571 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 281591 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 235400962 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.266540 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.981476 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 52794785 70.96% 70.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6823804 9.17% 80.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3272663 4.40% 84.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2786608 3.75% 88.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6272134 8.43% 96.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1319081 1.77% 98.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 820611 1.10% 99.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 247257 0.33% 99.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 66035 0.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 213793871 90.82% 90.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6637383 2.82% 93.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3199231 1.36% 95.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2579548 1.10% 96.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6422119 2.73% 98.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1152982 0.49% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1001630 0.43% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 407456 0.17% 99.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 206742 0.09% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74402978 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 235400962 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29526 0.66% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4196905 94.38% 95.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 220217 4.95% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 146491 2.81% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4788852 91.80% 94.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 281237 5.39% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 13541 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28679065 47.33% 47.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45344 0.07% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 858 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26009717 42.92% 90.35% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5847084 9.65% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13506 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 27516436 43.86% 43.88% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46370 0.07% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1209 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 28654021 45.67% 89.62% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6512241 10.38% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60595640 # Type of FU issued -system.cpu1.iq.rate 0.256966 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4446652 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.073382 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 200172970 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57588554 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41991709 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11520 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6240 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4992 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65022566 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6185 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 323560 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62743783 # Type of FU issued +system.cpu1.iq.rate 0.264676 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 5216581 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.083141 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 366155152 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 52582376 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41291326 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11482 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6074 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5054 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 67940659 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6199 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 226253 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2067890 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2468 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15600 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 783792 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1460814 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2639 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 24306 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 652998 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16950409 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 331839 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17101900 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3881798 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1534066 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5578937 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 735039 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48101549 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 89840 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9768473 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6353478 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 710230 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 138266 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 531900 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15600 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 167974 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 132221 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 300195 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59563474 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25690610 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1032166 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 389454 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 50160792 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 3093797 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 45494090 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 85835 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 8459299 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6818667 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 741438 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2862513 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 24306 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 166054 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 139765 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 305819 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 62318890 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 28486625 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 369994 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 114910 # number of nop insts executed -system.cpu1.iew.exec_refs 31485549 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5840798 # Number of branches executed -system.cpu1.iew.exec_stores 5794939 # Number of stores executed -system.cpu1.iew.exec_rate 0.252589 # Inst execution rate -system.cpu1.iew.wb_sent 59096440 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41996701 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23719594 # num instructions producing a value -system.cpu1.iew.wb_consumers 43668575 # num instructions consuming a value +system.cpu1.iew.exec_nop 133996 # number of nop insts executed +system.cpu1.iew.exec_refs 34929125 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6064585 # Number of branches executed +system.cpu1.iew.exec_stores 6442500 # Number of stores executed +system.cpu1.iew.exec_rate 0.262884 # Inst execution rate +system.cpu1.iew.wb_sent 58464614 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41296380 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23329556 # num instructions producing a value +system.cpu1.iew.wb_consumers 41830645 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178094 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.543173 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.174203 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.557714 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9469311 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 734469 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 259123 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 72868911 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.524128 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.502288 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 7169441 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 763898 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 257160 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 234250313 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.162130 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 0.884909 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 58802570 80.70% 80.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7335717 10.07% 90.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1834357 2.52% 93.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1110131 1.52% 94.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 806352 1.11% 95.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 478738 0.66% 96.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 708592 0.97% 97.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 352493 0.48% 98.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1439961 1.98% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 220821840 94.27% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6746509 2.88% 97.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1771690 0.76% 97.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1085849 0.46% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 731494 0.31% 98.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 648369 0.28% 98.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 505518 0.22% 99.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 281725 0.12% 99.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1657319 0.71% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 72868911 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30042313 # Number of instructions committed -system.cpu1.commit.committedOps 38192613 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 234250313 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31416794 # Number of instructions committed +system.cpu1.commit.committedOps 37978992 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13270269 # Number of memory references committed -system.cpu1.commit.loads 7700583 # Number of loads committed -system.cpu1.commit.membars 192827 # Number of memory barriers committed -system.cpu1.commit.branches 5091642 # Number of branches committed -system.cpu1.commit.fp_insts 4942 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33962282 # Number of committed integer instructions. -system.cpu1.commit.function_calls 485556 # Number of function calls committed. +system.cpu1.commit.refs 13164154 # Number of memory references committed +system.cpu1.commit.loads 6998485 # Number of loads committed +system.cpu1.commit.membars 211048 # Number of memory barriers committed +system.cpu1.commit.branches 5351716 # Number of branches committed +system.cpu1.commit.fp_insts 5038 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33506635 # Number of committed integer instructions. +system.cpu1.commit.function_calls 519749 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 24878693 65.14% 65.14% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 42793 0.11% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 858 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 7700583 20.16% 85.42% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 5569686 14.58% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 24770094 65.22% 65.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 43535 0.11% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 1209 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 6998485 18.43% 83.77% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6165669 16.23% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 38192613 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1439961 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 37978992 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1657319 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 118199712 # The number of ROB reads -system.cpu1.rob.rob_writes 96901530 # The number of ROB writes -system.cpu1.timesIdled 866503 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 161409140 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2317329341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29966199 # Number of Instructions Simulated -system.cpu1.committedOps 38116499 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 7.869270 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.869270 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.127077 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.127077 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 270334360 # number of integer regfile reads -system.cpu1.int_regfile_writes 43344614 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45048 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42280 # number of floating regfile writes -system.cpu1.misc_regfile_reads 130449609 # number of misc regfile reads -system.cpu1.misc_regfile_writes 594503 # number of misc regfile writes +system.cpu1.rob.rob_reads 276790751 # The number of ROB reads +system.cpu1.rob.rob_writes 91451122 # The number of ROB writes +system.cpu1.timesIdled 270857 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1658001 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2279071980 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31333111 # Number of Instructions Simulated +system.cpu1.committedOps 37895309 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 7.565765 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.565765 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.132174 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.132174 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 71132794 # number of integer regfile reads +system.cpu1.int_regfile_writes 26016814 # number of integer regfile writes +system.cpu1.fp_regfile_reads 44316 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42056 # number of floating regfile writes +system.cpu1.cc_regfile_reads 209312794 # number of cc regfile reads +system.cpu1.cc_regfile_writes 17049814 # number of cc regfile writes +system.cpu1.misc_regfile_reads 299103919 # number of misc regfile reads +system.cpu1.misc_regfile_writes 609097 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2125,17 +2120,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1734330533049 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1734330533049 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1732377463327 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1732377463327 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83365 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index cce768d16..936db738a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.631271 # Number of seconds simulated -sim_ticks 2631271319500 # Number of ticks simulated -final_tick 2631271319500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.626162 # Number of seconds simulated +sim_ticks 2626161554000 # Number of ticks simulated +final_tick 2626161554000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 354699 # Simulator instruction rate (inst/s) -host_op_rate 451347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15499898557 # Simulator tick rate (ticks/s) -host_mem_usage 465856 # Number of bytes of host memory used -host_seconds 169.76 # Real time elapsed on the host -sim_insts 60213853 # Number of instructions simulated -sim_ops 76620850 # Number of ops (including micro ops) simulated +host_inst_rate 476066 # Simulator instruction rate (inst/s) +host_op_rate 568569 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20761634862 # Simulator tick rate (ticks/s) +host_mem_usage 472496 # Number of bytes of host memory used +host_seconds 126.49 # Real time elapsed on the host +sim_insts 60218144 # Number of instructions simulated +sim_ops 71918894 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -27,134 +27,134 @@ system.realview.nvmem.bw_total::cpu0.inst 8 # T system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 299528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4518680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 306888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4490328 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 404800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4542464 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 299528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 404800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1524152 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1491920 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706696 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 399040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4560448 # Number of bytes read from this memory +system.physmem.bytes_read::total 134013152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 306888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 399040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677952 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1536620 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1479452 # Number of bytes written to this memory +system.physmem.bytes_written::total 6694024 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10892 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70640 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11007 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 70976 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690868 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 381038 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 372980 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811684 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47222898 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6235 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 71257 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690721 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57468 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 384155 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 369863 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811486 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47314780 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 113834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1717299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 116858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1709845 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 153842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1726338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50934284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 113834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 153842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1402601 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 579245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 566996 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2548842 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1402601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47222898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 151948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1736545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51030049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 116858 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 151948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268806 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1400505 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 585120 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 563351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2548976 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1400505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47314780 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 113834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2296545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 116858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2294965 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 153842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2293334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53483126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690868 # Number of read requests accepted -system.physmem.writeReqs 811684 # Number of write requests accepted -system.physmem.readBursts 15690868 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811684 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004214848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue -system.physmem.bytesWritten 6724608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134021920 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6706696 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706598 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 980391 # Per bank write bursts -system.physmem.perBankRdBursts::1 980206 # Per bank write bursts -system.physmem.perBankRdBursts::2 980222 # Per bank write bursts -system.physmem.perBankRdBursts::3 980428 # Per bank write bursts -system.physmem.perBankRdBursts::4 986950 # Per bank write bursts -system.physmem.perBankRdBursts::5 980708 # Per bank write bursts -system.physmem.perBankRdBursts::6 980611 # Per bank write bursts -system.physmem.perBankRdBursts::7 980420 # Per bank write bursts -system.physmem.perBankRdBursts::8 980615 # Per bank write bursts -system.physmem.perBankRdBursts::9 980431 # Per bank write bursts -system.physmem.perBankRdBursts::10 979815 # Per bank write bursts -system.physmem.perBankRdBursts::11 979544 # Per bank write bursts -system.physmem.perBankRdBursts::12 980153 # Per bank write bursts -system.physmem.perBankRdBursts::13 980076 # Per bank write bursts -system.physmem.perBankRdBursts::14 980177 # Per bank write bursts -system.physmem.perBankRdBursts::15 980110 # Per bank write bursts -system.physmem.perBankWrBursts::0 6626 # Per bank write bursts -system.physmem.perBankWrBursts::1 6496 # Per bank write bursts -system.physmem.perBankWrBursts::2 6497 # Per bank write bursts -system.physmem.perBankWrBursts::3 6558 # Per bank write bursts -system.physmem.perBankWrBursts::4 6634 # Per bank write bursts -system.physmem.perBankWrBursts::5 6937 # Per bank write bursts -system.physmem.perBankWrBursts::6 6920 # Per bank write bursts -system.physmem.perBankWrBursts::7 6772 # Per bank write bursts -system.physmem.perBankWrBursts::8 6893 # Per bank write bursts -system.physmem.perBankWrBursts::9 6718 # Per bank write bursts -system.physmem.perBankWrBursts::10 6212 # Per bank write bursts -system.physmem.perBankWrBursts::11 6014 # Per bank write bursts -system.physmem.perBankWrBursts::12 6499 # Per bank write bursts -system.physmem.perBankWrBursts::13 6274 # Per bank write bursts -system.physmem.perBankWrBursts::14 6516 # Per bank write bursts -system.physmem.perBankWrBursts::15 6506 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 151948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2299897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53579025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690721 # Number of read requests accepted +system.physmem.writeReqs 811486 # Number of write requests accepted +system.physmem.readBursts 15690721 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811486 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004205504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue +system.physmem.bytesWritten 6711360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134013152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6694024 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706602 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4522 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 980414 # Per bank write bursts +system.physmem.perBankRdBursts::1 980046 # Per bank write bursts +system.physmem.perBankRdBursts::2 979991 # Per bank write bursts +system.physmem.perBankRdBursts::3 980262 # Per bank write bursts +system.physmem.perBankRdBursts::4 986671 # Per bank write bursts +system.physmem.perBankRdBursts::5 980424 # Per bank write bursts +system.physmem.perBankRdBursts::6 980568 # Per bank write bursts +system.physmem.perBankRdBursts::7 980428 # Per bank write bursts +system.physmem.perBankRdBursts::8 980784 # Per bank write bursts +system.physmem.perBankRdBursts::9 980432 # Per bank write bursts +system.physmem.perBankRdBursts::10 979731 # Per bank write bursts +system.physmem.perBankRdBursts::11 979594 # Per bank write bursts +system.physmem.perBankRdBursts::12 980346 # Per bank write bursts +system.physmem.perBankRdBursts::13 980257 # Per bank write bursts +system.physmem.perBankRdBursts::14 980396 # Per bank write bursts +system.physmem.perBankRdBursts::15 980367 # Per bank write bursts +system.physmem.perBankWrBursts::0 6649 # Per bank write bursts +system.physmem.perBankWrBursts::1 6328 # Per bank write bursts +system.physmem.perBankWrBursts::2 6318 # Per bank write bursts +system.physmem.perBankWrBursts::3 6427 # Per bank write bursts +system.physmem.perBankWrBursts::4 6389 # Per bank write bursts +system.physmem.perBankWrBursts::5 6673 # Per bank write bursts +system.physmem.perBankWrBursts::6 6856 # Per bank write bursts +system.physmem.perBankWrBursts::7 6766 # Per bank write bursts +system.physmem.perBankWrBursts::8 7040 # Per bank write bursts +system.physmem.perBankWrBursts::9 6684 # Per bank write bursts +system.physmem.perBankWrBursts::10 6144 # Per bank write bursts +system.physmem.perBankWrBursts::11 6041 # Per bank write bursts +system.physmem.perBankWrBursts::12 6664 # Per bank write bursts +system.physmem.perBankWrBursts::13 6480 # Per bank write bursts +system.physmem.perBankWrBursts::14 6708 # Per bank write bursts +system.physmem.perBankWrBursts::15 6698 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2631266900000 # Total gap between requests +system.physmem.totGap 2626157242500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6664 # Read request sizes (log2) -system.physmem.readPktSize::3 15532032 # Read request sizes (log2) +system.physmem.readPktSize::2 6644 # Read request sizes (log2) +system.physmem.readPktSize::3 15532042 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152172 # Read request sizes (log2) +system.physmem.readPktSize::6 152035 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57666 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1139961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 982153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 987606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1093203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 997403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1062031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2774379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2684271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3510460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 111897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 101929 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 96137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 92760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57468 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1139192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 982322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 987642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1099516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 997956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1065450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2766854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2672571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3490866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 121692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 109210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 101989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -169,39 +169,39 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 317 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5638 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -233,350 +233,349 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1040545 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.548041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.383017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 204.411888 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22983 2.21% 2.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22832 2.19% 4.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9281 0.89% 5.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2277 0.22% 5.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2320 0.22% 5.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1623 0.16% 5.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9470 0.91% 6.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 703 0.07% 6.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 969056 93.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1040545 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6005 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2612.962531 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 47489.703553 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 5977 99.53% 99.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 11 0.18% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.77% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 3 0.05% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1040256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.796235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.926694 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 203.945376 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22813 2.19% 2.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22914 2.20% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8969 0.86% 5.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2415 0.23% 5.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2270 0.22% 5.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1819 0.17% 5.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9086 0.87% 6.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 877 0.08% 6.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 969093 93.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1040256 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5997 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2616.425880 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 48628.845120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 5973 99.60% 99.60% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 7 0.12% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 4 0.07% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6005 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.497419 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.315574 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.169730 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 7 0.12% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 6 0.10% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 6 0.10% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 4 0.07% 0.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 3 0.05% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.02% 0.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 3 0.05% 0.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 3 0.05% 0.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 4 0.07% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.05% 0.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 4 0.07% 0.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 8 0.13% 0.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 3 0.05% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 4 0.07% 0.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 16 0.27% 1.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1890 31.47% 32.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 59 0.98% 33.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3765 62.70% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 21 0.35% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 14 0.23% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 16 0.27% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 19 0.32% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 20 0.33% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 12 0.20% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.10% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 23 0.38% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 21 0.35% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 18 0.30% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 14 0.23% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 10 0.17% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 11 0.18% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 11 0.18% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6005 # Writes before turning the bus around for reads -system.physmem.totQLat 402822623250 # Total ticks spent queuing -system.physmem.totMemAccLat 697026192000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454285000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25672.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5997 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5997 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.486243 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.330739 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.155795 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 3 0.05% 0.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 3 0.05% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 4 0.07% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 5 0.08% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 8 0.13% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.02% 0.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 4 0.07% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 6 0.10% 0.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 2 0.03% 0.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 3 0.05% 0.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 2 0.03% 0.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 11 0.18% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2055 34.27% 35.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 30 0.50% 35.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3613 60.25% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 37 0.62% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 21 0.35% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 16 0.27% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.23% 97.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 18 0.30% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.22% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 29 0.48% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 18 0.30% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 15 0.25% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 9 0.15% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 11 0.18% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 15 0.25% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 16 0.27% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 11 0.18% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5997 # Writes before turning the bus around for reads +system.physmem.totQLat 404022182250 # Total ticks spent queuing +system.physmem.totMemAccLat 698223013500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78453555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25749.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44422.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44499.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 382.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.03 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.00 # Data bus utilization in percentage -system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.01 # Data bus utilization in percentage +system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.68 # Average write queue length when enqueuing -system.physmem.readRowHits 14667283 # Number of row buffer hits during reads -system.physmem.writeRowHits 88101 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.57 # Average read queue length when enqueuing +system.physmem.avgWrQLen 16.75 # Average write queue length when enqueuing +system.physmem.readRowHits 14667428 # Number of row buffer hits during reads +system.physmem.writeRowHits 87892 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.84 # Row buffer hit rate for writes -system.physmem.avgGap 159446.06 # Average gap between requests +system.physmem.writeRowHitRate 83.80 # Row buffer hit rate for writes +system.physmem.avgGap 159139.76 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2257272287500 # Time in different power states -system.physmem.memoryStateTime::REF 87863880000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2253794386750 # Time in different power states +system.physmem.memoryStateTime::REF 87693060000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 286133845000 # Time in different power states +system.physmem.memoryStateTime::ACT 284666999500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54394584 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743630 # Transaction distribution -system.membus.trans_dist::ReadResp 16743630 # Transaction distribution +system.membus.throughput 54492260 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743274 # Transaction distribution +system.membus.trans_dist::ReadResp 16743274 # Transaction distribution system.membus.trans_dist::WriteReq 763389 # Transaction distribution system.membus.trans_dist::WriteResp 763389 # Transaction distribution -system.membus.trans_dist::Writeback 57666 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution -system.membus.trans_dist::ReadExReq 131349 # Transaction distribution -system.membus.trans_dist::ReadExResp 131349 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383092 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57468 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution +system.membus.trans_dist::ReadExReq 131560 # Transaction distribution +system.membus.trans_dist::ReadExResp 131560 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383096 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892408 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1891926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4278894 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343436 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390550 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35342958 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390558 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472360 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18870654 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16450920 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18849222 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143126910 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143126910 # Total data (bytes) +system.membus.tot_pkt_size::total 143105478 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143105478 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225776000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225841000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3753500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3816000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171055500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171677500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4987830629 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4988493167 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 38455776750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 38432312250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62060 # number of replacements -system.l2c.tags.tagsinuse 51620.522057 # Cycle average of tags in use -system.l2c.tags.total_refs 1699511 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127448 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.334937 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2576403565500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38224.293292 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2572.111888 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3079.413643 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4449.101058 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3295.601290 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583256 # Average percentage of cache occupancy +system.l2c.tags.replacements 61927 # number of replacements +system.l2c.tags.tagsinuse 50918.981702 # Cycle average of tags in use +system.l2c.tags.total_refs 1698761 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127310 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.343500 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574018004500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37920.667518 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2858.981429 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3190.441154 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4136.744409 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2812.146305 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.578623 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.039247 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046988 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.043625 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048682 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.067888 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050287 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787667 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65388 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2135 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6611 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56587 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.997742 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17278044 # Number of tag accesses -system.l2c.tags.data_accesses 17278044 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 10108 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3664 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 418356 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 187332 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9807 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3568 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 426125 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 183124 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242084 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596476 # number of Writeback hits -system.l2c.Writeback_hits::total 596476 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.063122 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.042910 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.776962 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2167 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6500 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56664 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17277278 # Number of tag accesses +system.l2c.tags.data_accesses 17277278 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9702 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 462087 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 188003 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9966 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3602 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 382555 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 182697 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242114 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596521 # number of Writeback hits +system.l2c.Writeback_hits::total 596521 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57771 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56762 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114533 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 10108 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3664 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 418356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 245103 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9807 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3568 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 426125 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 239886 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356617 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 10108 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3664 # number of overall hits -system.l2c.overall_hits::cpu0.inst 418356 # number of overall hits -system.l2c.overall_hits::cpu0.data 245103 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9807 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3568 # number of overall hits -system.l2c.overall_hits::cpu1.inst 426125 # number of overall hits -system.l2c.overall_hits::cpu1.data 239886 # number of overall hits -system.l2c.overall_hits::total 1356617 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 60509 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 53980 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114489 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9702 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3502 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 462087 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 248512 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9966 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3602 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 382555 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 236677 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356603 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9702 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3502 # number of overall hits +system.l2c.overall_hits::cpu0.inst 462087 # number of overall hits +system.l2c.overall_hits::cpu0.data 248512 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 9966 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3602 # number of overall hits +system.l2c.overall_hits::cpu1.inst 382555 # number of overall hits +system.l2c.overall_hits::cpu1.data 236677 # number of overall hits +system.l2c.overall_hits::total 1356603 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4266 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5262 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4381 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5534 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6325 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4967 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20823 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1468 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1421 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2889 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 66168 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 66809 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132977 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 6235 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4322 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20475 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1413 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1464 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2877 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 65455 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 67750 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133205 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 4266 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 71430 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 4381 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 70989 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6325 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 71776 # number of demand (read+write) misses -system.l2c.demand_misses::total 153800 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6235 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 72072 # number of demand (read+write) misses +system.l2c.demand_misses::total 153680 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 4266 # number of overall misses -system.l2c.overall_misses::cpu0.data 71430 # number of overall misses +system.l2c.overall_misses::cpu0.inst 4381 # number of overall misses +system.l2c.overall_misses::cpu0.data 70989 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6325 # number of overall misses -system.l2c.overall_misses::cpu1.data 71776 # number of overall misses -system.l2c.overall_misses::total 153800 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6235 # number of overall misses +system.l2c.overall_misses::cpu1.data 72072 # number of overall misses +system.l2c.overall_misses::total 153680 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 299478000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 388418000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 310394250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 412660750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 441554500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 374768000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1504457250 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 209991 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 255989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4604837922 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4645007200 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9249845122 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 435283750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 322856500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1481434000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 232990 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4532234420 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4730173185 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9262407605 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 299478000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4993255922 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 310394250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4944895170 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 441554500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 5019775200 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10754302372 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 435283750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 5053029685 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10743841605 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 299478000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4993255922 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 310394250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4944895170 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 441554500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 5019775200 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10754302372 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 10108 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3666 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 422622 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 192594 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9808 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3568 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 432450 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 188091 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1262907 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 596476 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 596476 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1483 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1432 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2915 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 123939 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 123571 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247510 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 10108 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3666 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 422622 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 316533 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9808 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3568 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 432450 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 311662 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1510417 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 10108 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3666 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 422622 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 316533 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9808 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3568 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 432450 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 311662 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1510417 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000546 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.010094 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.027322 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000102 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014626 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.026407 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016488 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989885 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992318 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991081 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.533876 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.540653 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.537259 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000546 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.010094 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.225664 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000102 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014626 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.230301 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.101826 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000546 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.010094 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.225664 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000102 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014626 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.230301 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.101826 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu1.inst 435283750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 5053029685 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10743841605 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9702 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3504 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 466468 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 193537 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 9967 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3602 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 388790 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 187019 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1262589 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 596521 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 596521 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1428 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1475 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2903 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 125964 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 121730 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247694 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9702 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3504 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 466468 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 319501 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9967 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3602 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 388790 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 308749 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1510283 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9702 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3504 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 466468 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 319501 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9967 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3602 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 388790 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 308749 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1510283 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000571 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.009392 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.028594 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016037 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.023110 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016217 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989496 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992542 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991044 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.519633 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.556560 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.537780 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009392 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.222187 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016037 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.233432 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.101756 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009392 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.222187 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016037 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.233432 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.101756 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70201.125176 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73815.659445 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70850.091303 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 74568.259848 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 69810.988142 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75451.580431 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 72249.783893 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 143.045640 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 180.147080 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 161.294566 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69593.125408 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69526.668563 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69559.736812 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 69812.951083 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 74700.717261 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 72353.308913 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 164.536447 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 159.146175 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 161.793535 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69241.989458 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69818.054391 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 69534.984460 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 70201.125176 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 69904.184824 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 70850.091303 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 69657.202806 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 69810.988142 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 69936.680785 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 69923.942601 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 69812.951083 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 70110.856990 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 69910.473744 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 70201.125176 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 69904.184824 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 70850.091303 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 69657.202806 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 69810.988142 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 69936.680785 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 69923.942601 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 69812.951083 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 70110.856990 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 69910.473744 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -585,127 +584,127 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57666 # number of writebacks -system.l2c.writebacks::total 57666 # number of writebacks +system.l2c.writebacks::writebacks 57468 # number of writebacks +system.l2c.writebacks::total 57468 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 4266 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5262 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 4381 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5534 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6325 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4967 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 20823 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1468 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1421 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2889 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 66168 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 66809 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 132977 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6235 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4322 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 20475 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1413 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1464 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2877 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 65455 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 67750 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133205 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 4266 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 71430 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 4381 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 70989 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6325 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 71776 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153800 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6235 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 72072 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 153680 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 4266 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 71430 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 4381 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 70989 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6325 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 71776 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153800 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6235 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 72072 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 153680 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 245455500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 322888500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 254926750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 343694250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 361377500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312814000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1242736750 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14681468 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14215421 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 28896889 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3759009578 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3789807300 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7548816878 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 356241750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 268891500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1223955500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14131413 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14641964 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 28773377 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3694483580 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3862282315 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7556765895 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 245455500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4081898078 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 254926750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4038177830 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 361377500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4102621300 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8791553628 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 356241750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4131173815 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8780721395 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 245455500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4081898078 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 254926750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4038177830 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 361377500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4102621300 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8791553628 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 349718500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83155205750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83528725500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167033649750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8440426101 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8262522003 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16702948104 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 349718500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91595631851 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91791247503 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183736597854 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000546 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010094 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027322 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000102 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014626 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026407 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016488 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989885 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992318 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991081 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.533876 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.540653 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537259 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000546 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010094 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.225664 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000102 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014626 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.230301 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101826 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000546 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010094 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.225664 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000102 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014626 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.230301 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101826 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 356241750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4131173815 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8780721395 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 349507750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83968607250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82715661500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167033776500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8327021074 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8376108487 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16703129561 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 349507750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92295628324 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91091769987 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183736906061 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000571 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009392 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028594 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016037 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023110 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016217 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989496 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992542 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991044 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.519633 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.556560 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537780 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009392 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.222187 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016037 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.233432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101756 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009392 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.222187 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016037 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.233432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101756 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57537.623066 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61362.314709 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58189.169139 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62105.936032 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57134.782609 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62978.457822 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59680.965759 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57135.805934 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62214.599722 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59778.046398 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.814919 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.384562 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56810.083092 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56725.999491 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56767.838634 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.341530 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.173792 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56443.107173 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57007.857048 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56730.347172 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57537.623066 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57145.430183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58189.169139 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56884.557185 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57134.782609 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57158.678388 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57162.247256 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57135.805934 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57320.094003 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57136.396376 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57537.623066 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57145.430183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58189.169139 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56884.557185 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57134.782609 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57158.678388 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57162.247256 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57135.805934 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57320.094003 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57136.396376 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -724,47 +723,47 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52759012 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471877 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471877 # Transaction distribution +system.toL2Bus.throughput 52868072 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471434 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471434 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763389 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763389 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596476 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2915 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2915 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247510 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247510 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725028 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753762 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20291 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50582 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549663 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54751132 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83793442 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138653174 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138653174 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 170100 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808682000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 596521 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2903 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2903 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247694 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247694 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753877 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20010 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 49988 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549283 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54763036 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83799850 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 78676 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138669986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138669986 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 170112 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808749000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865303000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3866196743 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420412121 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4420580083 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13057000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12904000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30666250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30319250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48131413 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715394 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715394 # Transaction distribution +system.iobus.throughput 48225066 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715396 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715396 # Transaction distribution system.iobus.trans_dist::WriteReq 8184 # Transaction distribution system.iobus.trans_dist::WriteResp 8184 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7948 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -784,14 +783,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383092 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383096 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447156 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447160 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15896 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -811,18 +810,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390550 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390558 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646806 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646806 # Total data (bytes) +system.iobus.tot_pkt_size::total 126646814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646814 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3979000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -864,9 +863,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374908000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374912000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 39139813250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 39164946750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -891,25 +890,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7447963 # DTB read hits -system.cpu0.dtb.read_misses 7119 # DTB read misses -system.cpu0.dtb.write_hits 5549645 # DTB write hits -system.cpu0.dtb.write_misses 1815 # DTB write misses -system.cpu0.dtb.flush_tlb 2495 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 6652404 # DTB read hits +system.cpu0.dtb.read_misses 6867 # DTB read misses +system.cpu0.dtb.write_hits 5702862 # DTB write hits +system.cpu0.dtb.write_misses 1758 # DTB write misses +system.cpu0.dtb.flush_tlb 2489 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6552 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6327 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 129 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 230 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7455082 # DTB read accesses -system.cpu0.dtb.write_accesses 5551460 # DTB write accesses +system.cpu0.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6659271 # DTB read accesses +system.cpu0.dtb.write_accesses 5704620 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12997608 # DTB hits -system.cpu0.dtb.misses 8934 # DTB misses -system.cpu0.dtb.accesses 13006542 # DTB accesses +system.cpu0.dtb.hits 12355266 # DTB hits +system.cpu0.dtb.misses 8625 # DTB misses +system.cpu0.dtb.accesses 12363891 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -931,160 +930,162 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30500446 # ITB inst hits -system.cpu0.itb.inst_misses 3756 # ITB inst misses +system.cpu0.itb.inst_hits 30639417 # ITB inst hits +system.cpu0.itb.inst_misses 3605 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2495 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2489 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2854 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2770 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30504202 # ITB inst accesses -system.cpu0.itb.hits 30500446 # DTB hits -system.cpu0.itb.misses 3756 # DTB misses -system.cpu0.itb.accesses 30504202 # DTB accesses -system.cpu0.numCycles 2629256644 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30643022 # ITB inst accesses +system.cpu0.itb.hits 30639417 # DTB hits +system.cpu0.itb.misses 3605 # DTB misses +system.cpu0.itb.accesses 30643022 # DTB accesses +system.cpu0.numCycles 2625139831 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29876886 # Number of instructions committed -system.cpu0.committedOps 37981807 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34283991 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4842 # Number of float alu accesses -system.cpu0.num_func_calls 1058651 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3976280 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34283991 # number of integer instructions -system.cpu0.num_fp_insts 4842 # number of float instructions -system.cpu0.num_int_register_reads 198984803 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36984019 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3491 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1354 # number of times the floating registers were written -system.cpu0.num_mem_refs 13572889 # number of memory refs -system.cpu0.num_load_insts 7771976 # Number of load instructions -system.cpu0.num_store_insts 5800913 # Number of store instructions -system.cpu0.num_idle_cycles 2280913483.245505 # Number of idle cycles -system.cpu0.num_busy_cycles 348343160.754495 # Number of busy cycles -system.cpu0.not_idle_fraction 0.132487 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.867513 # Percentage of idle cycles -system.cpu0.Branches 5129174 # Number of branches fetched -system.cpu0.op_class::No_OpClass 12846 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 24984996 64.70% 64.73% # Class of executed instruction -system.cpu0.op_class::IntMult 44336 0.11% 64.85% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 930 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::MemRead 7771976 20.13% 84.98% # Class of executed instruction -system.cpu0.op_class::MemWrite 5800913 15.02% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30062808 # Number of instructions committed +system.cpu0.committedOps 36081752 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 32258130 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5851 # Number of float alu accesses +system.cpu0.num_func_calls 1105626 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3807715 # number of instructions that are conditional controls +system.cpu0.num_int_insts 32258130 # number of integer instructions +system.cpu0.num_fp_insts 5851 # number of float instructions +system.cpu0.num_int_register_reads 58404320 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21560333 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4184 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1670 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 129650201 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 14353458 # number of times the CC registers were written +system.cpu0.num_mem_refs 12793226 # number of memory refs +system.cpu0.num_load_insts 6826552 # Number of load instructions +system.cpu0.num_store_insts 5966674 # Number of store instructions +system.cpu0.num_idle_cycles 2291568668.895058 # Number of idle cycles +system.cpu0.num_busy_cycles 333571162.104942 # Number of busy cycles +system.cpu0.not_idle_fraction 0.127068 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.872932 # Percentage of idle cycles +system.cpu0.Branches 5192489 # Number of branches fetched +system.cpu0.op_class::No_OpClass 12678 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 23764768 64.90% 64.94% # Class of executed instruction +system.cpu0.op_class::IntMult 45316 0.12% 65.06% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1041 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::MemRead 6826552 18.64% 83.71% # Class of executed instruction +system.cpu0.op_class::MemWrite 5966674 16.29% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 38615997 # Class of executed instruction +system.cpu0.op_class::total 36617029 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856182 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.863139 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60651276 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856694 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.796896 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 20196898250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 155.776297 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 355.086842 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.304251 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.693529 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997780 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 83036 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 856376 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.872089 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60655440 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856888 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.785727 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 19833794250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 155.467241 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 355.404848 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.303647 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.694150 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997797 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 268 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62364664 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62364664 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30077042 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30574234 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60651276 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30077042 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30574234 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60651276 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30077042 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30574234 # number of overall hits -system.cpu0.icache.overall_hits::total 60651276 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423404 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 433290 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856694 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423404 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 433290 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856694 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423404 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 433290 # number of overall misses -system.cpu0.icache.overall_misses::total 856694 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5772656000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6023287000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11795943000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5772656000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6023287000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11795943000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5772656000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6023287000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11795943000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30500446 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 31007524 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61507970 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30500446 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 31007524 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61507970 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30500446 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 31007524 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61507970 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013974 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013928 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013974 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013928 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013974 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013928 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13633.919377 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13901.283205 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13769.143942 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13633.919377 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13901.283205 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13769.143942 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13633.919377 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13901.283205 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13769.143942 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 62369216 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62369216 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 30172107 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30483333 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60655440 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30172107 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30483333 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60655440 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30172107 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30483333 # number of overall hits +system.cpu0.icache.overall_hits::total 60655440 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467310 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 389578 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 856888 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467310 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 389578 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 856888 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467310 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 389578 # number of overall misses +system.cpu0.icache.overall_misses::total 856888 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6355213744 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5449642249 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11804855993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6355213744 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 5449642249 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11804855993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6355213744 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 5449642249 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11804855993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30639417 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 30872911 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61512328 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30639417 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 30872911 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61512328 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30639417 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 30872911 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61512328 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015252 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012619 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015252 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012619 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015252 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012619 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13599.567191 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13988.578023 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13776.428183 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13599.567191 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13988.578023 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13776.428183 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13599.567191 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13988.578023 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13776.428183 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1093,244 +1094,280 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 423404 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 433290 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856694 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 423404 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 433290 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856694 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 423404 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 433290 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 856694 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4924249000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5154307000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10078556000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4924249000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5154307000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10078556000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4924249000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5154307000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10078556000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 441046000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 441046000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 441046000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 441046000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013974 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013928 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013974 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013928 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013974 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013928 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11630.142842 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.744190 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11764.475997 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11630.142842 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.744190 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11764.475997 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11630.142842 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.744190 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11764.475997 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467310 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 389578 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 856888 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 467310 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 389578 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 856888 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 467310 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 389578 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 856888 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5418947256 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 4668092751 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10087040007 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5418947256 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 4668092751 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10087040007 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5418947256 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 4668092751 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10087040007 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 440846250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 440846250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 440846250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 440846250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015252 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012619 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013930 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015252 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.012619 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013930 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015252 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.012619 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013930 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.043860 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11982.434201 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11771.713464 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.043860 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11982.434201 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11771.713464 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.043860 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11982.434201 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11771.713464 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627683 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.876343 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23661001 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628195 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.665058 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 669376250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 147.481748 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 364.394596 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.288050 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.711708 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 627738 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.876206 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21798920 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628250 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.697843 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 154.066297 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 357.809909 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.300911 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.698847 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999758 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 97784979 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 97784979 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6545596 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6653610 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13199206 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4917377 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 5057557 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9974934 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 119123 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117066 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236189 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125242 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 122515 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247757 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11462973 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11711167 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23174140 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11462973 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11711167 # number of overall hits -system.cpu0.dcache.overall_hits::total 23174140 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 186473 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 182643 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 369116 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 125422 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 125003 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250425 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6121 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5448 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11569 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 311895 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 307646 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 619541 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 311895 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 307646 # number of overall misses -system.cpu0.dcache.overall_misses::total 619541 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2771059250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2705059750 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5476119000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5617953546 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5645844221 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11263797767 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82277250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 78257750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 160535000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8389012796 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 8350903971 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 16739916767 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8389012796 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 8350903971 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 16739916767 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6732069 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6836253 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13568322 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5042799 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5182560 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10225359 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125244 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 122514 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247758 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125242 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 122515 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247757 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11774868 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12018813 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23793681 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11774868 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12018813 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23793681 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027699 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026717 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027204 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024872 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024120 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024491 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048873 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044468 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046695 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026488 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025597 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026038 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026488 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025597 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026038 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14860.377910 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14810.640156 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14835.767076 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44792.409195 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45165.669792 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44978.727232 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13441.798726 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14364.491557 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13876.307373 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26896.913371 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27144.523156 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 27019.869173 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26896.913371 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27144.523156 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 27019.869173 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 90464778 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 90464778 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5681092 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 5575113 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11256205 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5059212 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4912213 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9971425 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 43677 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 40519 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 84196 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 123460 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 112914 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236374 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 129861 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 117956 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247817 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10740304 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10487326 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21227630 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10783981 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10527845 # number of overall hits +system.cpu0.dcache.overall_hits::total 21311826 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 148158 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 147905 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 296063 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 129911 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 125509 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 255420 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 52745 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 47443 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100188 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6399 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5045 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11444 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 278069 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 273414 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 551483 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 330814 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 320857 # number of overall misses +system.cpu0.dcache.overall_misses::total 651671 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2069842250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2010175249 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4080017499 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5698764993 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5806816529 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11505581522 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 85596250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 73843500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 159439750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 7768607243 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 7816991778 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15585599021 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 7768607243 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 7816991778 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15585599021 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5829250 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 5723018 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 11552268 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5189123 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5037722 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10226845 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 96422 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 87962 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 184384 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 129859 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 117959 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 247818 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 129861 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 117956 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247817 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11018373 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 10760740 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21779113 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11114795 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 10848702 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21963497 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025416 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.025844 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.025628 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025035 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024914 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024975 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.547022 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.539358 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.543366 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049277 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.042769 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046179 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025237 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025408 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025322 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029763 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029576 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029671 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13970.506149 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13590.989142 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13780.909803 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43866.685600 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 46266.136524 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45045.734563 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13376.504141 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14636.967294 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13932.169696 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27937.696194 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28590.312778 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 28261.250158 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23483.308575 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24362.852542 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23916.361202 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596476 # number of writebacks -system.cpu0.dcache.writebacks::total 596476 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186473 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 182643 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369116 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 125422 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 125003 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250425 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6121 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5448 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11569 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 311895 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 307646 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619541 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 311895 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 307646 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619541 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2396807750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2338699250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4735507000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5342161454 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5370757779 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10712919233 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70030750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67311250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137342000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7738969204 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7709457029 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15448426233 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7738969204 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7709457029 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15448426233 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90834275250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91243928750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078204000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13255943399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12983118997 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239062396 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104090218649 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104227047747 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317266396 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027699 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026717 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024872 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024120 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024491 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048873 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044468 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046695 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026488 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026488 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12853.376896 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12804.757094 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12829.319238 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42593.495990 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42965.031071 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42778.952712 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.063552 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12355.222100 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11871.553289 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24812.738915 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25059.506800 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24935.276653 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24812.738915 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25059.506800 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24935.276653 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596521 # number of writebacks +system.cpu0.dcache.writebacks::total 596521 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 239 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 285 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 524 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2519 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 2304 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 4823 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2758 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 2589 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 5347 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2758 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 2589 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 5347 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 147919 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 147620 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 295539 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127392 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 123205 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250597 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 39219 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 34354 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 73573 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6399 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5045 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11444 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 275311 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 270825 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 546136 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 314530 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 305179 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619709 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1770558000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1711285000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3481843000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5304830507 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5433667721 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10738498228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 656374250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 573183000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1229557250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72793750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63702500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136496250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7075388507 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7144952721 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14220341228 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7731762757 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7718135721 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15449898478 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91728534250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90349964750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078499000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13171576426 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13067690513 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239266939 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104900110676 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103417655263 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317765939 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025375 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025794 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025583 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024550 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024456 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.406743 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.390555 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.399021 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049277 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.042769 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046179 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024987 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025168 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025076 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028298 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028130 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028215 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.780758 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.501016 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11781.331736 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41641.786823 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44102.655907 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42851.663140 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16736.129172 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16684.607324 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16712.071684 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.800906 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12626.858276 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11927.319993 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25699.621544 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26382.175652 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26038.095324 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24581.956433 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25290.520386 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24930.892529 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1364,25 +1401,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7552227 # DTB read hits -system.cpu1.dtb.read_misses 6971 # DTB read misses -system.cpu1.dtb.write_hits 5683121 # DTB write hits -system.cpu1.dtb.write_misses 1859 # DTB write misses -system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 6516178 # DTB read hits +system.cpu1.dtb.read_misses 7066 # DTB read misses +system.cpu1.dtb.write_hits 5531450 # DTB write hits +system.cpu1.dtb.write_misses 1844 # DTB write misses +system.cpu1.dtb.flush_tlb 2489 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6603 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6501 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 152 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 222 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7559198 # DTB read accesses -system.cpu1.dtb.write_accesses 5684980 # DTB write accesses +system.cpu1.dtb.perms_faults 238 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6523244 # DTB read accesses +system.cpu1.dtb.write_accesses 5533294 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13235348 # DTB hits -system.cpu1.dtb.misses 8830 # DTB misses -system.cpu1.dtb.accesses 13244178 # DTB accesses +system.cpu1.dtb.hits 12047628 # DTB hits +system.cpu1.dtb.misses 8910 # DTB misses +system.cpu1.dtb.accesses 12056538 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1404,85 +1441,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 31007524 # ITB inst hits -system.cpu1.itb.inst_misses 3606 # ITB inst misses +system.cpu1.itb.inst_hits 30872911 # ITB inst hits +system.cpu1.itb.inst_misses 3673 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2489 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2820 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2794 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31011130 # ITB inst accesses -system.cpu1.itb.hits 31007524 # DTB hits -system.cpu1.itb.misses 3606 # DTB misses -system.cpu1.itb.accesses 31011130 # DTB accesses -system.cpu1.numCycles 2633285995 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30876584 # ITB inst accesses +system.cpu1.itb.hits 30872911 # DTB hits +system.cpu1.itb.misses 3673 # DTB misses +system.cpu1.itb.accesses 30876584 # DTB accesses +system.cpu1.numCycles 2627183277 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30336967 # Number of instructions committed -system.cpu1.committedOps 38639043 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34937438 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5427 # Number of float alu accesses -system.cpu1.num_func_calls 1081754 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3973481 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34937438 # number of integer instructions -system.cpu1.num_fp_insts 5427 # number of float instructions -system.cpu1.num_int_register_reads 202463130 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37550545 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4002 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1426 # number of times the floating registers were written -system.cpu1.num_mem_refs 13827657 # number of memory refs -system.cpu1.num_load_insts 7892397 # Number of load instructions -system.cpu1.num_store_insts 5935260 # Number of store instructions -system.cpu1.num_idle_cycles 2291893093.755996 # Number of idle cycles -system.cpu1.num_busy_cycles 341392901.244004 # Number of busy cycles -system.cpu1.not_idle_fraction 0.129645 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.870355 # Percentage of idle cycles -system.cpu1.Branches 5180924 # Number of branches fetched -system.cpu1.op_class::No_OpClass 15672 0.04% 0.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 25411566 64.66% 64.70% # Class of executed instruction -system.cpu1.op_class::IntMult 43588 0.11% 64.81% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1181 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::MemRead 7892397 20.08% 84.90% # Class of executed instruction -system.cpu1.op_class::MemWrite 5935260 15.10% 100.00% # Class of executed instruction +system.cpu1.committedInsts 30155336 # Number of instructions committed +system.cpu1.committedOps 35837142 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 32021976 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4418 # Number of float alu accesses +system.cpu1.num_func_calls 1035067 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3744201 # number of instructions that are conditional controls +system.cpu1.num_int_insts 32021976 # number of integer instructions +system.cpu1.num_fp_insts 4418 # number of float instructions +system.cpu1.num_int_register_reads 57765753 # number of times the integer registers were read +system.cpu1.num_int_register_writes 21325005 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3309 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1110 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 128250854 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 14653287 # number of times the CC registers were written +system.cpu1.num_mem_refs 12466012 # number of memory refs +system.cpu1.num_load_insts 6694911 # Number of load instructions +system.cpu1.num_store_insts 5771101 # Number of store instructions +system.cpu1.num_idle_cycles 2287259017.662607 # Number of idle cycles +system.cpu1.num_busy_cycles 339924259.337393 # Number of busy cycles +system.cpu1.not_idle_fraction 0.129387 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.870613 # Percentage of idle cycles +system.cpu1.Branches 5118153 # Number of branches fetched +system.cpu1.op_class::No_OpClass 15840 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 23832212 65.55% 65.59% # Class of executed instruction +system.cpu1.op_class::IntMult 42672 0.12% 65.71% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1070 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::MemRead 6694911 18.41% 84.13% # Class of executed instruction +system.cpu1.op_class::MemWrite 5771101 15.87% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 39299664 # Class of executed instruction +system.cpu1.op_class::total 36357806 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1501,10 +1540,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1779915025250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1779915025250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1781125703750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1781125703750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1781125703750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1781125703750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |