diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/fs/10.linux-boot/ref/arm | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
12 files changed, 10271 insertions, 9249 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index d132fd20b..25f2809e1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -188,6 +199,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.checker.dtb +eventq_index=0 exitOnError=false function_trace=false function_trace_start=0 @@ -212,18 +224,21 @@ workload= [system.cpu.checker.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[5] [system.cpu.checker.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -242,18 +257,21 @@ midr=890224640 [system.cpu.checker.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[4] [system.cpu.checker.tracer] type=ExeTracer +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -261,6 +279,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -283,18 +302,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -303,15 +325,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -320,16 +345,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -338,22 +366,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -362,22 +394,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -386,10 +422,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -398,124 +436,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -524,10 +583,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -536,16 +597,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -554,10 +618,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -568,6 +634,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -590,14 +657,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -616,12 +686,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -632,6 +704,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -654,12 +727,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -669,19 +744,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -694,6 +773,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -716,6 +796,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -723,6 +804,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -734,6 +816,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -760,6 +843,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -771,19 +855,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -793,6 +881,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -802,6 +891,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -830,6 +920,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -839,8 +930,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -852,6 +975,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -867,6 +991,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -881,6 +1007,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -890,6 +1017,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -911,8 +1039,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -921,6 +1051,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -931,6 +1062,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -941,6 +1073,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -951,6 +1084,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -965,6 +1099,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -978,6 +1113,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -995,6 +1131,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1007,6 +1144,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1018,6 +1156,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1028,6 +1167,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1040,6 +1180,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1053,6 +1194,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1063,6 +1205,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1073,6 +1216,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1083,6 +1227,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1095,6 +1240,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1109,6 +1255,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1121,6 +1268,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1135,6 +1283,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1145,6 +1294,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1155,6 +1305,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1165,6 +1316,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1173,6 +1325,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1180,11 +1333,13 @@ port=3456 [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 8cfdfc3f7..d7c49d42e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525141 # Number of seconds simulated -sim_ticks 2525141046500 # Number of ticks simulated -final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525132 # Number of seconds simulated +sim_ticks 2525131633500 # Number of ticks simulated +final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50522 # Simulator instruction rate (inst/s) -host_op_rate 65007 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2115457252 # Simulator tick rate (ticks/s) -host_mem_usage 427804 # Number of bytes of host memory used -host_seconds 1193.66 # Real time elapsed on the host -sim_insts 60305756 # Number of instructions simulated -sim_ops 77596741 # Number of ops (including micro ops) simulated +host_inst_rate 41051 # Simulator instruction rate (inst/s) +host_op_rate 52821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1718892257 # Simulator tick rate (ticks/s) +host_mem_usage 447424 # Number of bytes of host memory used +host_seconds 1469.05 # Real time elapsed on the host +sim_insts 60305678 # Number of instructions simulated +sim_ops 77596684 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15096843 # Number of read requests accepted -system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.writeReqs 813149 # Number of write requests accepted system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943582 # Per bank write bursts -system.physmem.perBankRdBursts::1 943145 # Per bank write bursts -system.physmem.perBankRdBursts::2 939291 # Per bank write bursts -system.physmem.perBankRdBursts::3 939307 # Per bank write bursts -system.physmem.perBankRdBursts::4 943115 # Per bank write bursts -system.physmem.perBankRdBursts::5 943141 # Per bank write bursts -system.physmem.perBankRdBursts::6 939138 # Per bank write bursts -system.physmem.perBankRdBursts::7 938546 # Per bank write bursts -system.physmem.perBankRdBursts::8 943996 # Per bank write bursts -system.physmem.perBankRdBursts::9 943390 # Per bank write bursts -system.physmem.perBankRdBursts::10 938426 # Per bank write bursts -system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943580 # Per bank write bursts +system.physmem.perBankRdBursts::1 943152 # Per bank write bursts +system.physmem.perBankRdBursts::2 939288 # Per bank write bursts +system.physmem.perBankRdBursts::3 939310 # Per bank write bursts +system.physmem.perBankRdBursts::4 943113 # Per bank write bursts +system.physmem.perBankRdBursts::5 943139 # Per bank write bursts +system.physmem.perBankRdBursts::6 939134 # Per bank write bursts +system.physmem.perBankRdBursts::7 938551 # Per bank write bursts +system.physmem.perBankRdBursts::8 944000 # Per bank write bursts +system.physmem.perBankRdBursts::9 943392 # Per bank write bursts +system.physmem.perBankRdBursts::10 938425 # Per bank write bursts +system.physmem.perBankRdBursts::11 937973 # Per bank write bursts system.physmem.perBankRdBursts::12 943928 # Per bank write bursts -system.physmem.perBankRdBursts::13 943533 # Per bank write bursts -system.physmem.perBankRdBursts::14 939234 # Per bank write bursts -system.physmem.perBankRdBursts::15 938672 # Per bank write bursts -system.physmem.perBankWrBursts::0 6704 # Per bank write bursts -system.physmem.perBankWrBursts::1 6457 # Per bank write bursts -system.physmem.perBankWrBursts::2 6598 # Per bank write bursts -system.physmem.perBankWrBursts::3 6635 # Per bank write bursts -system.physmem.perBankWrBursts::4 6561 # Per bank write bursts -system.physmem.perBankWrBursts::5 6794 # Per bank write bursts -system.physmem.perBankWrBursts::6 6789 # Per bank write bursts -system.physmem.perBankWrBursts::7 6723 # Per bank write bursts -system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankRdBursts::13 943534 # Per bank write bursts +system.physmem.perBankRdBursts::14 939230 # Per bank write bursts +system.physmem.perBankRdBursts::15 938669 # Per bank write bursts +system.physmem.perBankWrBursts::0 6703 # Per bank write bursts +system.physmem.perBankWrBursts::1 6464 # Per bank write bursts +system.physmem.perBankWrBursts::2 6595 # Per bank write bursts +system.physmem.perBankWrBursts::3 6634 # Per bank write bursts +system.physmem.perBankWrBursts::4 6559 # Per bank write bursts +system.physmem.perBankWrBursts::5 6792 # Per bank write bursts +system.physmem.perBankWrBursts::6 6793 # Per bank write bursts +system.physmem.perBankWrBursts::7 6730 # Per bank write bursts +system.physmem.perBankWrBursts::8 7130 # Per bank write bursts system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 6538 # Per bank write bursts -system.physmem.perBankWrBursts::11 6183 # Per bank write bursts -system.physmem.perBankWrBursts::12 7149 # Per bank write bursts -system.physmem.perBankWrBursts::13 6765 # Per bank write bursts -system.physmem.perBankWrBursts::14 7038 # Per bank write bursts -system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.perBankWrBursts::10 6539 # Per bank write bursts +system.physmem.perBankWrBursts::11 6181 # Per bank write bursts +system.physmem.perBankWrBursts::12 7151 # Per bank write bursts +system.physmem.perBankWrBursts::13 6766 # Per bank write bursts +system.physmem.perBankWrBursts::14 7035 # Per bank write bursts +system.physmem.perBankWrBursts::15 6897 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.totGap 2525130505500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 36 # Read request sizes (log2) @@ -109,26 +109,26 @@ system.physmem.writePktSize::2 754018 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59125 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59131 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -142,29 +142,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see @@ -174,521 +174,534 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11268.950798 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1000.903149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16775.480046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23607 27.41% 27.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14081 16.35% 43.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2628 3.05% 46.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2075 2.41% 49.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1317 1.53% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1250 1.45% 52.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 847 0.98% 53.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 989 1.15% 54.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 557 0.65% 54.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 603 0.70% 55.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 514 0.60% 56.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 583 0.68% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 264 0.31% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 155 0.18% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 634 0.74% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 90 0.10% 58.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 121 0.14% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 516 0.60% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 33 0.04% 59.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 269 0.31% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 22 0.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 94 0.11% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 142 0.16% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 22 0.03% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 57 0.07% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 390 0.45% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 120 0.14% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 5 0.01% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 22 0.03% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 8 0.01% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 107 0.12% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 24 0.03% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 86 0.10% 61.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 27 0.03% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 358 0.42% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 154 0.18% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 62.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 15 0.02% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 31 0.04% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 11 0.01% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 39 0.05% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 368 0.43% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 15 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 165 0.19% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 92 0.11% 63.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::41472-41479 75 0.09% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 131 0.15% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 349 0.41% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 70 0.08% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 140 0.16% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 77 0.09% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 267 0.31% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 3 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 14 0.02% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 127 0.15% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 80 0.09% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 364 0.42% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 83 0.10% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 73 0.08% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 144 0.17% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 337 0.39% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 24 0.03% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 3 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 16 0.02% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 144 0.17% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 2 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 327 0.38% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 69 0.08% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 79 0.09% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 89 0.10% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 334 0.39% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 88 0.10% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 24 0.03% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 398 0.46% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 77 0.09% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 72 0.08% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 83 0.10% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5012 5.82% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation @@ -714,15 +727,15 @@ system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation -system.physmem.totQLat 365610387500 # Total ticks spent queuing -system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation +system.physmem.totQLat 365453646000 # Total ticks spent queuing +system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks -system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks +system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s @@ -732,14 +745,14 @@ system.physmem.busUtil 3.00 # Da system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing -system.physmem.readRowHits 14986740 # Number of row buffer hits during reads -system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing +system.physmem.readRowHits 14986798 # Number of row buffer hits during reads +system.physmem.writeRowHits 93332 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes -system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes +system.physmem.avgGap 158713.50 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -752,50 +765,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54899945 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149440 # Transaction distribution -system.membus.trans_dist::ReadResp 16149440 # Transaction distribution +system.membus.throughput 54900302 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149434 # Transaction distribution +system.membus.trans_dist::ReadResp 16149434 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::Writeback 59131 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution -system.membus.trans_dist::ReadExReq 131442 # Transaction distribution -system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution +system.membus.trans_dist::ReadExReq 131448 # Transaction distribution +system.membus.trans_dist::ReadExResp 131448 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630105 # Total data (bytes) +system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630489 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -803,7 +816,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.throughput 48285786 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution @@ -913,22 +926,22 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14384905 # Number of BP lookups -system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits +system.cpu.branchPred.lookups 14384927 # Number of BP lookups +system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14986852 # DTB read hits -system.cpu.checker.dtb.read_misses 7306 # DTB read misses -system.cpu.checker.dtb.write_hits 11227410 # DTB write hits +system.cpu.checker.dtb.read_hits 14986834 # DTB read hits +system.cpu.checker.dtb.read_misses 7307 # DTB read misses +system.cpu.checker.dtb.write_hits 11227416 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -939,13 +952,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994158 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229601 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994141 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229607 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26214262 # DTB hits -system.cpu.checker.dtb.misses 9497 # DTB misses -system.cpu.checker.dtb.accesses 26223759 # DTB accesses -system.cpu.checker.itb.inst_hits 61479743 # ITB inst hits +system.cpu.checker.dtb.hits 26214250 # DTB hits +system.cpu.checker.dtb.misses 9498 # DTB misses +system.cpu.checker.dtb.accesses 26223748 # DTB accesses +system.cpu.checker.itb.inst_hits 61479663 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -962,36 +975,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61484214 # ITB inst accesses -system.cpu.checker.itb.hits 61479743 # DTB hits +system.cpu.checker.itb.inst_accesses 61484134 # ITB inst accesses +system.cpu.checker.itb.hits 61479663 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61484214 # DTB accesses -system.cpu.checker.numCycles 77882535 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61484134 # DTB accesses +system.cpu.checker.numCycles 77882476 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51179212 # DTB read hits -system.cpu.dtb.read_misses 64531 # DTB read misses -system.cpu.dtb.write_hits 11698539 # DTB write hits -system.cpu.dtb.write_misses 15837 # DTB write misses +system.cpu.dtb.read_hits 51182106 # DTB read hits +system.cpu.dtb.read_misses 64421 # DTB read misses +system.cpu.dtb.write_hits 11699698 # DTB write hits +system.cpu.dtb.write_misses 15824 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6568 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6560 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51243743 # DTB read accesses -system.cpu.dtb.write_accesses 11714376 # DTB write accesses +system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51246527 # DTB read accesses +system.cpu.dtb.write_accesses 11715522 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62877751 # DTB hits -system.cpu.dtb.misses 80368 # DTB misses -system.cpu.dtb.accesses 62958119 # DTB accesses -system.cpu.itb.inst_hits 11513998 # ITB inst hits -system.cpu.itb.inst_misses 11344 # ITB inst misses +system.cpu.dtb.hits 62881804 # DTB hits +system.cpu.dtb.misses 80245 # DTB misses +system.cpu.dtb.accesses 62962049 # DTB accesses +system.cpu.itb.inst_hits 11522583 # ITB inst hits +system.cpu.itb.inst_misses 11276 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -1000,148 +1013,148 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4962 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4956 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11525342 # ITB inst accesses -system.cpu.itb.hits 11513998 # DTB hits -system.cpu.itb.misses 11344 # DTB misses -system.cpu.itb.accesses 11525342 # DTB accesses -system.cpu.numCycles 474882944 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11533859 # ITB inst accesses +system.cpu.itb.hits 11522583 # DTB hits +system.cpu.itb.misses 11276 # DTB misses +system.cpu.itb.accesses 11533859 # DTB accesses +system.cpu.numCycles 474898657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle +system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -1154,397 +1167,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued -system.cpu.iq.rate 0.258795 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued +system.cpu.iq.rate 0.258806 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221869 # number of nop insts executed -system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed -system.cpu.iew.exec_branches 11475076 # Number of branches executed -system.cpu.iew.exec_stores 12210518 # Number of stores executed -system.cpu.iew.exec_rate 0.254424 # Inst execution rate -system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47026181 # num instructions producing a value -system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value +system.cpu.iew.exec_nop 221761 # number of nop insts executed +system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475005 # Number of branches executed +system.cpu.iew.exec_stores 12211635 # Number of stores executed +system.cpu.iew.exec_rate 0.254432 # Inst execution rate +system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47031033 # num instructions producing a value +system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456137 # Number of instructions committed -system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456059 # Number of instructions committed +system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385736 # Number of memory references committed -system.cpu.commit.loads 15654008 # Number of loads committed -system.cpu.commit.membars 403573 # Number of memory barriers committed -system.cpu.commit.branches 9961077 # Number of branches committed +system.cpu.commit.refs 27385723 # Number of memory references committed +system.cpu.commit.loads 15653991 # Number of loads committed +system.cpu.commit.membars 403571 # Number of memory barriers committed +system.cpu.commit.branches 9961071 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. -system.cpu.commit.function_calls 991208 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. +system.cpu.commit.function_calls 991207 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240636318 # The number of ROB reads -system.cpu.rob.rob_writes 195934369 # The number of ROB writes -system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305756 # Number of Instructions Simulated -system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated -system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547208472 # number of integer regfile reads -system.cpu.int_regfile_writes 87526189 # number of integer regfile writes -system.cpu.fp_regfile_reads 8624 # number of floating regfile reads -system.cpu.fp_regfile_writes 3008 # number of floating regfile writes -system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.rob.rob_reads 240665808 # The number of ROB reads +system.cpu.rob.rob_writes 195946920 # The number of ROB writes +system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305678 # Number of Instructions Simulated +system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated +system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547244885 # number of integer regfile reads +system.cpu.int_regfile_writes 87532646 # number of integer regfile writes +system.cpu.fp_regfile_reads 8511 # number of floating regfile reads +system.cpu.fp_regfile_writes 2972 # number of floating regfile writes +system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads system.cpu.misc_regfile_writes 831837 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution +system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) 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count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62740736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85535129 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41644 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 210260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148527769 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148527769 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 199672 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3129078659 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474541718 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550360089 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20171491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74593037 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980741 # number of replacements -system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 980798 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579102 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10457750 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981310 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.656928 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits -system.cpu.icache.overall_hits::total 10449649 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of 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-system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits 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miss cycles +system.cpu.icache.demand_miss_latency::total 14272429649 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 322 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.602484 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79476 # 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11584683024 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11584683024 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11584683024 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085194 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085194 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085194 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11804.891469 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11804.891469 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 64371 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid 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+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1665,161 +1678,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.replacements 643483 # number of replacements system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits -system.cpu.dcache.overall_hits::total 21010251 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses 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-system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258628 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242811 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242811 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247593 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247593 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21014112 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21014112 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21014112 # number of overall hits +system.cpu.dcache.overall_hits::total 21014112 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737297 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737297 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963410 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963410 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13576 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700707 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700707 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700707 # number of overall misses +system.cpu.dcache.overall_misses::total 3700707 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10005137822 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10005137822 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 141347559382 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 141347559382 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185728250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185728250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 206503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 206503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 151352697204 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 151352697204 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 151352697204 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 151352697204 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492781 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492781 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222038 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222038 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24714819 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714819 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24714819 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24714819 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050873 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050873 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000053 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000053 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked 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WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks +system.cpu.dcache.writebacks::total 607897 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065987 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065987 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385715 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385715 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249005 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249005 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1841,16 +1854,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 7ff8826e3..98e6f2256 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,18 +602,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=DerivO3CPU @@ -581,6 +647,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -645,6 +713,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -660,6 +729,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -682,18 +752,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -702,15 +775,18 @@ port=system.toL2Bus.slave[7] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -719,16 +795,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -737,22 +816,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -761,22 +844,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -785,10 +872,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -797,124 +886,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -923,10 +1033,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -935,16 +1047,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -953,10 +1068,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -967,6 +1084,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -989,14 +1107,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -1015,31 +1136,37 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -1052,6 +1179,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1074,6 +1202,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1083,6 +1212,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1105,6 +1235,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1112,6 +1243,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1123,6 +1255,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1149,6 +1282,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1160,19 +1294,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -1182,6 +1320,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -1191,6 +1330,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1219,6 +1359,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -1228,8 +1369,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1241,6 +1414,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -1256,6 +1430,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -1270,6 +1446,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1279,6 +1456,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1300,8 +1478,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1310,6 +1490,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1320,6 +1501,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1330,6 +1512,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1340,6 +1523,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1354,6 +1538,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1367,6 +1552,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1384,6 +1570,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1396,6 +1583,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1407,6 +1595,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1417,6 +1606,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1429,6 +1619,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1442,6 +1633,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1452,6 +1644,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1462,6 +1655,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1472,6 +1666,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1484,6 +1679,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1498,6 +1694,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1510,6 +1707,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1524,6 +1722,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1534,6 +1733,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1544,6 +1744,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1554,6 +1755,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1562,6 +1764,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1570,6 +1773,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1579,11 +1783,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 22f0dd0ff..fbdae72ae 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.104766 # Number of seconds simulated -sim_ticks 1104765949000 # Number of ticks simulated -final_tick 1104765949000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1104766159000 # Number of ticks simulated +final_tick 1104766159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62642 # Simulator instruction rate (inst/s) -host_op_rate 80640 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1123477436 # Simulator tick rate (ticks/s) -host_mem_usage 430892 # Number of bytes of host memory used -host_seconds 983.35 # Real time elapsed on the host -sim_insts 61598253 # Number of instructions simulated -sim_ops 79296895 # Number of ops (including micro ops) simulated +host_inst_rate 49697 # Simulator instruction rate (inst/s) +host_op_rate 63978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 891289209 # Simulator tick rate (ticks/s) +host_mem_usage 450492 # Number of bytes of host memory used +host_seconds 1239.51 # Real time elapsed on the host +sim_insts 61600257 # Number of instructions simulated +sim_ops 79301805 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 408192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4366132 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5251248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 409280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 408192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4268480 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu0.inst 409280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7295824 # Number of bytes written to this memory +system.physmem.bytes_written::total 7294864 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6378 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6357 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66695 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 66680 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823531 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44134945 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823516 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44134936 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 369483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3952088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 368266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4753267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53579613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 369483 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 368266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 737749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3863696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3952666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4752513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53579603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 737807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3862827 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6603954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3863696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44134945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 6603084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3862827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44134936 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 369483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3967476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 368266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7478138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60183567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 370468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3968054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7477383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60182687 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 6257980 # Number of read requests accepted -system.physmem.writeReqs 823531 # Number of write requests accepted +system.physmem.writeReqs 823516 # Number of write requests accepted system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823531 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 398200448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2310272 # Total number of bytes read from write queue -system.physmem.bytesWritten 7402624 # Total number of bytes written to DRAM +system.physmem.writeBursts 823516 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 398158784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2351936 # Total number of bytes read from write queue +system.physmem.bytesWritten 7399168 # Total number of bytes written to DRAM system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7295824 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 36098 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707850 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12605 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 391110 # Per bank write bursts -system.physmem.perBankRdBursts::1 390863 # Per bank write bursts -system.physmem.perBankRdBursts::2 386866 # Per bank write bursts -system.physmem.perBankRdBursts::3 386878 # Per bank write bursts -system.physmem.perBankRdBursts::4 391778 # Per bank write bursts -system.physmem.perBankRdBursts::5 391417 # Per bank write bursts -system.physmem.perBankRdBursts::6 386925 # Per bank write bursts -system.physmem.perBankRdBursts::7 386783 # Per bank write bursts -system.physmem.perBankRdBursts::8 391442 # Per bank write bursts -system.physmem.perBankRdBursts::9 391216 # Per bank write bursts -system.physmem.perBankRdBursts::10 386574 # Per bank write bursts -system.physmem.perBankRdBursts::11 385570 # Per bank write bursts -system.physmem.perBankRdBursts::12 390981 # Per bank write bursts -system.physmem.perBankRdBursts::13 390596 # Per bank write bursts -system.physmem.perBankRdBursts::14 386700 # Per bank write bursts -system.physmem.perBankRdBursts::15 386183 # Per bank write bursts -system.physmem.perBankWrBursts::0 7188 # Per bank write bursts -system.physmem.perBankWrBursts::1 7193 # Per bank write bursts -system.physmem.perBankWrBursts::2 7297 # Per bank write bursts -system.physmem.perBankWrBursts::3 7231 # Per bank write bursts -system.physmem.perBankWrBursts::4 7835 # Per bank write bursts -system.physmem.perBankWrBursts::5 7450 # Per bank write bursts -system.physmem.perBankWrBursts::6 7370 # Per bank write bursts -system.physmem.perBankWrBursts::7 7176 # Per bank write bursts -system.physmem.perBankWrBursts::8 7508 # Per bank write bursts -system.physmem.perBankWrBursts::9 7517 # Per bank write bursts -system.physmem.perBankWrBursts::10 6849 # Per bank write bursts -system.physmem.perBankWrBursts::11 6596 # Per bank write bursts -system.physmem.perBankWrBursts::12 7160 # Per bank write bursts -system.physmem.perBankWrBursts::13 6824 # Per bank write bursts -system.physmem.perBankWrBursts::14 7287 # Per bank write bursts -system.physmem.perBankWrBursts::15 7185 # Per bank write bursts +system.physmem.bytesWrittenSys 7294864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 36749 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707898 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12570 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 391105 # Per bank write bursts +system.physmem.perBankRdBursts::1 391040 # Per bank write bursts +system.physmem.perBankRdBursts::2 387008 # Per bank write bursts +system.physmem.perBankRdBursts::3 386856 # Per bank write bursts +system.physmem.perBankRdBursts::4 391768 # Per bank write bursts +system.physmem.perBankRdBursts::5 391357 # Per bank write bursts +system.physmem.perBankRdBursts::6 387221 # Per bank write bursts +system.physmem.perBankRdBursts::7 386642 # Per bank write bursts +system.physmem.perBankRdBursts::8 391438 # Per bank write bursts +system.physmem.perBankRdBursts::9 391160 # Per bank write bursts +system.physmem.perBankRdBursts::10 385906 # Per bank write bursts +system.physmem.perBankRdBursts::11 385319 # Per bank write bursts +system.physmem.perBankRdBursts::12 390977 # Per bank write bursts +system.physmem.perBankRdBursts::13 390642 # Per bank write bursts +system.physmem.perBankRdBursts::14 386557 # Per bank write bursts +system.physmem.perBankRdBursts::15 386235 # Per bank write bursts +system.physmem.perBankWrBursts::0 7173 # Per bank write bursts +system.physmem.perBankWrBursts::1 7194 # Per bank write bursts +system.physmem.perBankWrBursts::2 7298 # Per bank write bursts +system.physmem.perBankWrBursts::3 7217 # Per bank write bursts +system.physmem.perBankWrBursts::4 7815 # Per bank write bursts +system.physmem.perBankWrBursts::5 7451 # Per bank write bursts +system.physmem.perBankWrBursts::6 7359 # Per bank write bursts +system.physmem.perBankWrBursts::7 7185 # Per bank write bursts +system.physmem.perBankWrBursts::8 7499 # Per bank write bursts +system.physmem.perBankWrBursts::9 7507 # Per bank write bursts +system.physmem.perBankWrBursts::10 6838 # Per bank write bursts +system.physmem.perBankWrBursts::11 6616 # Per bank write bursts +system.physmem.perBankWrBursts::12 7156 # Per bank write bursts +system.physmem.perBankWrBursts::13 6834 # Per bank write bursts +system.physmem.perBankWrBursts::14 7291 # Per bank write bursts +system.physmem.perBankWrBursts::15 7179 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1104764856500 # Total gap between requests +system.physmem.totGap 1104765054500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 105 # Read request sizes (log2) @@ -126,29 +126,29 @@ system.physmem.writePktSize::2 756836 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66695 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 548369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 494073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 445478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1468713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1058783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1047686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1043195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 25416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66680 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 551365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 495534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 447275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1468617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1056766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1046048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1041328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,547 +159,563 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 71125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5702.673097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 368.783347 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 12967.835637 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25909 36.43% 36.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14850 20.88% 57.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3162 4.45% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2234 3.14% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1545 2.17% 67.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1302 1.83% 68.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 996 1.40% 70.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1191 1.67% 71.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 629 0.88% 72.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 663 0.93% 73.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 567 0.80% 74.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 536 0.75% 75.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 288 0.40% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 263 0.37% 76.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 175 0.25% 76.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 373 0.52% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 125 0.18% 77.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 132 0.19% 77.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 91 0.13% 77.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 197 0.28% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 57 0.08% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 541 0.76% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 41 0.06% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 225 0.32% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 27 0.04% 78.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 110 0.15% 79.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 22 0.03% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 16 0.02% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 61 0.09% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 267 0.38% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 16 0.02% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 40 0.06% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 17 0.02% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 50 0.07% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 11 0.02% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 22 0.03% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 7 0.01% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 43 0.06% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 4 0.01% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 15 0.02% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 8 0.01% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 32 0.04% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 30 0.04% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 157 0.22% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 6 0.01% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 17 0.02% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 2 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 36 0.05% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 17 0.02% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 7 0.01% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 7 0.01% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 8 0.01% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 39 0.05% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 6 0.01% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 181 0.25% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 9 0.01% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 12 0.02% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 12 0.02% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 102 0.14% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 17 0.02% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 25 0.04% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 7 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 11 0.02% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 5 0.01% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 19 0.03% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 161 0.23% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 13 0.02% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 9 0.01% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 14 0.02% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 3 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 16 0.02% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 18 0.03% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 5 0.01% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 8 0.01% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 5 0.01% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 150 0.21% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 2 0.00% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 12 0.02% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 13 0.02% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 95 0.13% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 7 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 23 0.03% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 70891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5720.862056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 370.371771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 12983.455583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25780 36.37% 36.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14831 20.92% 57.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3170 4.47% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2175 3.07% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1493 2.11% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1297 1.83% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1053 1.49% 70.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1149 1.62% 71.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 657 0.93% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 651 0.92% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 556 0.78% 74.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 523 0.74% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 304 0.43% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 266 0.38% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 142 0.20% 76.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 425 0.60% 76.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 119 0.17% 77.01% # Bytes accessed per row activation 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178 0.25% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 2 0.00% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 13 0.02% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 3 0.00% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 91 0.13% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 20 0.03% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 46 0.06% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 11 0.02% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 5 0.01% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 37 0.05% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 12 0.02% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 12 0.02% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 201 0.28% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 6 0.01% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 17 0.02% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 92 0.13% 81.15% # Bytes accessed per row activation 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3 0.00% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 93 0.13% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 4 0.01% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 15 0.02% 81.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 8 0.01% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 84 0.12% 81.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 5 0.01% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 9 0.01% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 5 0.01% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 19 0.03% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 7 0.01% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 138 0.19% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 4 0.01% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 11 0.02% 81.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 12 0.02% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 85 0.12% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 8 0.01% 82.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 5 0.01% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 96 0.14% 82.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6471 4 0.01% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 11 0.02% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 3 0.00% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 112 0.16% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 9 0.01% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 20 0.03% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 8 0.01% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 28 0.04% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 4 0.01% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 2 0.00% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 94 0.13% 82.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 6 0.01% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 10 0.01% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 92 0.13% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 3 0.00% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 10 0.01% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 3 0.00% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 20 0.03% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 2 0.00% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 4 0.01% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 6 0.01% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8135 1 0.00% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 249 0.35% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 83.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 31 0.04% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 16 0.02% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 3 0.00% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 75 0.11% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 93 0.13% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9415 1 0.00% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 20 0.03% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 1 0.00% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 102 0.14% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 14 0.02% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 94 0.13% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 94 0.13% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 15 0.02% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10823 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10887 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 6 0.01% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 2 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 147 0.21% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 3 0.00% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 84.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 1 0.00% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11847 1 0.00% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 79 0.11% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 162 0.23% 84.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 20 0.03% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12743 1 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 68 0.10% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 1 0.00% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 148 0.21% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13447 1 0.00% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13511 1 0.00% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 19 0.03% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 18 0.03% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 11 0.02% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 228 0.32% 85.41% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::19968-19975 68 0.10% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20103 1 0.00% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 17 0.02% 87.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 2 0.00% 87.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 157 0.22% 87.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 82 0.12% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 4 0.01% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 14 0.02% 87.81% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::25600-25607 90 0.13% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 104 0.15% 89.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 14 0.02% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 87 0.12% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 2 0.00% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 94 0.13% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.80% # Bytes accessed per row activation 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0.13% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 1 0.00% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 12 0.02% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 4 0.01% 82.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 79 0.11% 82.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 3 0.00% 82.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 3 0.00% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 2 0.00% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 32 0.05% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 4 0.01% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 266 0.38% 83.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 25 0.04% 83.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 67 0.09% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8775 3 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 85 0.12% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 19 0.03% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9287 1 0.00% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 13 0.02% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 69 0.10% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 2 0.00% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 92 0.13% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10183 1 0.00% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 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-system.physmem.bytesPerActivate::48832-48839 2 0.00% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 13 0.02% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 1979 2.78% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 75 0.11% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 86 0.12% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 74 0.10% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 73 0.10% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 3 0.00% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 16 0.02% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 9 0.01% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44608-44615 2 0.00% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 74 0.10% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 4 0.01% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 173 0.24% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 1 0.00% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 19 0.03% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 34 0.05% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 76 0.11% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 150 0.21% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 8 0.01% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 9 0.01% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 17 0.02% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 174 0.25% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 22 0.03% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 2 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 3 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 21 0.03% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 208 0.29% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 12 0.02% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 4 0.01% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 10 0.01% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 97.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2000 2.82% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49792-49799 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50048-50055 2 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::50176-50183 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50311 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50880-50887 4 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50951 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51648-51655 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51719 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 4 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51648-51655 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51904-51911 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52352-52359 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52672-52679 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 71125 # Bytes accessed per row activation -system.physmem.totQLat 151840872500 # Total ticks spent queuing -system.physmem.totMemAccLat 191562815000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 31109410000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8612532500 # Total ticks spent accessing banks -system.physmem.avgQLat 24404.33 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1384.23 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 70891 # Bytes accessed per row activation +system.physmem.totQLat 151784626000 # Total ticks spent queuing +system.physmem.totMemAccLat 191524282250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 31106155000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8633501250 # Total ticks spent accessing banks +system.physmem.avgQLat 24397.84 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1387.75 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30788.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30785.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 360.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s @@ -708,14 +724,14 @@ system.physmem.busUtil 2.87 # Da system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.06 # Average write queue length when enqueuing -system.physmem.readRowHits 6168484 # Number of row buffer hits during reads -system.physmem.writeRowHits 97939 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.13 # Average write queue length when enqueuing +system.physmem.readRowHits 6167948 # Number of row buffer hits during reads +system.physmem.writeRowHits 98004 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.66 # Row buffer hit rate for writes -system.physmem.avgGap 156006.94 # Average gap between requests +system.physmem.writeRowHitRate 84.77 # Row buffer hit rate for writes +system.physmem.avgGap 156007.30 # Average gap between requests system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 3.92 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 3.90 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -734,286 +750,286 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 62369736 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306752 # Transaction distribution -system.membus.trans_dist::ReadResp 7306752 # Transaction distribution -system.membus.trans_dist::WriteReq 767894 # Transaction distribution -system.membus.trans_dist::WriteResp 767894 # Transaction distribution -system.membus.trans_dist::Writeback 66695 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33888 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17695 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12605 # Transaction distribution -system.membus.trans_dist::ReadExReq 138070 # Transaction distribution -system.membus.trans_dist::ReadExResp 137680 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382518 # Packet count per connected master and slave (bytes) +system.membus.throughput 62368825 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306736 # Transaction distribution +system.membus.trans_dist::ReadResp 7306736 # Transaction distribution +system.membus.trans_dist::WriteReq 767886 # Transaction distribution +system.membus.trans_dist::WriteResp 767886 # Transaction distribution +system.membus.trans_dist::Writeback 66680 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33856 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17703 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12570 # Transaction distribution +system.membus.trans_dist::ReadExReq 138080 # Transaction distribution +system.membus.trans_dist::ReadExResp 137692 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382504 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971209 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366229 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366129 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555925 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389781 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16555825 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389767 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23284 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23264 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729972 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20145177 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729012 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20144183 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68903961 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68903961 # Total data (bytes) +system.membus.tot_pkt_size::total 68902967 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68902967 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487006499 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486954500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9880000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9891500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 749500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 747500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8612723499 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8614133500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4837509170 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4838543340 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13760375954 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13759512942 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) system.l2c.tags.replacements 72740 # number of replacements -system.l2c.tags.tagsinuse 53853.567584 # Cycle average of tags in use -system.l2c.tags.total_refs 1839137 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 53860.173191 # Cycle average of tags in use +system.l2c.tags.total_refs 1837966 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.334423 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 13.325933 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39512.680536 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.162068 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257969 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4009.847433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2829.767621 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.955070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3709.355619 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3778.541270 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.602916 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061185 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057656 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821740 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22065 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386342 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166614 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30647 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5089 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 590258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198399 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403772 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581386 # number of Writeback hits -system.l2c.Writeback_hits::total 581386 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 750 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2084 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48317 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58643 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22065 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386342 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214931 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5089 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 590258 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 257042 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510732 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22065 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4358 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386342 # number of overall hits -system.l2c.overall_hits::cpu0.data 214931 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30647 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5089 # number of overall hits -system.l2c.overall_hits::cpu1.inst 590258 # number of overall hits -system.l2c.overall_hits::cpu1.data 257042 # number of overall hits -system.l2c.overall_hits::total 1510732 # number of overall hits +system.l2c.tags.occ_blocks::writebacks 39518.362493 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.391068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.010261 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4016.186215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2832.215798 # Average occupied blocks per requestor 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accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567738 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567361 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098774 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098774 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62578.188661 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65201.487138 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62839.467228 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.691291 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10093.271186 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10051.992377 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.216430 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10048.609524 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10028.535613 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57372.440322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68943.264778 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63723.943645 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1204,61 +1220,61 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 136691596 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2708551 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2708550 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581386 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33382 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18023 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51405 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258959 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258959 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785985 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13547 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1193885 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4802054 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14684 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 71694 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8011498 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25134272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847315 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17444 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38184256 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47797126 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20356 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 122632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 146211713 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146211713 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4800508 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4894625900 # Layer occupancy (ticks) +system.toL2Bus.throughput 136617428 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2707473 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2707472 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767886 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767886 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 581363 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33341 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18047 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51388 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258982 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258982 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785116 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073701 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13590 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55763 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1192186 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801848 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72416 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8009257 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25105344 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847157 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17404 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88060 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38129856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47787842 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 124384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146120255 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146120255 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4810056 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4893985918 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1771371395 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1769514129 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1514575770 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1514543493 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9208452 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9260456 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34011429 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 33892454 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2689519761 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2685747678 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3237226447 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 3237154790 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9617950 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 9609448 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41300207 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41592193 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 46298101 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution -system.iobus.trans_dist::WriteReq 7950 # Transaction distribution -system.iobus.trans_dist::WriteResp 7950 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) +system.iobus.throughput 46298079 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278155 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278155 # Transaction distribution +system.iobus.trans_dist::WriteReq 7945 # Transaction distribution +system.iobus.trans_dist::WriteResp 7945 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30446 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) @@ -1281,11 +1297,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382504 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572214 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 14572200 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40164 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) @@ -1308,12 +1324,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389767 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148565 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148565 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 51148551 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148551 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21348000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1361,42 +1377,42 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374568000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374559000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16664438046 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16664463058 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6002691 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4577903 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294712 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3771820 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2913648 # Number of BTB hits +system.cpu0.branchPred.lookups 5998612 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4575425 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295221 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3794321 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2910648 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.247801 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672509 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28479 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.710642 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672923 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29222 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8905508 # DTB read hits -system.cpu0.dtb.read_misses 28991 # DTB read misses -system.cpu0.dtb.write_hits 5140500 # DTB write hits -system.cpu0.dtb.write_misses 5723 # DTB write misses +system.cpu0.dtb.read_hits 8906772 # DTB read hits +system.cpu0.dtb.read_misses 28714 # DTB read misses +system.cpu0.dtb.write_hits 5141355 # DTB write hits +system.cpu0.dtb.write_misses 5491 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1824 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 969 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 924 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 556 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8934499 # DTB read accesses -system.cpu0.dtb.write_accesses 5146223 # DTB write accesses +system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8935486 # DTB read accesses +system.cpu0.dtb.write_accesses 5146846 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14046008 # DTB hits -system.cpu0.dtb.misses 34714 # DTB misses -system.cpu0.dtb.accesses 14080722 # DTB accesses -system.cpu0.itb.inst_hits 4219281 # ITB inst hits -system.cpu0.itb.inst_misses 5089 # ITB inst misses +system.cpu0.dtb.hits 14048127 # DTB hits +system.cpu0.dtb.misses 34205 # DTB misses +system.cpu0.dtb.accesses 14082332 # DTB accesses +system.cpu0.itb.inst_hits 4217878 # ITB inst hits +system.cpu0.itb.inst_misses 5102 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1405,530 +1421,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1343 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1349 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1465 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4224370 # ITB inst accesses -system.cpu0.itb.hits 4219281 # DTB hits -system.cpu0.itb.misses 5089 # DTB misses -system.cpu0.itb.accesses 4224370 # DTB accesses -system.cpu0.numCycles 69432037 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4222980 # ITB inst accesses +system.cpu0.itb.hits 4217878 # DTB hits +system.cpu0.itb.misses 5102 # DTB misses +system.cpu0.itb.accesses 4222980 # DTB accesses +system.cpu0.numCycles 69399845 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11713503 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32019404 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6002691 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3586157 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7516730 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1449804 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 61386 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19631994 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46872 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1335943 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4217707 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157539 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41351812 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.000563 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.381156 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11707943 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32011744 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5998612 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3583571 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7516048 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1450698 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61322 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19616707 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4844 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46699 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1334001 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4216315 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157019 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2077 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41328581 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.001115 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.381687 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33842541 81.84% 81.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565579 1.37% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816874 1.98% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676358 1.64% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772843 1.87% 88.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558608 1.35% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 669211 1.62% 91.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351371 0.85% 92.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098427 7.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33820062 81.83% 81.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 563590 1.36% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816833 1.98% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 678550 1.64% 86.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773451 1.87% 88.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557877 1.35% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 667950 1.62% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351268 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3099000 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41351812 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086454 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.461162 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12216999 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20826551 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6820783 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 510850 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 976629 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935170 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64759 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40012064 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213022 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 976629 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12786291 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5985032 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12800887 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6711570 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2091403 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38907337 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 435425 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1163203 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 107 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39252215 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175728295 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 161804372 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 3955 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30935092 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8317122 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411284 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370379 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5367119 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7645996 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5688511 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1121166 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1220161 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36823164 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895382 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37236653 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80347 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6279547 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13158300 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256522 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41351812 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.900484 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514831 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41328581 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086436 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461265 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12211654 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20807916 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6822131 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 509652 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 977228 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 934234 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64577 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40012411 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212282 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 977228 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12781253 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5974864 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12788176 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6710782 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2096278 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38908722 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1870 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435924 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1167673 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 74 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39248766 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175739111 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 161807828 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3998 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30938690 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8310075 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411292 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370393 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5377655 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7648768 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5690459 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124911 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1238842 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36825251 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895403 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37248866 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80758 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6273186 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13119240 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256527 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41328581 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.901286 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.515261 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26282952 63.56% 63.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5688374 13.76% 77.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3116432 7.54% 84.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2466494 5.96% 90.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2112034 5.11% 95.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 939185 2.27% 98.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 506930 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184996 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54415 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26256934 63.53% 63.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5686623 13.76% 77.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3113893 7.53% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2469463 5.98% 90.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2128203 5.15% 95.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 923425 2.23% 98.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 509489 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 185211 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 55340 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41351812 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41328581 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27736 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 453 0.04% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842113 78.49% 81.12% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 202594 18.88% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26660 2.48% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 451 0.04% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 843359 78.54% 81.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 203361 18.94% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22326150 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46947 0.13% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22336119 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46932 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9362954 25.14% 85.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5447671 14.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9364529 25.14% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5448283 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37236653 # Type of FU issued -system.cpu0.iq.rate 0.536304 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1072896 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028813 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117004426 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44005967 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34332716 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8422 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4624 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3857 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38252914 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4421 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307648 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37248866 # Type of FU issued +system.cpu0.iq.rate 0.536728 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1073831 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028829 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117006401 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44001611 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34345325 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8483 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4644 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3871 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38265951 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4467 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306869 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1368398 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2491 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13086 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537466 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1369766 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2413 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12945 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 538318 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192854 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5939 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192768 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5933 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 976629 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4337522 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 100010 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37836354 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83498 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7645996 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5688511 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571219 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39755 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6621 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13086 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149491 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117486 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 266977 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36859042 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9220953 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 377611 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 977228 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4326370 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 99368 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37837801 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83554 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7648768 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5690459 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571361 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39650 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5884 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12945 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150463 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117241 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267704 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36870822 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9222297 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 378044 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117808 # number of nop insts executed -system.cpu0.iew.exec_refs 14621413 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4853789 # Number of branches executed -system.cpu0.iew.exec_stores 5400460 # Number of stores executed -system.cpu0.iew.exec_rate 0.530865 # Inst execution rate -system.cpu0.iew.wb_sent 36664720 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34336573 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18306413 # num instructions producing a value -system.cpu0.iew.wb_consumers 35193198 # num instructions consuming a value +system.cpu0.iew.exec_nop 117147 # number of nop insts executed +system.cpu0.iew.exec_refs 14623543 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4855012 # Number of branches executed +system.cpu0.iew.exec_stores 5401246 # Number of stores executed +system.cpu0.iew.exec_rate 0.531281 # Inst execution rate +system.cpu0.iew.wb_sent 36677243 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34349196 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18314277 # num instructions producing a value +system.cpu0.iew.wb_consumers 35200184 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.494535 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520169 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.494946 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520289 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6085996 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638860 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231074 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40375183 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775004 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.739173 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6083137 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638876 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231723 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40351353 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775579 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.741147 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28737053 71.18% 71.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5697190 14.11% 85.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1882101 4.66% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 980199 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 786708 1.95% 94.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 526531 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 398386 0.99% 96.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 216969 0.54% 97.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1150046 2.85% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28712298 71.16% 71.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5699883 14.13% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1888088 4.68% 89.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 980743 2.43% 92.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 789976 1.96% 94.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 505077 1.25% 95.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395357 0.98% 96.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 219519 0.54% 97.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1160412 2.88% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40375183 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23683551 # Number of instructions committed -system.cpu0.commit.committedOps 31290943 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40351353 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23685352 # Number of instructions committed +system.cpu0.commit.committedOps 31295648 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11428643 # Number of memory references committed -system.cpu0.commit.loads 6277598 # Number of loads committed -system.cpu0.commit.membars 229694 # Number of memory barriers committed -system.cpu0.commit.branches 4245889 # Number of branches committed +system.cpu0.commit.refs 11431143 # Number of memory references committed +system.cpu0.commit.loads 6279002 # Number of loads committed +system.cpu0.commit.membars 229688 # Number of memory barriers committed +system.cpu0.commit.branches 4246153 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27646853 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489416 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1150046 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27651273 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489419 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1160412 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75750709 # The number of ROB reads -system.cpu0.rob.rob_writes 75732466 # The number of ROB writes -system.cpu0.timesIdled 364061 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28080225 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2140058132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23602809 # Number of Instructions Simulated -system.cpu0.committedOps 31210201 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23602809 # Number of Instructions Simulated -system.cpu0.cpi 2.941685 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.941685 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.339941 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.339941 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171807193 # number of integer regfile reads -system.cpu0.int_regfile_writes 34081987 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3237 # number of floating regfile reads -system.cpu0.fp_regfile_writes 886 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13003191 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451099 # number of misc regfile writes -system.cpu0.icache.tags.replacements 392605 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.965142 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3793600 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 393117 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.650053 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7051834000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.965142 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997979 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997979 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3793600 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3793600 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3793600 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3793600 # number of demand (read+write) hits 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of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5892352014 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5892352014 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4217579 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4217579 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4217579 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4217579 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4217579 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4217579 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100527 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100527 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100527 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100527 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100527 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100527 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.744969 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.744969 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13897.744969 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13897.744969 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3802 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75718589 # The number of ROB reads +system.cpu0.rob.rob_writes 75736714 # The number of ROB writes +system.cpu0.timesIdled 363087 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28071264 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2140090760 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23604610 # Number of Instructions Simulated +system.cpu0.committedOps 31214906 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23604610 # Number of Instructions Simulated +system.cpu0.cpi 2.940097 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.940097 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.340125 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.340125 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171854579 # number of integer regfile reads +system.cpu0.int_regfile_writes 34094081 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3288 # number of floating regfile reads +system.cpu0.fp_regfile_writes 904 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13012931 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451079 # number of misc regfile writes +system.cpu0.icache.tags.replacements 392190 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.931857 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3792228 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 392702 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.656758 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7054061250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.931857 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997914 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997914 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3792228 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3792228 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3792228 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3792228 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3792228 # number of overall hits +system.cpu0.icache.overall_hits::total 3792228 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423961 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423961 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423961 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423961 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423961 # number of overall misses +system.cpu0.icache.overall_misses::total 423961 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5895815248 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5895815248 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5895815248 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5895815248 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5895815248 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5895815248 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4216189 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4216189 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4216189 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4216189 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4216189 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4216189 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13906.503777 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13906.503777 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13906.503777 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13906.503777 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3717 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 164 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.182927 # average number of cycles each access was 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-system.cpu0.icache.ReadReq_mshr_misses::total 393140 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393140 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393140 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393140 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393140 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4794002596 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4794002596 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4794002596 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4794002596 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4794002596 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4794002596 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093215 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093215 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093215 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12194.135921 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31238 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31238 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31238 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31238 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31238 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31238 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392723 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 392723 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 392723 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 392723 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 392723 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 392723 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4798060362 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4798060362 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4798060362 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4798060362 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4798060362 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4798060362 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093146 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093146 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093146 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.416250 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 276287 # number of replacements -system.cpu0.dcache.tags.tagsinuse 459.684046 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9258198 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 276799 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.447368 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 276315 # number of replacements +system.cpu0.dcache.tags.tagsinuse 459.475838 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9261350 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 276827 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.455371 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 43491250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.684046 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897820 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.897820 # Average percentage of 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0.181102 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181102 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181102 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14108.118468 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14108.118468 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50233.162540 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50233.162540 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10346.271621 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10346.271621 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6147.486204 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6147.486204 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43084.696471 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43084.696471 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10884 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 8688 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 601 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.109817 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 67.875000 # average number of cycles each access was blocked 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(read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319286 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319286 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319286 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2419086873 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2419086873 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5310990170 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5310990170 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68672765 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68672765 # number of LoadLockedReq MSHR miss cycles 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accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056029 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056029 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029255 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029255 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12812.892268 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12812.892268 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40701.921064 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40701.921064 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8288.806880 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8288.806880 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4150.807491 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4150.807491 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029246 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029246 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12793.617668 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12793.617668 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40533.727359 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40533.727359 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8323.129589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8323.129589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4147.316903 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4147.316903 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1936,38 +1952,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8781819 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7169373 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 406881 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5765537 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4953289 # Number of BTB hits +system.cpu1.branchPred.lookups 8777296 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7163659 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 407085 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5785994 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4951432 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.912015 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772113 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42948 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.576169 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 773226 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42749 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42694682 # DTB read hits -system.cpu1.dtb.read_misses 36199 # DTB read misses -system.cpu1.dtb.write_hits 6825983 # DTB write hits -system.cpu1.dtb.write_misses 10603 # DTB write misses +system.cpu1.dtb.read_hits 42697243 # DTB read hits +system.cpu1.dtb.read_misses 36228 # DTB read misses +system.cpu1.dtb.write_hits 6821056 # DTB write hits +system.cpu1.dtb.write_misses 10680 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2691 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 287 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2016 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2677 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 664 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42730881 # DTB read accesses -system.cpu1.dtb.write_accesses 6836586 # DTB write accesses +system.cpu1.dtb.perms_faults 642 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42733471 # DTB read accesses +system.cpu1.dtb.write_accesses 6831736 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49520665 # DTB hits -system.cpu1.dtb.misses 46802 # DTB misses -system.cpu1.dtb.accesses 49567467 # DTB accesses -system.cpu1.itb.inst_hits 7578103 # ITB inst hits -system.cpu1.itb.inst_misses 5415 # ITB inst misses +system.cpu1.dtb.hits 49518299 # DTB hits +system.cpu1.dtb.misses 46908 # DTB misses +system.cpu1.dtb.accesses 49565207 # DTB accesses +system.cpu1.itb.inst_hits 7578630 # ITB inst hits +system.cpu1.itb.inst_misses 5358 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1976,114 +1992,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1496 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1501 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7583518 # ITB inst accesses -system.cpu1.itb.hits 7578103 # DTB hits -system.cpu1.itb.misses 5415 # DTB misses -system.cpu1.itb.accesses 7583518 # DTB accesses -system.cpu1.numCycles 409882606 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7583988 # ITB inst accesses +system.cpu1.itb.hits 7578630 # DTB hits +system.cpu1.itb.misses 5358 # DTB misses +system.cpu1.itb.accesses 7583988 # DTB accesses +system.cpu1.numCycles 409868912 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18878139 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 60299044 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8781819 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5725402 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13123323 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3309042 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63154 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78443797 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5020 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42366 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1440662 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7576329 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 547353 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2737 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114261108 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.645293 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.969526 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18867977 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 60276924 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8777296 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5724658 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13120224 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3305222 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63128 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78446194 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5050 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41923 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1438516 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7576833 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 547191 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2712 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114243922 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.645142 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.969298 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 101145087 88.52% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796077 0.70% 89.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 936773 0.82% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1687391 1.48% 91.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1395150 1.22% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 571856 0.50% 93.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1930284 1.69% 94.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 409373 0.36% 95.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5389117 4.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 101131185 88.52% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796172 0.70% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937688 0.82% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1689020 1.48% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1395475 1.22% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 568258 0.50% 93.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1928403 1.69% 94.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410429 0.36% 95.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5387292 4.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114261108 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.021425 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.147113 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20196476 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 79405562 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11967958 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523276 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2167836 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1103528 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98181 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69822224 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 326370 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2167836 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21386304 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 34427825 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40782107 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11206546 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4290490 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 65904089 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18821 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 671145 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3046869 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 355 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 69217965 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 302501585 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 280690851 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6493 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49057579 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20160386 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444741 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387793 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7877859 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12590402 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7938263 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1041211 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1447247 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60694774 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157845 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 87723814 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94478 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13427979 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 35976172 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277080 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114261108 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.767749 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.513486 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114243922 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021415 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.147064 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20194584 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 79395702 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11966487 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 522966 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2164183 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1104463 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98170 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69803405 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327162 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2164183 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21384110 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34428627 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40773355 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11205851 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4287796 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 65891244 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18827 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 669159 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3045569 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1057 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 69207054 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 302452168 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 280640301 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6501 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49057788 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20149266 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444930 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 388060 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7871220 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12589854 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7931577 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1030582 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1486229 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60667262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1158299 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 87712047 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93594 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13406861 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 35899906 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277508 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114243922 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.767761 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.513174 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84436887 73.90% 73.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8271726 7.24% 81.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4125209 3.61% 84.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3692140 3.23% 87.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10373138 9.08% 97.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1967895 1.72% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1041724 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 276233 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 76156 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84413448 73.89% 73.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8278708 7.25% 81.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4125885 3.61% 84.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3695285 3.23% 87.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10373691 9.08% 97.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1966586 1.72% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1039954 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 274624 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 75741 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114261108 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114243922 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32226 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 994 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32139 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 997 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -2111,13 +2127,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7551636 95.89% 96.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 290793 3.69% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7551678 95.88% 96.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 291209 3.70% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36606472 41.73% 42.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59249 0.07% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36599204 41.73% 42.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59264 0.07% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued @@ -2130,376 +2146,376 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43568189 49.67% 91.82% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7174305 8.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43568617 49.67% 91.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7169368 8.17% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 87723814 # Type of FU issued -system.cpu1.iq.rate 0.214022 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7875649 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089778 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 297709996 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 75289267 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53144243 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15477 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8000 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95277128 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8273 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 341654 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 87712047 # Type of FU issued +system.cpu1.iq.rate 0.214000 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7876023 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089794 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 297668917 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 75240910 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53134013 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15426 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7990 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6798 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95265766 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8242 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342419 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2834942 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3919 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1098203 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2834348 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3679 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17028 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1091492 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31919752 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 674526 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31919677 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675013 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2167836 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26657812 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 361941 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 61957280 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112544 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12590402 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7938263 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869014 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64925 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17226 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 200285 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154811 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 355096 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 85998990 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43064757 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1724824 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2164183 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26656099 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 359793 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 61930029 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112185 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12589854 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7931577 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869499 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 63855 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3879 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17028 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201052 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154389 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 355441 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85989380 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43067298 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1722667 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104661 # number of nop insts executed -system.cpu1.iew.exec_refs 50176981 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6911907 # Number of branches executed -system.cpu1.iew.exec_stores 7112224 # Number of stores executed -system.cpu1.iew.exec_rate 0.209814 # Inst execution rate -system.cpu1.iew.wb_sent 85240093 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53151046 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29713379 # num instructions producing a value -system.cpu1.iew.wb_consumers 52980753 # num instructions consuming a value +system.cpu1.iew.exec_nop 104468 # number of nop insts executed +system.cpu1.iew.exec_refs 50174734 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6912361 # Number of branches executed +system.cpu1.iew.exec_stores 7107436 # Number of stores executed +system.cpu1.iew.exec_rate 0.209797 # Inst execution rate +system.cpu1.iew.wb_sent 85230326 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53140811 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29705560 # num instructions producing a value +system.cpu1.iew.wb_consumers 52974804 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.129674 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560833 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.129653 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560749 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13311701 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880765 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 310263 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112093272 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.429609 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.397405 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13285222 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880791 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 310591 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112079739 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.429663 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.397726 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95372912 85.08% 85.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8221460 7.33% 92.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2092695 1.87% 94.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254196 1.12% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1248841 1.11% 96.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 572620 0.51% 97.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 992421 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 531111 0.47% 98.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1807016 1.61% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95362610 85.08% 85.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8223786 7.34% 92.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2087568 1.86% 94.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1250330 1.12% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1251085 1.12% 96.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 572828 0.51% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 991388 0.88% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 531334 0.47% 98.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1808810 1.61% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112093272 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38065083 # Number of instructions committed -system.cpu1.commit.committedOps 48156333 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112079739 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38065286 # Number of instructions committed +system.cpu1.commit.committedOps 48156538 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16595520 # Number of memory references committed -system.cpu1.commit.loads 9755460 # Number of loads committed +system.cpu1.commit.refs 16595591 # Number of memory references committed +system.cpu1.commit.loads 9755506 # Number of loads committed system.cpu1.commit.membars 190120 # Number of memory barriers committed -system.cpu1.commit.branches 5967695 # Number of branches committed +system.cpu1.commit.branches 5967745 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42691207 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534629 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1807016 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42691339 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534627 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1808810 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 170710273 # The number of ROB reads -system.cpu1.rob.rob_writes 125186848 # The number of ROB writes -system.cpu1.timesIdled 1415125 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295621498 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1799013115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37995444 # Number of Instructions Simulated -system.cpu1.committedOps 48086694 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37995444 # Number of Instructions Simulated -system.cpu1.cpi 10.787678 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.787678 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092698 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092698 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 384930549 # number of integer regfile reads -system.cpu1.int_regfile_writes 55277579 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5074 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18448778 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405411 # number of misc regfile writes -system.cpu1.icache.tags.replacements 596659 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.521199 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6934084 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 597171 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.611555 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74930526000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.521199 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938518 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938518 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 6934084 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6934084 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6934084 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6934084 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6934084 # number of overall hits -system.cpu1.icache.overall_hits::total 6934084 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 642197 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 642197 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 642197 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 642197 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 642197 # number of overall misses -system.cpu1.icache.overall_misses::total 642197 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8716898620 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8716898620 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8716898620 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8716898620 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8716898620 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8716898620 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576281 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7576281 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7576281 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7576281 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7576281 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7576281 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084764 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084764 # miss rate for ReadReq accesses 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miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.847232 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13573.847232 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13573.847232 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2595 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 176 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.610526 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.744318 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44987 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44987 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44987 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44987 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44987 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44987 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597210 # number of ReadReq MSHR misses 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-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11913.810018 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078709 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.078709 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078709 # mshr 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misses -system.cpu1.dcache.overall_misses::total 1956575 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6078170016 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6078170016 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 80199088679 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 80199088679 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128606244 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 128606244 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52837907 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 52837907 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 86277258695 # number of demand (read+write) miss cycles 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0.125229 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100265 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100265 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135859 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135859 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135859 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135859 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.359434 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.359434 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51480.325677 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 51480.325677 # average WriteReq miss latency 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WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161692 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12502 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12502 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10574 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10574 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 390063 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 390063 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 390063 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 390063 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2847018297 # number of ReadReq MSHR miss cycles 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rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026235 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028384 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028384 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112335 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112335 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100256 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100256 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027085 # mshr miss rate for demand accesses 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MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7240277216 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88160756 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88160756 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31863585 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31863585 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10083543020 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 10083543020 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10083543020 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 10083543020 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925167755 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925167755 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25834747063 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25834747063 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194759914818 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194759914818 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026228 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026228 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028372 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028372 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112330 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112330 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100319 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100319 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027076 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027076 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12450.695843 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12450.695843 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44796.765451 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44796.765451 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7035.412657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7035.412657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3011.396371 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3011.396371 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2521,18 +2537,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612781961046 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 612781961046 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612781961046 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 612781961046 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612762276058 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 612762276058 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612762276058 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 612762276058 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41730 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41714 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48851 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48863 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index f1e51a584..49d73e9a8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,12 +602,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -555,6 +620,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -577,12 +643,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -592,19 +660,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -617,6 +689,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -639,6 +712,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -646,6 +720,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -657,6 +732,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -683,6 +759,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -694,19 +771,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -716,6 +797,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -725,6 +807,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -753,6 +836,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -762,8 +846,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -775,6 +891,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -790,6 +907,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -804,6 +923,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -813,6 +933,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -834,8 +955,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -844,6 +967,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -854,6 +978,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -864,6 +989,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -874,6 +1000,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -888,6 +1015,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -901,6 +1029,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -918,6 +1047,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -930,6 +1060,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -941,6 +1072,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -951,6 +1083,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -963,6 +1096,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -976,6 +1110,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -986,6 +1121,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -996,6 +1132,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1006,6 +1143,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1018,6 +1156,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1032,6 +1171,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1044,6 +1184,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1058,6 +1199,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1068,6 +1210,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1078,6 +1221,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1088,6 +1232,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1096,6 +1241,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1103,11 +1249,13 @@ port=3456 [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b60e42a06..65955f345 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525141 # Number of seconds simulated -sim_ticks 2525141046500 # Number of ticks simulated -final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525132 # Number of seconds simulated +sim_ticks 2525131633500 # Number of ticks simulated +final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61643 # Simulator instruction rate (inst/s) -host_op_rate 79318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2581152882 # Simulator tick rate (ticks/s) -host_mem_usage 426780 # Number of bytes of host memory used -host_seconds 978.30 # Real time elapsed on the host -sim_insts 60305756 # Number of instructions simulated -sim_ops 77596741 # Number of ops (including micro ops) simulated +host_inst_rate 49653 # Simulator instruction rate (inst/s) +host_op_rate 63890 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2079077169 # Simulator tick rate (ticks/s) +host_mem_usage 446400 # Number of bytes of host memory used +host_seconds 1214.54 # Real time elapsed on the host +sim_insts 60305678 # Number of instructions simulated +sim_ops 77596684 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15096843 # Number of read requests accepted -system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.writeReqs 813149 # Number of write requests accepted system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943582 # Per bank write bursts -system.physmem.perBankRdBursts::1 943145 # Per bank write bursts -system.physmem.perBankRdBursts::2 939291 # Per bank write bursts -system.physmem.perBankRdBursts::3 939307 # Per bank write bursts -system.physmem.perBankRdBursts::4 943115 # Per bank write bursts -system.physmem.perBankRdBursts::5 943141 # Per bank write bursts -system.physmem.perBankRdBursts::6 939138 # Per bank write bursts -system.physmem.perBankRdBursts::7 938546 # Per bank write bursts -system.physmem.perBankRdBursts::8 943996 # Per bank write bursts -system.physmem.perBankRdBursts::9 943390 # Per bank write bursts -system.physmem.perBankRdBursts::10 938426 # Per bank write bursts -system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943580 # Per bank write bursts +system.physmem.perBankRdBursts::1 943152 # Per bank write bursts +system.physmem.perBankRdBursts::2 939288 # Per bank write bursts +system.physmem.perBankRdBursts::3 939310 # Per bank write bursts +system.physmem.perBankRdBursts::4 943113 # Per bank write bursts +system.physmem.perBankRdBursts::5 943139 # Per bank write bursts +system.physmem.perBankRdBursts::6 939134 # Per bank write bursts +system.physmem.perBankRdBursts::7 938551 # Per bank write bursts +system.physmem.perBankRdBursts::8 944000 # Per bank write bursts +system.physmem.perBankRdBursts::9 943392 # Per bank write bursts +system.physmem.perBankRdBursts::10 938425 # Per bank write bursts +system.physmem.perBankRdBursts::11 937973 # Per bank write bursts system.physmem.perBankRdBursts::12 943928 # Per bank write bursts -system.physmem.perBankRdBursts::13 943533 # Per bank write bursts -system.physmem.perBankRdBursts::14 939234 # Per bank write bursts -system.physmem.perBankRdBursts::15 938672 # Per bank write bursts -system.physmem.perBankWrBursts::0 6704 # Per bank write bursts -system.physmem.perBankWrBursts::1 6457 # Per bank write bursts -system.physmem.perBankWrBursts::2 6598 # Per bank write bursts -system.physmem.perBankWrBursts::3 6635 # Per bank write bursts -system.physmem.perBankWrBursts::4 6561 # Per bank write bursts -system.physmem.perBankWrBursts::5 6794 # Per bank write bursts -system.physmem.perBankWrBursts::6 6789 # Per bank write bursts -system.physmem.perBankWrBursts::7 6723 # Per bank write bursts -system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankRdBursts::13 943534 # Per bank write bursts +system.physmem.perBankRdBursts::14 939230 # Per bank write bursts +system.physmem.perBankRdBursts::15 938669 # Per bank write bursts +system.physmem.perBankWrBursts::0 6703 # Per bank write bursts +system.physmem.perBankWrBursts::1 6464 # Per bank write bursts +system.physmem.perBankWrBursts::2 6595 # Per bank write bursts +system.physmem.perBankWrBursts::3 6634 # Per bank write bursts +system.physmem.perBankWrBursts::4 6559 # Per bank write bursts +system.physmem.perBankWrBursts::5 6792 # Per bank write bursts +system.physmem.perBankWrBursts::6 6793 # Per bank write bursts +system.physmem.perBankWrBursts::7 6730 # Per bank write bursts +system.physmem.perBankWrBursts::8 7130 # Per bank write bursts system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 6538 # Per bank write bursts -system.physmem.perBankWrBursts::11 6183 # Per bank write bursts -system.physmem.perBankWrBursts::12 7149 # Per bank write bursts -system.physmem.perBankWrBursts::13 6765 # Per bank write bursts -system.physmem.perBankWrBursts::14 7038 # Per bank write bursts -system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.perBankWrBursts::10 6539 # Per bank write bursts +system.physmem.perBankWrBursts::11 6181 # Per bank write bursts +system.physmem.perBankWrBursts::12 7151 # Per bank write bursts +system.physmem.perBankWrBursts::13 6766 # Per bank write bursts +system.physmem.perBankWrBursts::14 7035 # Per bank write bursts +system.physmem.perBankWrBursts::15 6897 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.totGap 2525130505500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 36 # Read request sizes (log2) @@ -109,26 +109,26 @@ system.physmem.writePktSize::2 754018 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59125 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59131 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -142,29 +142,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see @@ -174,521 +174,534 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11268.950798 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1000.903149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16775.480046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23607 27.41% 27.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14081 16.35% 43.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2628 3.05% 46.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2075 2.41% 49.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1317 1.53% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1250 1.45% 52.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 847 0.98% 53.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 989 1.15% 54.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 557 0.65% 54.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 603 0.70% 55.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 514 0.60% 56.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 583 0.68% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 264 0.31% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 155 0.18% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 634 0.74% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 90 0.10% 58.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 121 0.14% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 516 0.60% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 33 0.04% 59.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 269 0.31% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 22 0.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 94 0.11% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 142 0.16% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 22 0.03% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 57 0.07% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 390 0.45% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 120 0.14% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 5 0.01% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 22 0.03% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 8 0.01% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 107 0.12% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 24 0.03% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 86 0.10% 61.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 27 0.03% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 358 0.42% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 154 0.18% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 62.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 15 0.02% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 31 0.04% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 11 0.01% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 39 0.05% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 368 0.43% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 15 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 165 0.19% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 92 0.11% 63.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row 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-system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 82 0.10% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 365 0.42% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 75 0.09% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 129 0.15% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38464-38471 1 0.00% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 14 0.02% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 267 0.31% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 140 0.16% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 70 0.08% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 351 0.41% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 129 0.15% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 76 0.09% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 2 0.00% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 80 0.09% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40832-40839 2 0.00% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 269 0.31% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 77 0.09% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 75 0.09% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 131 0.15% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 349 0.41% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 70 0.08% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 140 0.16% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 77 0.09% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 267 0.31% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 3 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 14 0.02% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 127 0.15% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 80 0.09% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 364 0.42% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 83 0.10% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 73 0.08% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 144 0.17% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 337 0.39% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 24 0.03% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 3 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 16 0.02% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 144 0.17% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 2 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 327 0.38% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 69 0.08% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 79 0.09% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 89 0.10% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 334 0.39% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 88 0.10% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 24 0.03% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 398 0.46% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 77 0.09% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 72 0.08% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 83 0.10% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5012 5.82% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation @@ -714,15 +727,15 @@ system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation -system.physmem.totQLat 365610387500 # Total ticks spent queuing -system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation +system.physmem.totQLat 365453646000 # Total ticks spent queuing +system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks -system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks +system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s @@ -732,14 +745,14 @@ system.physmem.busUtil 3.00 # Da system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing -system.physmem.readRowHits 14986740 # Number of row buffer hits during reads -system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing +system.physmem.readRowHits 14986798 # Number of row buffer hits during reads +system.physmem.writeRowHits 93332 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes -system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes +system.physmem.avgGap 158713.50 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -752,50 +765,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54899945 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149440 # Transaction distribution -system.membus.trans_dist::ReadResp 16149440 # Transaction distribution +system.membus.throughput 54900302 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149434 # Transaction distribution +system.membus.trans_dist::ReadResp 16149434 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::Writeback 59131 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution -system.membus.trans_dist::ReadExReq 131442 # Transaction distribution -system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution +system.membus.trans_dist::ReadExReq 131448 # Transaction distribution +system.membus.trans_dist::ReadExResp 131448 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630105 # Total data (bytes) +system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630489 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -803,7 +816,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.throughput 48285786 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution @@ -913,40 +926,40 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14384905 # Number of BP lookups -system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits +system.cpu.branchPred.lookups 14384927 # Number of BP lookups +system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51179212 # DTB read hits -system.cpu.dtb.read_misses 64531 # DTB read misses -system.cpu.dtb.write_hits 11698539 # DTB write hits -system.cpu.dtb.write_misses 15837 # DTB write misses +system.cpu.dtb.read_hits 51182106 # DTB read hits +system.cpu.dtb.read_misses 64421 # DTB read misses +system.cpu.dtb.write_hits 11699698 # DTB write hits +system.cpu.dtb.write_misses 15824 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3571 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3567 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51243743 # DTB read accesses -system.cpu.dtb.write_accesses 11714376 # DTB write accesses +system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51246527 # DTB read accesses +system.cpu.dtb.write_accesses 11715522 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62877751 # DTB hits -system.cpu.dtb.misses 80368 # DTB misses -system.cpu.dtb.accesses 62958119 # DTB accesses -system.cpu.itb.inst_hits 11513998 # ITB inst hits -system.cpu.itb.inst_misses 11344 # ITB inst misses +system.cpu.dtb.hits 62881804 # DTB hits +system.cpu.dtb.misses 80245 # DTB misses +system.cpu.dtb.accesses 62962049 # DTB accesses +system.cpu.itb.inst_hits 11522583 # ITB inst hits +system.cpu.itb.inst_misses 11276 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -955,148 +968,148 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2483 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11525342 # ITB inst accesses -system.cpu.itb.hits 11513998 # DTB hits -system.cpu.itb.misses 11344 # DTB misses -system.cpu.itb.accesses 11525342 # DTB accesses -system.cpu.numCycles 474882944 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11533859 # ITB inst accesses +system.cpu.itb.hits 11522583 # DTB hits +system.cpu.itb.misses 11276 # DTB misses +system.cpu.itb.accesses 11533859 # DTB accesses +system.cpu.numCycles 474898657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle +system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -1109,397 +1122,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued -system.cpu.iq.rate 0.258795 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued +system.cpu.iq.rate 0.258806 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221869 # number of nop insts executed -system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed -system.cpu.iew.exec_branches 11475076 # Number of branches executed -system.cpu.iew.exec_stores 12210518 # Number of stores executed -system.cpu.iew.exec_rate 0.254424 # Inst execution rate -system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47026181 # num instructions producing a value -system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value +system.cpu.iew.exec_nop 221761 # number of nop insts executed +system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475005 # Number of branches executed +system.cpu.iew.exec_stores 12211635 # Number of stores executed +system.cpu.iew.exec_rate 0.254432 # Inst execution rate +system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47031033 # num instructions producing a value +system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456137 # Number of instructions committed -system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456059 # Number of instructions committed +system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385736 # Number of memory references committed -system.cpu.commit.loads 15654008 # Number of loads committed -system.cpu.commit.membars 403573 # Number of memory barriers committed -system.cpu.commit.branches 9961077 # Number of branches committed +system.cpu.commit.refs 27385723 # Number of memory references committed +system.cpu.commit.loads 15653991 # Number of loads committed +system.cpu.commit.membars 403571 # Number of memory barriers committed +system.cpu.commit.branches 9961071 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. -system.cpu.commit.function_calls 991208 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. +system.cpu.commit.function_calls 991207 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240636318 # The number of ROB reads -system.cpu.rob.rob_writes 195934369 # The number of ROB writes -system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305756 # Number of Instructions Simulated -system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated -system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547208469 # number of integer regfile reads -system.cpu.int_regfile_writes 87526188 # number of integer regfile writes -system.cpu.fp_regfile_reads 8624 # number of floating regfile reads -system.cpu.fp_regfile_writes 3008 # number of floating regfile writes -system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.rob.rob_reads 240665808 # The number of ROB reads +system.cpu.rob.rob_writes 195946920 # The number of ROB writes +system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305678 # Number of Instructions Simulated +system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated +system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547244882 # number of integer regfile reads +system.cpu.int_regfile_writes 87532645 # number of integer regfile writes +system.cpu.fp_regfile_reads 8511 # number of floating regfile reads +system.cpu.fp_regfile_writes 2972 # number of floating regfile writes +system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads system.cpu.misc_regfile_writes 831837 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution +system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246128 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796637 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62740736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85535129 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41644 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 210260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148527769 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148527769 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 199672 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3129078659 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474541718 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550360089 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20171491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74593037 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980741 # number of replacements -system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 980798 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579102 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10457750 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981310 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.656928 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits -system.cpu.icache.overall_hits::total 10449649 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses -system.cpu.icache.overall_misses::total 1060761 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10457750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10457750 # number of overall hits +system.cpu.icache.overall_hits::total 10457750 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061214 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061214 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061214 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061214 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061214 # number of overall misses +system.cpu.icache.overall_misses::total 1061214 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14272429649 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14272429649 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14272429649 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14272429649 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 322 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.602484 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits 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-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79868 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79868 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79868 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79868 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79868 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79868 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981346 # 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overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11584683024 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085194 # mshr miss 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11804.891469 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 64371 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.550810 # Average number of references to valid blocks. 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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63471.335270 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63471.335270 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1620,161 +1633,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.replacements 643483 # number of replacements system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits -system.cpu.dcache.overall_hits::total 21010251 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses -system.cpu.dcache.overall_misses::total 3701471 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258628 # number of WriteReq hits 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+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13576 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700707 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700707 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700707 # number of overall misses +system.cpu.dcache.overall_misses::total 3700707 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10005137822 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10005137822 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 141347559382 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 141347559382 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185728250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185728250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 206503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 206503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 151352697204 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 151352697204 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 151352697204 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 151352697204 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492781 # number of ReadReq accesses(hits+misses) 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demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks -system.cpu.dcache.writebacks::total 607699 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks +system.cpu.dcache.writebacks::total 607897 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065987 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065987 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385715 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385715 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249005 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249005 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1796,16 +1809,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index c314ac71a..745161c28 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -119,6 +128,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -141,18 +151,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -163,6 +176,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -185,14 +199,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -211,18 +228,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -234,6 +254,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -255,17 +276,20 @@ workload= [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -284,17 +308,20 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=DerivO3CPU @@ -325,6 +352,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -387,6 +416,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -399,12 +429,14 @@ predType=tournament [system.cpu2.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu2.dtb.walker [system.cpu2.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system @@ -412,15 +444,18 @@ sys=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -429,16 +464,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu2.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -447,22 +485,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu2.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu2.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -471,22 +513,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu2.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu2.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -495,10 +541,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -507,124 +555,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu2.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu2.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu2.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu2.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu2.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu2.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu2.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu2.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu2.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu2.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu2.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu2.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu2.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu2.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu2.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu2.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu2.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -633,10 +702,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -645,16 +716,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu2.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -663,16 +737,19 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu2.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -691,30 +768,36 @@ midr=890224640 [system.cpu2.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu2.itb.walker [system.cpu2.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -727,6 +810,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -749,6 +833,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -758,6 +843,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -780,6 +866,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -787,6 +874,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -798,6 +886,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -824,6 +913,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -835,19 +925,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -857,6 +951,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -866,6 +961,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -894,6 +990,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -903,8 +1000,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -916,6 +1045,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -931,6 +1061,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -945,6 +1077,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -954,6 +1087,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -975,8 +1109,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -985,6 +1121,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -995,6 +1132,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1005,6 +1143,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1015,6 +1154,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1029,6 +1169,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1042,6 +1183,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1059,6 +1201,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1071,6 +1214,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1082,6 +1226,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1092,6 +1237,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1104,6 +1250,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1117,6 +1264,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1127,6 +1275,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1137,6 +1286,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1147,6 +1297,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1159,6 +1310,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1173,6 +1325,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1185,6 +1338,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1199,6 +1353,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1209,6 +1364,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1219,6 +1375,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1229,6 +1386,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1237,6 +1395,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1245,6 +1404,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1254,11 +1414,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 506582551..3eab7d5a6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,166 +1,182 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403658 # Number of seconds simulated -sim_ticks 2403657545000 # Number of ticks simulated -final_tick 2403657545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403659 # Number of seconds simulated +sim_ticks 2403658742000 # Number of ticks simulated +final_tick 2403658742000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183148 # Simulator instruction rate (inst/s) -host_op_rate 235229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7297160965 # Simulator tick rate (ticks/s) -host_mem_usage 427808 # Number of bytes of host memory used -host_seconds 329.40 # Real time elapsed on the host -sim_insts 60328152 # Number of instructions simulated -sim_ops 77483430 # Number of ops (including micro ops) simulated +host_inst_rate 141358 # Simulator instruction rate (inst/s) +host_op_rate 181555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5632122143 # Simulator tick rate (ticks/s) +host_mem_usage 447420 # Number of bytes of host memory used +host_seconds 426.78 # Real time elapsed on the host +sim_insts 60328128 # Number of instructions simulated +sim_ops 77483556 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7048656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7049296 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 64128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 675392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 187392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1353632 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512416 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 674944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 186496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1353888 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512480 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 187392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3744384 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298192 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu2.inst 186496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743872 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298256 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 159304 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558320 # Number of bytes written to this memory -system.physmem.bytes_written::total 6760200 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558256 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759688 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14209 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14210 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110179 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1002 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10553 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58506 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324548 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 10546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2914 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21162 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512409 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58498 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324564 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 39826 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389580 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812460 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47768482 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu2.data 389564 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812452 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47768458 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2932471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2932736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 26679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 563155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 563261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213208 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 26679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77961 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557786 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540090 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557572 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540117 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648312 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47768482 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648285 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812249 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47768458 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3472561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3472852 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 26679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 347261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1211467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54675779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13467317 # Number of read requests accepted -system.physmem.writeReqs 446508 # Number of write requests accepted -system.physmem.readBursts 13467317 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446508 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 861908288 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.data 347074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1211546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54675299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13477345 # Number of read requests accepted +system.physmem.writeReqs 446482 # Number of write requests accepted +system.physmem.readBursts 13477345 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446482 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 862550080 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 2866432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109734624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2812152 # Total written bytes from the system interface side +system.physmem.bytesWritten 2865536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109813728 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2811448 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 401719 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2372 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 837719 # Per bank write bursts -system.physmem.perBankRdBursts::1 837389 # Per bank write bursts -system.physmem.perBankRdBursts::2 837556 # Per bank write bursts -system.physmem.perBankRdBursts::3 837999 # Per bank write bursts -system.physmem.perBankRdBursts::4 838842 # Per bank write bursts -system.physmem.perBankRdBursts::5 838880 # Per bank write bursts -system.physmem.perBankRdBursts::6 838796 # Per bank write bursts -system.physmem.perBankRdBursts::7 839742 # Per bank write bursts -system.physmem.perBankRdBursts::8 840911 # Per bank write bursts -system.physmem.perBankRdBursts::9 843323 # Per bank write bursts -system.physmem.perBankRdBursts::10 844015 # Per bank write bursts -system.physmem.perBankRdBursts::11 845500 # Per bank write bursts -system.physmem.perBankRdBursts::12 847242 # Per bank write bursts -system.physmem.perBankRdBursts::13 846993 # Per bank write bursts -system.physmem.perBankRdBursts::14 845867 # Per bank write bursts -system.physmem.perBankRdBursts::15 846543 # Per bank write bursts -system.physmem.perBankWrBursts::0 2729 # Per bank write bursts -system.physmem.perBankWrBursts::1 2587 # Per bank write bursts -system.physmem.perBankWrBursts::2 2574 # Per bank write bursts -system.physmem.perBankWrBursts::3 3045 # Per bank write bursts -system.physmem.perBankWrBursts::4 3468 # Per bank write bursts -system.physmem.perBankWrBursts::5 3206 # Per bank write bursts -system.physmem.perBankWrBursts::6 2544 # Per bank write bursts -system.physmem.perBankWrBursts::7 2321 # Per bank write bursts -system.physmem.perBankWrBursts::8 2236 # Per bank write bursts -system.physmem.perBankWrBursts::9 2427 # Per bank write bursts -system.physmem.perBankWrBursts::10 2367 # Per bank write bursts -system.physmem.perBankWrBursts::11 2798 # Per bank write bursts -system.physmem.perBankWrBursts::12 3813 # Per bank write bursts -system.physmem.perBankWrBursts::13 3444 # Per bank write bursts -system.physmem.perBankWrBursts::14 2680 # Per bank write bursts -system.physmem.perBankWrBursts::15 2549 # Per bank write bursts +system.physmem.mergedWrBursts 401707 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2370 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 837716 # Per bank write bursts +system.physmem.perBankRdBursts::1 837382 # Per bank write bursts +system.physmem.perBankRdBursts::2 837561 # Per bank write bursts +system.physmem.perBankRdBursts::3 838016 # Per bank write bursts +system.physmem.perBankRdBursts::4 839132 # Per bank write bursts +system.physmem.perBankRdBursts::5 839847 # Per bank write bursts +system.physmem.perBankRdBursts::6 839973 # Per bank write bursts +system.physmem.perBankRdBursts::7 841200 # Per bank write bursts +system.physmem.perBankRdBursts::8 842679 # Per bank write bursts +system.physmem.perBankRdBursts::9 845377 # Per bank write bursts +system.physmem.perBankRdBursts::10 845421 # Per bank write bursts +system.physmem.perBankRdBursts::11 845910 # Per bank write bursts +system.physmem.perBankRdBursts::12 847235 # Per bank write bursts +system.physmem.perBankRdBursts::13 846991 # Per bank write bursts +system.physmem.perBankRdBursts::14 846262 # Per bank write bursts +system.physmem.perBankRdBursts::15 846643 # Per bank write bursts +system.physmem.perBankWrBursts::0 2727 # Per bank write bursts +system.physmem.perBankWrBursts::1 2580 # Per bank write bursts +system.physmem.perBankWrBursts::2 2569 # Per bank write bursts +system.physmem.perBankWrBursts::3 3046 # Per bank write bursts +system.physmem.perBankWrBursts::4 3472 # Per bank write bursts +system.physmem.perBankWrBursts::5 3199 # Per bank write bursts +system.physmem.perBankWrBursts::6 2543 # Per bank write bursts +system.physmem.perBankWrBursts::7 2318 # Per bank write bursts +system.physmem.perBankWrBursts::8 2233 # Per bank write bursts +system.physmem.perBankWrBursts::9 2426 # Per bank write bursts +system.physmem.perBankWrBursts::10 2368 # Per bank write bursts +system.physmem.perBankWrBursts::11 2824 # Per bank write bursts +system.physmem.perBankWrBursts::12 3814 # Per bank write bursts +system.physmem.perBankWrBursts::13 3447 # Per bank write bursts +system.physmem.perBankWrBursts::14 2652 # Per bank write bursts +system.physmem.perBankWrBursts::15 2556 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402622305000 # Total gap between requests +system.physmem.totGap 2402623562000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13431664 # Read request sizes (log2) +system.physmem.readPktSize::3 13441712 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35645 # Read request sizes (log2) +system.physmem.readPktSize::6 35625 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429406 # Write request sizes (log2) +system.physmem.writePktSize::2 429390 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17102 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 965936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 943404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 937737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3274872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2367219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2366833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2384991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 47923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 55146 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17092 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 971418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 948778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 943230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3279616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2365953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2365403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2381873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 45829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 51923 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 17633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 17612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 17582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 17596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -176,30 +192,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -208,304 +224,298 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 17848.429795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3200.071202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 18346.519598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 8608 17.77% 17.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 4824 9.96% 27.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 1006 2.08% 29.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 654 1.35% 31.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 399 0.82% 31.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 406 0.84% 32.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 283 0.58% 33.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 297 0.61% 34.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 176 0.36% 34.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 170 0.35% 34.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 172 0.35% 35.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 155 0.32% 35.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 77 0.16% 35.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 80 0.17% 35.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 48 0.10% 35.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 416 0.86% 36.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 18 0.04% 36.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 23 0.05% 36.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 23 0.05% 36.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 108 0.22% 37.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 17 0.04% 37.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 165 0.34% 37.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 12 0.02% 37.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 112 0.23% 37.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 15 0.03% 37.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 32 0.07% 37.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 7 0.01% 37.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 140 0.29% 38.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 6 0.01% 38.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 13 0.03% 38.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 455 0.94% 39.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 12 0.02% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 2 0.00% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 72 0.15% 39.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 5 0.01% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 6 0.01% 39.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 5 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 10 0.02% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 5 0.01% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 8 0.02% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 2 0.00% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 505 1.04% 40.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 5 0.01% 40.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 5 0.01% 40.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 65 0.13% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 5 0.01% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.02% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 15 0.03% 40.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 3 0.01% 40.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 4 0.01% 40.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 6 0.01% 40.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 66 0.14% 40.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 3 0.01% 40.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 327 0.67% 41.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 5 0.01% 41.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 8 0.02% 41.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 2 0.00% 41.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 130 0.27% 41.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 6 0.01% 41.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 4 0.01% 41.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.01% 41.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 68 0.14% 41.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.01% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 2 0.00% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 5 0.01% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 4 0.01% 42.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.01% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 7 0.01% 42.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 258 0.53% 42.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 42.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 4 0.01% 42.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 3 0.01% 42.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 88 0.18% 42.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 3 0.01% 42.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 8 0.02% 42.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.01% 42.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 92 0.19% 42.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 4 0.01% 43.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 7 0.01% 43.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 43.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 102 0.21% 43.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 2 0.00% 43.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 3 0.01% 43.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 481 0.99% 44.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 2 0.00% 44.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 3 0.01% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 1 0.00% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 3 0.01% 44.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 67 0.14% 44.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 5 0.01% 44.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 6 0.01% 44.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 131 0.27% 44.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 1 0.00% 44.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 1 0.00% 44.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 72 0.15% 44.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 44.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 2 0.00% 44.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 13 0.03% 44.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 133 0.27% 45.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 66 0.14% 45.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 64 0.13% 45.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 385 0.79% 46.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 65 0.13% 46.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 128 0.26% 46.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 73 0.15% 46.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 128 0.26% 47.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 64 0.13% 47.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 478 0.99% 48.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 63 0.13% 48.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 48.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 89 0.18% 48.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 86 0.18% 48.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 257 0.53% 49.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 1 0.00% 49.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 65 0.13% 49.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 320 0.66% 50.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 64 0.13% 50.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 14 0.03% 50.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 50.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 64 0.13% 50.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 499 1.03% 51.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 64 0.13% 51.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 442 0.91% 52.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 66 0.14% 53.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 72 0.15% 53.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 362 0.75% 54.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 2 0.00% 54.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 6 0.01% 54.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 781 1.61% 55.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 7 0.01% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 362 0.75% 56.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 72 0.15% 56.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 64 0.13% 56.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 128 0.26% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 57.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 442 0.91% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 64 0.13% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 499 1.03% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 64 0.13% 59.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 12 0.02% 59.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 66 0.14% 59.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 320 0.66% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 128 0.26% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 256 0.53% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 85 0.18% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 87 0.18% 61.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 64 0.13% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 478 0.99% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 67 0.14% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 128 0.26% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 71 0.15% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 129 0.27% 63.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 64 0.13% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 384 0.79% 64.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 64 0.13% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 64 0.13% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 129 0.27% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 70 0.14% 64.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 128 0.26% 65.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26055 1 0.00% 65.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 66 0.14% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 480 0.99% 66.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 64 0.13% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 89 0.18% 66.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 86 0.18% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 1 0.00% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 67.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 127 0.26% 67.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 320 0.66% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 65 0.13% 68.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 13 0.03% 68.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 64 0.13% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 497 1.03% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 64 0.13% 69.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 442 0.91% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 1 0.00% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 65 0.13% 71.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 72 0.15% 71.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 362 0.75% 72.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 1 0.00% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 6 0.01% 72.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 778 1.61% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 5 0.01% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 1 0.00% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 2 0.00% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 362 0.75% 74.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 72 0.15% 74.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 66 0.14% 74.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 443 0.91% 75.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 1 0.00% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 499 1.03% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 64 0.13% 77.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 13 0.03% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 321 0.66% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 127 0.26% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 1 0.00% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 1 0.00% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 257 0.53% 79.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 1 0.00% 79.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 86 0.18% 79.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 89 0.18% 79.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 479 0.99% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39495 1 0.00% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 128 0.26% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 71 0.15% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 128 0.26% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 64 0.13% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 64 0.13% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 384 0.79% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 129 0.27% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 71 0.15% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 128 0.26% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 67 0.14% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 477 0.98% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 64 0.13% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 87 0.18% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 1 0.00% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 84 0.17% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 128 0.26% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 320 0.66% 86.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 65 0.13% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 12 0.02% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 64 0.13% 86.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 498 1.03% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 1 0.00% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 64 0.13% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 443 0.91% 88.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 66 0.14% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 72 0.15% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 362 0.75% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 2 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 2 0.00% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 1 0.00% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 7 0.01% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 4749 9.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48451 # Bytes accessed per row activation -system.physmem.totQLat 326245474250 # Total ticks spent queuing -system.physmem.totMemAccLat 407559786750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67336585000 # Total ticks spent in databus transfers -system.physmem.totBankLat 13977727500 # Total ticks spent accessing banks -system.physmem.avgQLat 24224.98 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1037.90 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 48550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 17825.239135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3190.498487 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 18342.849091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 8610 17.73% 17.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 4856 10.00% 27.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 981 2.02% 29.76% # Bytes accessed per row activation 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35.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 37 0.08% 36.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 306 0.63% 36.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 22 0.05% 36.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 33 0.07% 36.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 21 0.04% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 99 0.20% 37.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 20 0.04% 37.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 170 0.35% 37.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 13 0.03% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 137 0.28% 37.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 12 0.02% 37.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 29 0.06% 37.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 10 0.02% 37.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 139 0.29% 38.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 7 0.01% 38.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 11 0.02% 38.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 378 0.78% 38.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 7 0.01% 38.96% # Bytes accessed per row activation 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0.01% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 7 0.01% 39.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 5 0.01% 39.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 411 0.85% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 4 0.01% 40.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 1 0.00% 40.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 132 0.27% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 3 0.01% 40.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 6 0.01% 40.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 7 0.01% 40.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 67 0.14% 40.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 5 0.01% 40.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 5 0.01% 40.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 3 0.01% 40.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 73 0.15% 40.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 384 0.79% 41.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 41.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 7 0.01% 41.71% # Bytes accessed per row activation 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0.00% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 6 0.01% 42.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 4 0.01% 42.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 263 0.54% 42.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 1 0.00% 42.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 3 0.01% 42.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 5 0.01% 42.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 131 0.27% 43.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 4 0.01% 43.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 9 0.02% 43.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.01% 43.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 70 0.14% 43.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 3 0.01% 43.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 4 0.01% 43.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 5 0.01% 43.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 103 0.21% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 4 0.01% 43.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 9 0.02% 43.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 323 0.67% 44.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 3 0.01% 44.21% # Bytes accessed per row activation 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0.60% 45.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 2 0.00% 45.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 14 0.03% 45.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 4 0.01% 45.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 128 0.26% 45.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 65 0.13% 45.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 1 0.00% 45.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 415 0.85% 46.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 128 0.26% 46.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 291 0.60% 47.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 1 0.00% 47.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 81 0.17% 47.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 3 0.01% 47.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 320 0.66% 48.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 64 0.13% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 64 0.13% 48.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 128 0.26% 48.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 256 0.53% 49.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 32 0.07% 49.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 64 0.13% 49.43% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 414 0.85% 64.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 65 0.13% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 129 0.27% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 291 0.60% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 80 0.16% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 4 0.01% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 320 0.66% 66.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 65 0.13% 66.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 64 0.13% 66.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 128 0.26% 66.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 32 0.07% 67.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 128 0.26% 67.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 377 0.78% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 68 0.14% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 65 0.13% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 125 0.26% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 410 0.84% 69.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 1 0.00% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 64 0.13% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 65 0.13% 70.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 363 0.75% 70.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 96 0.20% 71.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 68 0.14% 71.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 256 0.53% 72.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 64 0.13% 72.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 72.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 72 0.15% 72.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 642 1.32% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 72 0.15% 73.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 1 0.00% 73.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 63 0.13% 73.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 256 0.53% 74.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 68 0.14% 74.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 96 0.20% 74.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 363 0.75% 75.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 64 0.13% 75.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 64 0.13% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 1 0.00% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 410 0.84% 76.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 125 0.26% 77.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 65 0.13% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 68 0.14% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 376 0.77% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 128 0.26% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 65 0.13% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 32 0.07% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 256 0.53% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 128 0.26% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 64 0.13% 79.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 320 0.66% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 4 0.01% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 80 0.16% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 292 0.60% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 129 0.27% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 65 0.13% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 413 0.85% 82.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 129 0.27% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 292 0.60% 83.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 82 0.17% 83.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 3 0.01% 83.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 320 0.66% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 65 0.13% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 65 0.13% 84.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 128 0.26% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 29 0.06% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 127 0.26% 85.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 375 0.77% 86.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 70 0.14% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 1 0.00% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 64 0.13% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 125 0.26% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 406 0.84% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 64 0.13% 88.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 364 0.75% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 96 0.20% 89.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 69 0.14% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 258 0.53% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 71 0.15% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4686 9.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48550 # Bytes accessed per row activation +system.physmem.totQLat 326412969750 # Total ticks spent queuing +system.physmem.totMemAccLat 407861489750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67386725000 # Total ticks spent in databus transfers +system.physmem.totBankLat 14061795000 # Total ticks spent accessing banks +system.physmem.avgQLat 24219.38 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1043.37 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30262.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30262.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage @@ -513,328 +523,330 @@ system.physmem.busUtilRead 2.80 # Da system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing -system.physmem.readRowHits 13424164 # Number of row buffer hits during reads -system.physmem.writeRowHits 39490 # Number of row buffer hits during writes +system.physmem.readRowHits 13434104 # Number of row buffer hits during reads +system.physmem.writeRowHits 39465 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 88.17 # Row buffer hit rate for writes -system.physmem.avgGap 172678.78 # Average gap between requests +system.physmem.writeRowHitRate 88.14 # Row buffer hit rate for writes +system.physmem.avgGap 172554.83 # Average gap between requests system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.76 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55673060 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13803640 # Transaction distribution -system.membus.trans_dist::ReadResp 13803640 # Transaction distribution -system.membus.trans_dist::WriteReq 432247 # Transaction distribution -system.membus.trans_dist::WriteResp 432247 # Transaction distribution -system.membus.trans_dist::Writeback 17102 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2372 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2372 # Transaction distribution -system.membus.trans_dist::ReadExReq 28053 # Transaction distribution -system.membus.trans_dist::ReadExResp 28053 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 734214 # Packet count per connected master and slave (bytes) +system.physmem.prechargeAllPercent 0.75 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 55672581 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13813538 # Transaction distribution +system.membus.trans_dist::ReadResp 13813538 # Transaction distribution +system.membus.trans_dist::WriteReq 432230 # Transaction distribution +system.membus.trans_dist::WriteResp 432230 # Transaction distribution +system.membus.trans_dist::Writeback 17092 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2370 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2370 # Transaction distribution +system.membus.trans_dist::ReadExReq 28046 # Transaction distribution +system.membus.trans_dist::ReadExResp 28046 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 733938 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1686398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26863328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26863328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28549726 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 738102 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1686036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26883424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26883424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28569460 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 737821 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5093464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5832006 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107453312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107453312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113285318 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133818970 # Total data (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5091480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5829741 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107533696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107533696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113363437 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133817886 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 417653000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 418359500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 204500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14595653500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14607428500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1597948868 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1598779620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30334798000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30355600750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 63262 # number of replacements -system.l2c.tags.tagsinuse 50391.923695 # Cycle average of tags in use -system.l2c.tags.total_refs 1749292 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128659 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.596344 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375568862000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36846.357046 # Average occupied blocks per requestor +system.l2c.tags.replacements 63253 # number of replacements +system.l2c.tags.tagsinuse 50392.264505 # Cycle average of tags in use +system.l2c.tags.total_refs 1749443 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128649 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.598574 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375574111000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36861.205107 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5224.016956 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3834.498559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5227.235315 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3840.097341 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 503.830830 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 691.484420 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832714 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1696.766805 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1584.142905 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562231 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 502.876093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 689.542033 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.851035 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974650 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1682.063126 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1580.426346 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562457 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079761 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058595 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007688 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010551 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000150 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024172 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768920 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8708 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3160 # number of ReadReq hits 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+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62775.676835 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63193.942271 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63013.907507 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -987,52 +1011,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58815755 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1021426 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1021425 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432247 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432247 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1513 # Transaction distribution +system.toL2Bus.throughput 58816500 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1021450 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1021449 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432230 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432230 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265546 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1512 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80586 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80586 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831264 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423236 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15497 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52067 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3322064 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26578304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37416070 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21580 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64100814 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141271334 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 101600 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2179143758 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80593 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80593 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831311 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423002 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52276 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3322226 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26580608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37417965 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 85464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64105945 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141275262 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 99532 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2179112263 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1872769954 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1872836168 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1848854181 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1848885181 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10116966 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10174967 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30973250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31036489 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48762849 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13795996 # Transaction distribution -system.iobus.trans_dist::ReadResp 13795996 # Transaction distribution -system.iobus.trans_dist::WriteReq 2775 # Transaction distribution -system.iobus.trans_dist::WriteResp 2775 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11418 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3030 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48762826 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13805907 # Transaction distribution +system.iobus.trans_dist::ReadResp 13805907 # Transaction distribution +system.iobus.trans_dist::WriteReq 2774 # Transaction distribution +system.iobus.trans_dist::WriteResp 2774 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 719202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 718942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1048,18 +1072,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 734214 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26863328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26863328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27597542 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15382 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 733938 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26883424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26883424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27617362 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715532 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715269 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1075,14 +1099,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 738102 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107453312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107453312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108191414 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209190 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7974000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 737821 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107533696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107533696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108271517 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209194 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1515000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1094,7 +1118,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 360101000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 359973000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -1126,35 +1150,35 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13431664000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13441712000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 731439000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 731164000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36823110000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36852557250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7991455 # DTB read hits -system.cpu0.dtb.read_misses 6184 # DTB read misses -system.cpu0.dtb.write_hits 6591541 # DTB write hits +system.cpu0.dtb.read_hits 7990938 # DTB read hits +system.cpu0.dtb.read_misses 6181 # DTB read misses +system.cpu0.dtb.write_hits 6591681 # DTB write hits system.cpu0.dtb.write_misses 1989 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5665 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 118 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 119 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 208 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7997639 # DTB read accesses -system.cpu0.dtb.write_accesses 6593530 # DTB write accesses +system.cpu0.dtb.read_accesses 7997119 # DTB read accesses +system.cpu0.dtb.write_accesses 6593670 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14582996 # DTB hits -system.cpu0.dtb.misses 8173 # DTB misses -system.cpu0.dtb.accesses 14591169 # DTB accesses -system.cpu0.itb.inst_hits 32325256 # ITB inst hits -system.cpu0.itb.inst_misses 3454 # ITB inst misses +system.cpu0.dtb.hits 14582619 # DTB hits +system.cpu0.dtb.misses 8170 # DTB misses +system.cpu0.dtb.accesses 14590789 # DTB accesses +system.cpu0.itb.inst_hits 32323173 # ITB inst hits +system.cpu0.itb.inst_misses 3455 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1170,400 +1194,400 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32328710 # ITB inst accesses -system.cpu0.itb.hits 32325256 # DTB hits -system.cpu0.itb.misses 3454 # DTB misses -system.cpu0.itb.accesses 32328710 # DTB accesses -system.cpu0.numCycles 113673861 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32326628 # ITB inst accesses +system.cpu0.itb.hits 32323173 # DTB hits +system.cpu0.itb.misses 3455 # DTB misses +system.cpu0.itb.accesses 32326628 # DTB accesses +system.cpu0.numCycles 113706934 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31847112 # Number of instructions committed -system.cpu0.committedOps 42008964 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37152656 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses -system.cpu0.num_func_calls 1198427 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4245737 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37152656 # number of integer instructions -system.cpu0.num_fp_insts 5018 # number of float instructions -system.cpu0.num_int_register_reads 189368889 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39264582 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written -system.cpu0.num_mem_refs 15250074 # number of memory refs -system.cpu0.num_load_insts 8359762 # Number of load instructions -system.cpu0.num_store_insts 6890312 # Number of store instructions -system.cpu0.num_idle_cycles 110868175.114613 # Number of idle cycles -system.cpu0.num_busy_cycles 2805685.885387 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024682 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975318 # Percentage of idle cycles +system.cpu0.committedInsts 31845607 # Number of instructions committed +system.cpu0.committedOps 42007795 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37151613 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses +system.cpu0.num_func_calls 1198507 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4245528 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37151613 # number of integer instructions +system.cpu0.num_fp_insts 4937 # number of float instructions +system.cpu0.num_int_register_reads 189362798 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39261274 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written +system.cpu0.num_mem_refs 15249830 # number of memory refs +system.cpu0.num_load_insts 8359344 # Number of load instructions +system.cpu0.num_store_insts 6890486 # Number of store instructions +system.cpu0.num_idle_cycles 110900908.371908 # Number of idle cycles +system.cpu0.num_busy_cycles 2806025.628092 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024678 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975322 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891412 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.602619 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43641790 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891924 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.929942 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8178595250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 492.265032 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.623785 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 11.713802 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.961455 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014890 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.022879 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31851952 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8051251 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3738587 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43641790 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31851952 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8051251 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3738587 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43641790 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31851952 # 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percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015867 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013368 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.025505 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.136631 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.834983 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970753 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015892 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013350 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6862135 # number of ReadReq hits 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overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6772754 # number of overall hits -system.cpu0.dcache.overall_hits::total 22730458 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 176872 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 63653 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 271744 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 512269 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167825 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 28657 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 610336 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 806818 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6461 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1738 # number of LoadLockedReq misses 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accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77427 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250374 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138143 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34804 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74444 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu1.data 1921006239 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27260222316 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 29181228555 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1921006239 # number of overall miss cycles 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3227459 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7654834 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24049545 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13167252 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3227459 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7654834 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24049545 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025127 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033793 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055338 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037032 # miss rate for ReadReq accesses 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0.020286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049859 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043028 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020218 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011523 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011523 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12227.125980 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12926.558181 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12698.318145 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33253.882507 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35539.841568 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34741.616574 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.301496 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11583.283747 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11427.249655 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011525 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011525 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12245.686678 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12959.606210 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.544437 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33315.433109 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35310.030029 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34614.428054 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.665513 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11526.466466 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11387.033208 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1576,27 +1600,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2096740 # DTB read hits -system.cpu1.dtb.read_misses 2075 # DTB read misses -system.cpu1.dtb.write_hits 1419315 # DTB write hits +system.cpu1.dtb.read_hits 2096419 # DTB read hits +system.cpu1.dtb.read_misses 2083 # DTB read misses +system.cpu1.dtb.write_hits 1418166 # DTB write hits system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1735 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1734 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2098815 # DTB read accesses -system.cpu1.dtb.write_accesses 1419688 # DTB write accesses +system.cpu1.dtb.read_accesses 2098502 # DTB read accesses +system.cpu1.dtb.write_accesses 1418539 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3516055 # DTB hits -system.cpu1.dtb.misses 2448 # DTB misses -system.cpu1.dtb.accesses 3518503 # DTB accesses -system.cpu1.itb.inst_hits 8182654 # ITB inst hits -system.cpu1.itb.inst_misses 1200 # ITB inst misses +system.cpu1.dtb.hits 3514585 # DTB hits +system.cpu1.dtb.misses 2456 # DTB misses +system.cpu1.dtb.accesses 3517041 # DTB accesses +system.cpu1.itb.inst_hits 8182058 # ITB inst hits +system.cpu1.itb.inst_misses 1201 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1605,73 +1629,73 @@ system.cpu1.itb.flush_tlb 277 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 888 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 889 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8183854 # ITB inst accesses -system.cpu1.itb.hits 8182654 # DTB hits -system.cpu1.itb.misses 1200 # DTB misses -system.cpu1.itb.accesses 8183854 # DTB accesses -system.cpu1.numCycles 581318737 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8183259 # ITB inst accesses +system.cpu1.itb.hits 8182058 # DTB hits +system.cpu1.itb.misses 1201 # DTB misses +system.cpu1.itb.accesses 8183259 # DTB accesses +system.cpu1.numCycles 581387993 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7974693 # Number of instructions committed -system.cpu1.committedOps 10126531 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9058549 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1938 # Number of float alu accesses -system.cpu1.num_func_calls 304877 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1114107 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9058549 # number of integer instructions -system.cpu1.num_fp_insts 1938 # number of float instructions -system.cpu1.num_int_register_reads 52214198 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9844324 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1424 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_mem_refs 3684398 # number of memory refs -system.cpu1.num_load_insts 2190368 # Number of load instructions -system.cpu1.num_store_insts 1494030 # Number of store instructions -system.cpu1.num_idle_cycles 546218260.044225 # Number of idle cycles -system.cpu1.num_busy_cycles 35100476.955774 # Number of busy cycles -system.cpu1.not_idle_fraction 0.060381 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.939619 # Percentage of idle cycles +system.cpu1.committedInsts 7973391 # Number of instructions committed +system.cpu1.committedOps 10123180 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9055145 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses +system.cpu1.num_func_calls 304839 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1113920 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9055145 # number of integer instructions +system.cpu1.num_fp_insts 2019 # number of float instructions +system.cpu1.num_int_register_reads 52196104 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9841677 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written +system.cpu1.num_mem_refs 3682729 # number of memory refs +system.cpu1.num_load_insts 2189938 # Number of load instructions +system.cpu1.num_store_insts 1492791 # Number of store instructions +system.cpu1.num_idle_cycles 546287151.729317 # Number of idle cycles +system.cpu1.num_busy_cycles 35100841.270683 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060374 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939626 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4723221 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3843292 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 222521 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3120017 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2528037 # Number of BTB hits +system.cpu2.branchPred.lookups 4728615 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3846891 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223365 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3153803 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2531568 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 81.026385 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 412365 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21211 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.270328 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 413323 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21760 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10969613 # DTB read hits -system.cpu2.dtb.read_misses 23045 # DTB read misses -system.cpu2.dtb.write_hits 3352330 # DTB write hits +system.cpu2.dtb.read_hits 10972958 # DTB read hits +system.cpu2.dtb.read_misses 22884 # DTB read misses +system.cpu2.dtb.write_hits 3353841 # DTB write hits system.cpu2.dtb.write_misses 6440 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2328 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2329 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 684 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10992658 # DTB read accesses -system.cpu2.dtb.write_accesses 3358770 # DTB write accesses +system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10995842 # DTB read accesses +system.cpu2.dtb.write_accesses 3360281 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14321943 # DTB hits -system.cpu2.dtb.misses 29485 # DTB misses -system.cpu2.dtb.accesses 14351428 # DTB accesses -system.cpu2.itb.inst_hits 4048520 # ITB inst hits -system.cpu2.itb.inst_misses 4581 # ITB inst misses +system.cpu2.dtb.hits 14326799 # DTB hits +system.cpu2.dtb.misses 29324 # DTB misses +system.cpu2.dtb.accesses 14356123 # DTB accesses +system.cpu2.itb.inst_hits 4052293 # ITB inst hits +system.cpu2.itb.inst_misses 4591 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1684,110 +1708,110 @@ system.cpu2.itb.flush_entries 1671 # Nu system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1028 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4053101 # ITB inst accesses -system.cpu2.itb.hits 4048520 # DTB hits -system.cpu2.itb.misses 4581 # DTB misses -system.cpu2.itb.accesses 4053101 # DTB accesses -system.cpu2.numCycles 88363580 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4056884 # ITB inst accesses +system.cpu2.itb.hits 4052293 # DTB hits +system.cpu2.itb.misses 4591 # DTB misses +system.cpu2.itb.accesses 4056884 # DTB accesses +system.cpu2.numCycles 88364936 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9342746 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32497136 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4723221 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2940402 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6855397 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1756636 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50446 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18848050 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 925 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 34178 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 721824 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4047074 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289511 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37061318 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.053700 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.440521 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9352566 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32517206 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4728615 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2944891 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6861610 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1759869 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50868 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18844594 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 866 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32744 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 721068 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 448 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4050852 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289827 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1989 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37074469 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.054164 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.440934 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30210914 81.52% 81.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385385 1.04% 82.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 515477 1.39% 83.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 820134 2.21% 86.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 628486 1.70% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 342820 0.93% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1044433 2.82% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 229207 0.62% 92.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2884462 7.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30218075 81.51% 81.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 386681 1.04% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516163 1.39% 83.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 819367 2.21% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 628808 1.70% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344228 0.93% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1045241 2.82% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 229591 0.62% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2886315 7.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37061318 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053452 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367766 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9926500 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19460558 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6238388 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 279816 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1155131 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608208 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53066 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36958585 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178391 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1155131 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10476553 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6920166 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11076723 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5947862 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1483966 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34870863 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2458 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 328650 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 889849 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 96 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37358262 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 159586833 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148423376 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3369 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26507725 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10850536 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 232822 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 209087 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3256835 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6623705 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3904787 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530493 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 775113 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32195808 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 505146 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34809127 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54913 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7172484 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19086467 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 147942 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37061318 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.939231 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.598560 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37074469 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053512 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367988 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9932859 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19459354 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6244628 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 279238 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1157490 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 609849 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53110 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36985250 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 179754 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1157490 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10483306 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6921288 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11074515 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5953553 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1483425 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34895792 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 326661 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 892066 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 111 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37386016 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 159700078 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148525933 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3408 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26513636 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10872379 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 232480 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 208815 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3253838 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6628841 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3905916 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 536820 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 771052 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32212739 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 505163 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34823222 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55040 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7182108 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19097970 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 148083 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37074469 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.939278 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.598547 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24455957 65.99% 65.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3833682 10.34% 76.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2322342 6.27% 82.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2005181 5.41% 88.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2795966 7.54% 95.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 971107 2.62% 98.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 498292 1.34% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144261 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34530 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24463826 65.99% 65.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3833492 10.34% 76.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2324654 6.27% 82.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2008652 5.42% 88.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2796278 7.54% 95.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 971248 2.62% 98.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 496274 1.34% 99.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144890 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35155 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37061318 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37074469 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19660 1.28% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19545 1.28% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available @@ -1816,13 +1840,13 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1402550 91.51% 92.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110445 7.21% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1401661 91.55% 92.82% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109897 7.18% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61175 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19747110 56.73% 56.91% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 27980 0.08% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61115 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19755783 56.73% 56.91% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28013 0.08% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.99% # Type of FU issued @@ -1838,7 +1862,7 @@ system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.99% # Ty system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.99% # Type of FU issued @@ -1850,114 +1874,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 388 0.00% 56.99% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11452276 32.90% 89.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3520179 10.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11456328 32.90% 89.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3521577 10.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34809127 # Type of FU issued -system.cpu2.iq.rate 0.393931 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1532656 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044030 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108288948 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39878610 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28070823 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7546 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3965 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3367 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36276582 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4026 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205280 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34823222 # Type of FU issued +system.cpu2.iq.rate 0.394084 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1531104 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043968 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108328678 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39905127 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28084625 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7572 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4019 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3368 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36289170 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4041 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206363 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1528845 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1875 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9489 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562920 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1533130 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9465 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562980 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5328051 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344229 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5327720 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344503 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1155131 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5244365 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 89322 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32783919 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60352 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6623705 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3904787 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362611 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 30261 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2481 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9489 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 106879 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89021 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 195900 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33894861 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11182187 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 914266 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1157490 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5247900 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 88519 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32800222 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60619 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6628841 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3905916 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362644 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29757 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2395 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9465 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107959 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89408 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197367 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33908136 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11185478 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 915086 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82965 # number of nop insts executed -system.cpu2.iew.exec_refs 14668868 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3706634 # Number of branches executed -system.cpu2.iew.exec_stores 3486681 # Number of stores executed -system.cpu2.iew.exec_rate 0.383584 # Inst execution rate -system.cpu2.iew.wb_sent 33494578 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28074190 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16115456 # num instructions producing a value -system.cpu2.iew.wb_consumers 29164308 # num instructions consuming a value +system.cpu2.iew.exec_nop 82320 # number of nop insts executed +system.cpu2.iew.exec_refs 14673656 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3709694 # Number of branches executed +system.cpu2.iew.exec_stores 3488178 # Number of stores executed +system.cpu2.iew.exec_rate 0.383728 # Inst execution rate +system.cpu2.iew.wb_sent 33508440 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28087993 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16121354 # num instructions producing a value +system.cpu2.iew.wb_consumers 29172590 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317712 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.552575 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317864 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.552620 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7126752 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357204 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 170224 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35906001 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.707499 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.751012 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7137877 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357080 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171034 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35916785 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.707415 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.751354 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27147368 75.61% 75.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4230684 11.78% 87.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1251387 3.49% 90.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 639812 1.78% 92.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 559957 1.56% 94.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 318640 0.89% 95.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 417979 1.16% 96.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 311730 0.87% 97.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1028444 2.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27161260 75.62% 75.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4227698 11.77% 87.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1252285 3.49% 90.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 635084 1.77% 92.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 561790 1.56% 94.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 319405 0.89% 95.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 418201 1.16% 96.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 311340 0.87% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1029722 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35906001 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20561870 # Number of instructions committed -system.cpu2.commit.committedOps 25403458 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35916785 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20564616 # Number of instructions committed +system.cpu2.commit.committedOps 25408067 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8436727 # Number of memory references committed -system.cpu2.commit.loads 5094860 # Number of loads committed -system.cpu2.commit.membars 94449 # Number of memory barriers committed -system.cpu2.commit.branches 3185060 # Number of branches committed +system.cpu2.commit.refs 8438647 # Number of memory references committed +system.cpu2.commit.loads 5095711 # Number of loads committed +system.cpu2.commit.membars 94423 # Number of memory barriers committed +system.cpu2.commit.branches 3185422 # Number of branches committed system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22606405 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295605 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1028444 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 22610745 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295586 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1029722 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66885510 # The number of ROB reads -system.cpu2.rob.rob_writes 66259648 # The number of ROB writes -system.cpu2.timesIdled 359925 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51302262 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3553994827 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20506347 # Number of Instructions Simulated -system.cpu2.committedOps 25347935 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20506347 # Number of Instructions Simulated -system.cpu2.cpi 4.309084 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.309084 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232068 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232068 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157055367 # number of integer regfile reads -system.cpu2.int_regfile_writes 29889640 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22622 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9269321 # number of misc regfile reads -system.cpu2.misc_regfile_writes 242794 # number of misc regfile writes +system.cpu2.rob.rob_reads 66910934 # The number of ROB reads +system.cpu2.rob.rob_writes 66293514 # The number of ROB writes +system.cpu2.timesIdled 359960 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51290467 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3553935024 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20509130 # Number of Instructions Simulated +system.cpu2.committedOps 25352581 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20509130 # Number of Instructions Simulated +system.cpu2.cpi 4.308566 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.308566 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232096 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232096 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157121826 # number of integer regfile reads +system.cpu2.int_regfile_writes 29906145 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22616 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20826 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9261107 # number of misc regfile reads +system.cpu2.misc_regfile_writes 242774 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1972,10 +1996,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1346583006000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1346583006000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1347589582250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1347589582250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 0865afb47..bd21d2c8f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,18 +602,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=DerivO3CPU @@ -581,6 +647,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -643,6 +711,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -655,12 +724,14 @@ predType=tournament [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system @@ -668,15 +739,18 @@ sys=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -685,16 +759,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -703,22 +780,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -727,22 +808,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -751,10 +836,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -763,124 +850,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -889,10 +997,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -901,16 +1011,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -919,16 +1032,19 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -947,30 +1063,36 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -983,6 +1105,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1005,6 +1128,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1014,6 +1138,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1036,6 +1161,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1043,6 +1169,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1054,6 +1181,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1080,6 +1208,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1091,19 +1220,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -1113,6 +1246,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -1122,6 +1256,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1150,6 +1285,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -1159,8 +1295,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1172,6 +1340,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -1187,6 +1356,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -1201,6 +1372,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1210,6 +1382,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1231,8 +1404,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1241,6 +1416,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1251,6 +1427,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1261,6 +1438,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1271,6 +1449,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1285,6 +1464,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1298,6 +1478,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1315,6 +1496,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1327,6 +1509,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1338,6 +1521,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1348,6 +1532,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1360,6 +1545,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1373,6 +1559,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1383,6 +1570,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1393,6 +1581,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1403,6 +1592,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1415,6 +1605,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1429,6 +1620,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1441,6 +1633,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1455,6 +1648,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1465,6 +1659,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1475,6 +1670,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1485,6 +1681,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1493,6 +1690,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1501,6 +1699,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1510,11 +1709,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index cc97b6f9f..5fef90c5a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,166 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.549325 # Number of seconds simulated -sim_ticks 2549325180000 # Number of ticks simulated -final_tick 2549325180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.549345 # Number of seconds simulated +sim_ticks 2549345168000 # Number of ticks simulated +final_tick 2549345168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61075 # Simulator instruction rate (inst/s) -host_op_rate 78588 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2581455626 # Simulator tick rate (ticks/s) -host_mem_usage 428832 # Number of bytes of host memory used -host_seconds 987.55 # Real time elapsed on the host -sim_insts 60314884 # Number of instructions simulated -sim_ops 77609482 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 48945 # Simulator instruction rate (inst/s) +host_op_rate 62980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2068782078 # Simulator tick rate (ticks/s) +host_mem_usage 448444 # Number of bytes of host memory used +host_seconds 1232.29 # Real time elapsed on the host +sim_insts 60314699 # Number of instructions simulated +sim_ops 77609228 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 507840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4720464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 291712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4372184 # Number of bytes read from this memory -system.physmem.bytes_read::total 131005480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 507840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 291712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785664 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521520 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494580 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801764 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 498624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4680272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 301248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4410392 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 498624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 301248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784640 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521380 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494720 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800740 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7935 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73791 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68321 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293464 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59151 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380380 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373645 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813176 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47506897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 678 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7791 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68918 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293442 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59135 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380345 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373680 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813160 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47506524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 199206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1851652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 114427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1715036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51388297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 199206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 114427 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313633 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586265 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2668064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47506897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 195589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1835872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 118167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1730010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51387342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 195589 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 118167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484554 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596773 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586315 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47506524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 199206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2448485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 114427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2301301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54056362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293464 # Number of read requests accepted -system.physmem.writeReqs 813176 # Number of write requests accepted -system.physmem.readBursts 15293464 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813176 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978217536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 564160 # Total number of bytes read from write queue -system.physmem.bytesWritten 6910272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131005480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801764 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8815 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705189 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4711 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955865 # Per bank write bursts -system.physmem.perBankRdBursts::1 955523 # Per bank write bursts -system.physmem.perBankRdBursts::2 954611 # Per bank write bursts -system.physmem.perBankRdBursts::3 954852 # Per bank write bursts -system.physmem.perBankRdBursts::4 955764 # Per bank write bursts -system.physmem.perBankRdBursts::5 955945 # Per bank write bursts -system.physmem.perBankRdBursts::6 954843 # Per bank write bursts -system.physmem.perBankRdBursts::7 954680 # Per bank write bursts -system.physmem.perBankRdBursts::8 956251 # Per bank write bursts -system.physmem.perBankRdBursts::9 955822 # Per bank write bursts -system.physmem.perBankRdBursts::10 954302 # Per bank write bursts -system.physmem.perBankRdBursts::11 954022 # Per bank write bursts -system.physmem.perBankRdBursts::12 956218 # Per bank write bursts -system.physmem.perBankRdBursts::13 955977 # Per bank write bursts -system.physmem.perBankRdBursts::14 955052 # Per bank write bursts -system.physmem.perBankRdBursts::15 954922 # Per bank write bursts -system.physmem.perBankWrBursts::0 6685 # Per bank write bursts -system.physmem.perBankWrBursts::1 6462 # Per bank write bursts -system.physmem.perBankWrBursts::2 6616 # Per bank write bursts -system.physmem.perBankWrBursts::3 6625 # Per bank write bursts -system.physmem.perBankWrBursts::4 6578 # Per bank write bursts -system.physmem.perBankWrBursts::5 6834 # Per bank write bursts -system.physmem.perBankWrBursts::6 6825 # Per bank write bursts -system.physmem.perBankWrBursts::7 6778 # Per bank write bursts -system.physmem.perBankWrBursts::8 7112 # Per bank write bursts -system.physmem.perBankWrBursts::9 6876 # Per bank write bursts -system.physmem.perBankWrBursts::10 6540 # Per bank write bursts -system.physmem.perBankWrBursts::11 6189 # Per bank write bursts -system.physmem.perBankWrBursts::12 7142 # Per bank write bursts -system.physmem.perBankWrBursts::13 6759 # Per bank write bursts -system.physmem.perBankWrBursts::14 7042 # Per bank write bursts -system.physmem.perBankWrBursts::15 6910 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 195589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2432645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 118167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2316325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54054984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293442 # Number of read requests accepted +system.physmem.writeReqs 813160 # Number of write requests accepted +system.physmem.readBursts 15293442 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813160 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978220224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 560064 # Total number of bytes read from write queue +system.physmem.bytesWritten 6909248 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131004072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800740 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8751 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705188 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4685 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955866 # Per bank write bursts +system.physmem.perBankRdBursts::1 955512 # Per bank write bursts +system.physmem.perBankRdBursts::2 954595 # Per bank write bursts +system.physmem.perBankRdBursts::3 954812 # Per bank write bursts +system.physmem.perBankRdBursts::4 955762 # Per bank write bursts +system.physmem.perBankRdBursts::5 955910 # Per bank write bursts +system.physmem.perBankRdBursts::6 954892 # Per bank write bursts +system.physmem.perBankRdBursts::7 954654 # Per bank write bursts +system.physmem.perBankRdBursts::8 956247 # Per bank write bursts +system.physmem.perBankRdBursts::9 955899 # Per bank write bursts +system.physmem.perBankRdBursts::10 954311 # Per bank write bursts +system.physmem.perBankRdBursts::11 954068 # Per bank write bursts +system.physmem.perBankRdBursts::12 956211 # Per bank write bursts +system.physmem.perBankRdBursts::13 955980 # Per bank write bursts +system.physmem.perBankRdBursts::14 955097 # Per bank write bursts +system.physmem.perBankRdBursts::15 954875 # Per bank write bursts +system.physmem.perBankWrBursts::0 6687 # Per bank write bursts +system.physmem.perBankWrBursts::1 6461 # Per bank write bursts +system.physmem.perBankWrBursts::2 6610 # Per bank write bursts +system.physmem.perBankWrBursts::3 6631 # Per bank write bursts +system.physmem.perBankWrBursts::4 6571 # Per bank write bursts +system.physmem.perBankWrBursts::5 6830 # Per bank write bursts +system.physmem.perBankWrBursts::6 6820 # Per bank write bursts +system.physmem.perBankWrBursts::7 6764 # Per bank write bursts +system.physmem.perBankWrBursts::8 7113 # Per bank write bursts +system.physmem.perBankWrBursts::9 6879 # Per bank write bursts +system.physmem.perBankWrBursts::10 6545 # Per bank write bursts +system.physmem.perBankWrBursts::11 6197 # Per bank write bursts +system.physmem.perBankWrBursts::12 7141 # Per bank write bursts +system.physmem.perBankWrBursts::13 6760 # Per bank write bursts +system.physmem.perBankWrBursts::14 7037 # Per bank write bursts +system.physmem.perBankWrBursts::15 6911 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2549324058500 # Total gap between requests +system.physmem.totGap 2549344036000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 42 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154606 # Read request sizes (log2) +system.physmem.readPktSize::6 154584 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754025 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59151 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1187642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1126920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1081304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3687011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2647213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2642028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2655762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 54010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 60825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59135 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1194358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1134175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1088302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3688965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2641659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2636525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2648641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52098 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 58013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -171,418 +159,411 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11344.953359 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1015.074534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16830.192081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23626 27.21% 27.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14089 16.23% 43.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2724 3.14% 46.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2126 2.45% 49.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1310 1.51% 50.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1204 1.39% 51.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 811 0.93% 52.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1018 1.17% 54.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 572 0.66% 54.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 583 0.67% 55.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 533 0.61% 55.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 603 0.69% 56.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 265 0.31% 57.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 147 0.17% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 578 0.67% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 113 0.13% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 129 0.15% 58.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 237 0.27% 58.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 56 0.06% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 502 0.58% 59.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 39 0.04% 59.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 171 0.20% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 11 0.01% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 115 0.13% 59.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 15 0.02% 59.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 109 0.13% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 18 0.02% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 54 0.06% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 24 0.03% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 490 0.56% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 17 0.02% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 7 0.01% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 154 0.18% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 14 0.02% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 32 0.04% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 7 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 95 0.11% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 14 0.02% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 9 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 155 0.18% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 16 0.02% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 10 0.01% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 408 0.47% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 96 0.11% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 10 0.01% 61.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 20 0.02% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.01% 61.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 86 0.10% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 6 0.01% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 21 0.02% 62.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 12 0.01% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 58 0.07% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 407 0.47% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 10 0.01% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 18 0.02% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 3 0.00% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 75 0.09% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 12 0.01% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 7 0.01% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 139 0.16% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 8 0.01% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 72 0.08% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 17 0.02% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 76 0.09% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 9 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 13 0.01% 63.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 144 0.17% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 9 0.01% 63.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 13 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 12 0.01% 64.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 6 0.01% 64.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 262 0.30% 64.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 5 0.01% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 136 0.16% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 8 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 21 0.02% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 74 0.09% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 8 0.01% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 452 0.52% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 4 0.00% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 13 0.01% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 23 0.03% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 4 0.00% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 73 0.08% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 3 0.00% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 132 0.15% 65.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 243 0.28% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 128 0.15% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 66 0.08% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 67 0.08% 66.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 450 0.52% 66.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 67 0.08% 66.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 2 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 1 0.00% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 251 0.29% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 128 0.15% 67.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 66 0.08% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 387 0.45% 68.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 67 0.08% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11719 1 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 121 0.14% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 66 0.08% 68.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 380 0.44% 68.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 37 0.04% 68.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 69 0.08% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 65 0.07% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 389 0.45% 69.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 129 0.15% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 66 0.08% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 120 0.14% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 443 0.51% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 57 0.07% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 13 0.01% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 119 0.14% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 388 0.45% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 123 0.14% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15751 1 0.00% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 64 0.07% 71.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 66 0.08% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16327 1 0.00% 71.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 526 0.61% 71.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 68 0.08% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 64 0.07% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 122 0.14% 72.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 391 0.45% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 120 0.14% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 15 0.02% 72.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 57 0.07% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 444 0.51% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 119 0.14% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 66 0.08% 73.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 129 0.15% 73.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 384 0.44% 74.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 64 0.07% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 70 0.08% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 37 0.04% 74.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 1 0.00% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 382 0.44% 74.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 65 0.07% 74.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 119 0.14% 75.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 66 0.08% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 385 0.44% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 68 0.08% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 128 0.15% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 69 0.08% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 1 0.00% 75.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 253 0.29% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 132 0.15% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22976-22983 1 0.00% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 67 0.08% 76.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 450 0.52% 76.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 67 0.08% 77.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 129 0.15% 77.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 137 0.16% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 1 0.00% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 129 0.15% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 67 0.08% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 67 0.08% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 448 0.52% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25671 1 0.00% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 66 0.08% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 134 0.15% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 253 0.29% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 68 0.08% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 129 0.15% 78.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 1 0.00% 78.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 68 0.08% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 384 0.44% 79.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 66 0.08% 79.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 119 0.14% 79.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 64 0.07% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 380 0.44% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 1 0.00% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 37 0.04% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 72 0.08% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 65 0.07% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 385 0.44% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 129 0.15% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 64 0.07% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 119 0.14% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 443 0.51% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 56 0.06% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 13 0.01% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 119 0.14% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 2 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 1 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 389 0.45% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31808-31815 1 0.00% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 124 0.14% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 66 0.08% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 66 0.08% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 65 0.07% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 125 0.14% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 390 0.45% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 119 0.14% 84.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 13 0.01% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 56 0.06% 84.27% # Bytes accessed per row activation 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Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 542 0.63% 54.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 595 0.69% 55.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 544 0.63% 56.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 497 0.57% 56.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 259 0.30% 56.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 256 0.30% 57.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 151 0.17% 57.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 457 0.53% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 109 0.13% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 146 0.17% 58.22% # Bytes accessed per row activation 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7 0.01% 61.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 145 0.17% 61.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 10 0.01% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 20 0.02% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 16 0.02% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 418 0.48% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 13 0.02% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 5 0.01% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 16 0.02% 62.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 22 0.03% 62.57% # Bytes accessed per row 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63 0.07% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 10 0.01% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 4 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 9 0.01% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 18 0.02% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 6 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 188 0.22% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 4 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 12 0.01% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 264 0.30% 65.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 8 0.01% 65.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 14 0.02% 65.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 15 0.02% 65.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 4 0.00% 65.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 8 0.01% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 3 0.00% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 139 0.16% 65.39% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::51072-51079 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86834 # Bytes accessed per row activation -system.physmem.totQLat 369633946000 # Total ticks spent queuing -system.physmem.totMemAccLat 463601929750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76423245000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17544738750 # Total ticks spent accessing banks -system.physmem.avgQLat 24183.35 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1147.87 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::51200-51207 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86636 # Bytes accessed per row activation +system.physmem.totQLat 369559391250 # Total ticks spent queuing +system.physmem.totMemAccLat 463610140000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76423455000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17627293750 # Total ticks spent accessing banks +system.physmem.avgQLat 24178.40 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1153.26 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30331.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30331.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s @@ -592,24 +573,35 @@ system.physmem.busUtilRead 3.00 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing -system.physmem.readRowHits 15212610 # Number of row buffer hits during reads -system.physmem.writeRowHits 93178 # Number of row buffer hits during writes +system.physmem.readRowHits 15212838 # Number of row buffer hits during reads +system.physmem.writeRowHits 93174 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate 86.29 # Row buffer hit rate for writes -system.physmem.avgGap 158277.83 # Average gap between requests +system.physmem.avgGap 158279.45 # Average gap between requests system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 1.88 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54996997 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346113 # Transaction distribution -system.membus.trans_dist::ReadResp 16346116 # Transaction distribution +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54995612 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346068 # Transaction distribution +system.membus.trans_dist::ReadResp 16346071 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59151 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4708 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4711 # Transaction distribution -system.membus.trans_dist::ReadExReq 131399 # Transaction distribution -system.membus.trans_dist::ReadExResp 131399 # Transaction distribution +system.membus.trans_dist::Writeback 59135 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4685 # Transaction distribution +system.membus.trans_dist::ReadExReq 131422 # Transaction distribution +system.membus.trans_dist::ReadExResp 131422 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution @@ -617,261 +609,255 @@ system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382960 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885919 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885807 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272561 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550305 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34550193 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390337 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696716 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19094701 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16694284 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19092269 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140205229 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140205229 # Total data (bytes) +system.membus.tot_pkt_size::total 140202797 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140202797 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487741000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487346000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3601000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3636500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17567405000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17566569000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4737923280 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4736419263 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34188515482 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34186627978 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 64379 # number of replacements -system.l2c.tags.tagsinuse 51427.622498 # Cycle average of tags in use -system.l2c.tags.total_refs 1904241 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129768 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.674195 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2512188924000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36951.825179 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.926736 # Average occupied blocks per requestor +system.l2c.tags.replacements 64357 # number of replacements +system.l2c.tags.tagsinuse 51453.251473 # Cycle average of tags in use +system.l2c.tags.total_refs 1905423 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129744 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.686020 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2512210729500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36987.198092 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.713113 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4986.850446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3336.949611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.947160 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3226.583152 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2894.539843 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563840 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000289 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4872.243485 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3313.752357 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.584037 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3345.363294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2901.396724 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564380 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.076093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050918 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000182 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049234 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044167 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784723 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32603 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 505956 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 182118 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 205502 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435201 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608382 # number of Writeback hits -system.l2c.Writeback_hits::total 608382 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 22 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58173 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54780 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112953 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32603 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 505956 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 240291 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30730 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260282 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548154 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32603 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7139 # number of overall hits -system.l2c.overall_hits::cpu0.inst 505956 # number of overall hits -system.l2c.overall_hits::cpu0.data 240291 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30730 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6661 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464492 # number of overall hits -system.l2c.overall_hits::cpu1.data 260282 # number of overall hits -system.l2c.overall_hits::total 1548154 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.074345 # Average percentage of cache occupancy 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ReadReq hits +system.l2c.ReadReq_hits::total 1436338 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608494 # number of Writeback hits +system.l2c.Writeback_hits::total 608494 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58298 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54682 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112980 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32950 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7107 # number of demand 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hits +system.l2c.overall_hits::cpu1.inst 464544 # number of overall hits +system.l2c.overall_hits::cpu1.data 260649 # number of overall hits +system.l2c.overall_hits::total 1549318 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7825 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6187 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4565 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4551 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23171 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1285 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1631 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2916 # number of UpgradeReq misses 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# number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1636 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 67869 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 65320 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133189 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7825 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74661 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4565 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 69268 # number of demand (read+write) misses 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0.000280 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.236922 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.210114 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091688 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93549406553 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90761460250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184316879802 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032489 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021425 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015791 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986154 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990315 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988482 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.537930 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.544324 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541047 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.235487 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.211285 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091600 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.235487 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.211285 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091600 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61701.627339 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65461.720946 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61973.540577 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62516.088096 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64764.744789 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62038.855339 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.065604 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.714678 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61956.189415 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63673.743808 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62790.742558 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.666870 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.055860 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61882.451473 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63776.931537 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62811.563019 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1066,43 +1040,43 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58456334 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676393 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676395 # Transaction distribution +system.toL2Bus.throughput 58478558 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677542 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677544 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608382 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2974 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246144 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246144 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608494 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2952 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2958 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246169 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246169 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967115 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798220 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37803 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149157 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952295 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62908992 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85598765 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148816461 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148816461 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 207744 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4964319701 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798582 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38031 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149645 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7954666 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62951744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85614957 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254244 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148876637 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148876637 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 205392 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4965399712 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4431802148 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4434611165 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4486267320 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4486677044 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24046904 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24152407 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86228845 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86557036 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48444532 # Throughput (bytes/s) +system.iobus.throughput 48444152 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322136 # Transaction distribution system.iobus.trans_dist::ReadResp 16322136 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution @@ -1212,40 +1186,40 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41492591518 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41494630022 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7178846 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5689563 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 376334 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4735029 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3823898 # Number of BTB hits +system.cpu0.branchPred.lookups 7183590 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5694303 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 377290 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4721847 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3824688 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 80.757647 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 708733 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 80.999829 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 708757 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39349 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25686724 # DTB read hits -system.cpu0.dtb.read_misses 37672 # DTB read misses -system.cpu0.dtb.write_hits 5882199 # DTB write hits -system.cpu0.dtb.write_misses 9157 # DTB write misses +system.cpu0.dtb.read_hits 25676392 # DTB read hits +system.cpu0.dtb.read_misses 38073 # DTB read misses +system.cpu0.dtb.write_hits 5871403 # DTB write hits +system.cpu0.dtb.write_misses 9193 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5402 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1359 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 227 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5420 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1344 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25724396 # DTB read accesses -system.cpu0.dtb.write_accesses 5891356 # DTB write accesses +system.cpu0.dtb.perms_faults 585 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25714465 # DTB read accesses +system.cpu0.dtb.write_accesses 5880596 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31568923 # DTB hits -system.cpu0.dtb.misses 46829 # DTB misses -system.cpu0.dtb.accesses 31615752 # DTB accesses -system.cpu0.itb.inst_hits 5794960 # ITB inst hits -system.cpu0.itb.inst_misses 6979 # ITB inst misses +system.cpu0.dtb.hits 31547795 # DTB hits +system.cpu0.dtb.misses 47266 # DTB misses +system.cpu0.dtb.accesses 31595061 # DTB accesses +system.cpu0.itb.inst_hits 5793609 # ITB inst hits +system.cpu0.itb.inst_misses 6965 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1254,114 +1228,114 @@ system.cpu0.itb.flush_tlb 257 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2537 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2542 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1475 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5801939 # ITB inst accesses -system.cpu0.itb.hits 5794960 # DTB hits -system.cpu0.itb.misses 6979 # DTB misses -system.cpu0.itb.accesses 5801939 # DTB accesses -system.cpu0.numCycles 241329954 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5800574 # ITB inst accesses +system.cpu0.itb.hits 5793609 # DTB hits +system.cpu0.itb.misses 6965 # DTB misses +system.cpu0.itb.accesses 5800574 # DTB accesses +system.cpu0.numCycles 241355643 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15402359 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 44612176 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7178846 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4532631 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10046821 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2409329 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 81802 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48777724 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1779 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1966 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 42894 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1416575 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 470 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5793020 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 368373 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3163 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77432013 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.722773 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.070911 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15408312 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 44581736 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7183590 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4533445 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10042154 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2412494 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 81949 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 48815807 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1726 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1993 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 42608 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1411972 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5791670 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 368874 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3149 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77468964 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.722040 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.069743 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67393349 87.04% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 663167 0.86% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 850708 1.10% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1161944 1.50% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1070979 1.38% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 538004 0.69% 92.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1258402 1.63% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 372673 0.48% 94.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4122787 5.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67434698 87.05% 87.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 662922 0.86% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 849826 1.10% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1158615 1.50% 90.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1071303 1.38% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 540404 0.70% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1264103 1.63% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 371341 0.48% 94.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4115752 5.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77432013 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.029747 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.184860 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16324291 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49901037 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9152885 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 482910 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1568783 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 985989 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 93507 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53239353 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 312067 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1568783 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17193647 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20516369 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 26371209 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8691714 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3088262 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50703360 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7236 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 484563 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2089605 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 237 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 52223867 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 231534090 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 214067803 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5431 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 38086867 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14136999 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 416413 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 366902 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6391113 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9801074 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6698586 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1023553 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1394670 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 47085778 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 981191 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61028996 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87181 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9766291 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24255892 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256976 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77432013 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.788162 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.509612 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77468964 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.029764 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.184714 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16332862 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49931887 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9147459 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 483482 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1571127 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 985970 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 93586 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53203424 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 313882 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1571127 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17204608 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20551297 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 26349401 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8685161 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3105311 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50667470 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7242 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 502803 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2087731 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 194 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 52194379 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 231353972 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 213903823 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5361 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 38031727 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14162651 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 415813 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 366209 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6409920 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9794680 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6688167 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1031152 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1299354 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47050561 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 979447 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 60972564 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 88288 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9787230 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24359943 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256705 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77468964 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.787058 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.508592 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55649099 71.87% 71.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6737778 8.70% 80.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3435441 4.44% 85.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2925983 3.78% 88.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6185685 7.99% 96.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1437832 1.86% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 773159 1.00% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 224755 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 62281 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55694568 71.89% 71.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6744950 8.71% 80.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3431902 4.43% 85.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2928703 3.78% 88.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6175861 7.97% 96.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1433177 1.85% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 773017 1.00% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 224018 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 62768 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77432013 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77468964 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29912 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 30016 0.67% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available @@ -1390,504 +1364,504 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4221653 94.70% 95.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 206360 4.63% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4221900 94.67% 95.34% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207684 4.66% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 165947 0.27% 0.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 28282024 46.34% 46.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46844 0.08% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1271 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26348641 43.17% 89.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6184237 10.13% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 165809 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 28246973 46.33% 46.60% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46806 0.08% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1267 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26338371 43.20% 89.88% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6173305 10.12% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61028996 # Type of FU issued -system.cpu0.iq.rate 0.252886 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4457926 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.073046 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 204069737 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57841875 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 42095336 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12029 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6474 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5396 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 65314591 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6384 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 305188 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 60972564 # Type of FU issued +system.cpu0.iq.rate 0.252625 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4459601 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.073141 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 203996977 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57825737 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 42036875 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12074 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6420 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 65259915 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6441 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 303470 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2103037 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3902 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15671 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 837358 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2107176 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15490 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 838182 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17232684 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348213 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17232343 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348683 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1568783 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15829049 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 237688 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 48167223 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105126 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9801074 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6698586 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 691561 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 54422 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4242 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15671 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 182031 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 143561 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 325592 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 59970791 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26024613 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1058205 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1571127 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15861030 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 237452 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 48130825 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105592 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9794680 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6688167 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 690516 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54721 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15490 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 181987 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144371 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 326358 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 59914186 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26012956 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1058378 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 100254 # number of nop insts executed -system.cpu0.iew.exec_refs 32151728 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5674244 # Number of branches executed -system.cpu0.iew.exec_stores 6127115 # Number of stores executed -system.cpu0.iew.exec_rate 0.248501 # Inst execution rate -system.cpu0.iew.wb_sent 59482820 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 42100732 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22797313 # num instructions producing a value -system.cpu0.iew.wb_consumers 41683102 # num instructions consuming a value +system.cpu0.iew.exec_nop 100817 # number of nop insts executed +system.cpu0.iew.exec_refs 32128938 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5674429 # Number of branches executed +system.cpu0.iew.exec_stores 6115982 # Number of stores executed +system.cpu0.iew.exec_rate 0.248240 # Inst execution rate +system.cpu0.iew.wb_sent 59424173 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 42042235 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22754717 # num instructions producing a value +system.cpu0.iew.wb_consumers 41618983 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.174453 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.546920 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.174192 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.546739 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9635326 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 724215 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 284304 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75863230 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.501725 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.477269 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9657152 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 722742 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 285161 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75897837 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.500741 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.473402 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 62300247 82.12% 82.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6632163 8.74% 90.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1905948 2.51% 93.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1063803 1.40% 94.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 963459 1.27% 96.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 539688 0.71% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 720050 0.95% 97.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 348558 0.46% 98.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1389314 1.83% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 62326931 82.12% 82.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6623929 8.73% 90.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1927651 2.54% 93.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1062809 1.40% 94.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 977806 1.29% 96.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 537572 0.71% 96.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 721191 0.95% 97.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 348340 0.46% 98.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1371608 1.81% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75863230 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29321704 # Number of instructions committed -system.cpu0.commit.committedOps 38062462 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75897837 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29270698 # Number of instructions committed +system.cpu0.commit.committedOps 38005132 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13559265 # Number of memory references committed -system.cpu0.commit.loads 7698037 # Number of loads committed -system.cpu0.commit.membars 204059 # Number of memory barriers committed -system.cpu0.commit.branches 4889328 # Number of branches committed -system.cpu0.commit.fp_insts 5354 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 33742241 # Number of committed integer instructions. -system.cpu0.commit.function_calls 497179 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1389314 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13537489 # Number of memory references committed +system.cpu0.commit.loads 7687504 # Number of loads committed +system.cpu0.commit.membars 203418 # Number of memory barriers committed +system.cpu0.commit.branches 4891612 # Number of branches committed +system.cpu0.commit.fp_insts 5306 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 33685063 # Number of committed integer instructions. +system.cpu0.commit.function_calls 497791 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1371608 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 121250209 # The number of ROB reads -system.cpu0.rob.rob_writes 97007351 # The number of ROB writes -system.cpu0.timesIdled 906901 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 163897941 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2251401803 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29254206 # Number of Instructions Simulated -system.cpu0.committedOps 37994964 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29254206 # Number of Instructions Simulated -system.cpu0.cpi 8.249410 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.249410 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.121221 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.121221 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 271506841 # number of integer regfile reads -system.cpu0.int_regfile_writes 42814380 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22646 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19918 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15055897 # number of misc regfile reads -system.cpu0.misc_regfile_writes 404161 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983492 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.574238 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10516196 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984004 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.687148 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6986136250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 318.901478 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 192.672760 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.622854 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.376314 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999168 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5235281 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5280915 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10516196 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5235281 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5280915 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10516196 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5235281 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5280915 # number of overall hits -system.cpu0.icache.overall_hits::total 10516196 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 557620 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 507749 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065369 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 557620 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 507749 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065369 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 557620 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 507749 # number of overall misses -system.cpu0.icache.overall_misses::total 1065369 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7715888650 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6834076460 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14549965110 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7715888650 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6834076460 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14549965110 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7715888650 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6834076460 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14549965110 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5792901 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5788664 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11581565 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5792901 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5788664 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11581565 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5792901 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5788664 # number of overall (read+write) accesses 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of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5567069659 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11826064063 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6258994404 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5567069659 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11826064063 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6258994404 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5567069659 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11826064063 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43117 # number of ReadReq MSHR hits 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-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084967 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.084967 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.084967 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.795980 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for ReadReq accesses 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miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.918977 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643990 # number of replacements +system.cpu0.dcache.tags.replacements 644131 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.993324 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21534082 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644502 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.411971 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 21534637 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644643 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.405524 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 43026250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.795317 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.198007 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499600 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500387 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.706394 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.286930 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497473 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502514 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6836118 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6942659 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13778777 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3601868 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3659456 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261324 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114429 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 128738 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243167 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116989 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 130670 # number of StoreCondReq hits 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-system.cpu0.dcache.WriteReq_misses::total 2962280 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7436 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6109 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13545 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 12 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1847401 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1863754 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3711155 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1847401 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1863754 # number of overall misses -system.cpu0.dcache.overall_misses::total 3711155 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5258794781 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6175311803 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11434106584 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76116558084 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 73496602051 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 149613160135 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106253499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82007996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 188261495 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 181002 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 271503 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 81375352865 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 79671913854 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 161047266719 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 81375352865 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 79671913854 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 161047266719 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7163263 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7364389 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14527652 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5122124 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5101480 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223604 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121865 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 134847 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256712 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116995 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 130682 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247677 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12285387 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12465869 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24751256 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12285387 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12465869 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24751256 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045670 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057266 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051548 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.296802 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.282668 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289749 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045303 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052763 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000051 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000092 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000073 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150374 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.149509 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149938 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.150374 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.149509 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149938 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16074.813251 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14642.808913 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15268.378012 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50068.250403 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50967.669089 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50506.083198 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14289.066568 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13424.127680 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13898.966039 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15083.500000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43395.456864 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43395.456864 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 38322 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25151 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3482 # number of cycles access was blocked +system.cpu0.dcache.ReadReq_hits::cpu0.data 6830201 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6949651 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13779852 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3598843 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3661860 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7260703 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114028 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129247 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243275 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116593 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131076 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247669 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10429044 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10611511 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21040555 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10429044 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10611511 # number of overall hits +system.cpu0.dcache.overall_hits::total 21040555 # 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of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1837607 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1874866 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3712473 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1837607 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1874866 # number of overall misses +system.cpu0.dcache.overall_misses::total 3712473 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5222562191 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6193158591 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11415720782 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 75296679857 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 74371858974 # number of WriteReq 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of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 80519242048 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 80565017565 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 161084259613 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7155035 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 7374446 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14529481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5111616 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5111931 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10223547 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121453 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135379 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256832 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116595 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 131080 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247675 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12266651 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12486377 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24753028 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12266651 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12486377 # 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# average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15228.494071 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49773.944840 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 51288.425859 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50515.160039 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14290.201751 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13398.849804 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13887.032161 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency 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0.026129 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13978.974235 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13269.059484 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.899713 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46428.448104 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47251.379913 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46828.660302 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12580.254879 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11592.833121 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12136.336094 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106094158515 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103008489165 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209102647680 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025341 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027810 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026594 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024927 # mshr miss rate for WriteReq accesses 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47507.207423 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46845.248826 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12583.867511 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11609.743295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12145.907145 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1902,38 +1876,38 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7299586 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5849815 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 347289 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4589899 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3862662 # Number of BTB hits +system.cpu1.branchPred.lookups 7296861 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5846678 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 347662 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4742078 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3857406 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.155708 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 691728 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34987 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 81.344212 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 691724 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35172 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25535708 # DTB read hits -system.cpu1.dtb.read_misses 37819 # DTB read misses -system.cpu1.dtb.write_hits 5832824 # DTB write hits -system.cpu1.dtb.write_misses 9748 # DTB write misses +system.cpu1.dtb.read_hits 25545961 # DTB read hits +system.cpu1.dtb.read_misses 37652 # DTB read misses +system.cpu1.dtb.write_hits 5843070 # DTB write hits +system.cpu1.dtb.write_misses 9833 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2100 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5607 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2149 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25573527 # DTB read accesses -system.cpu1.dtb.write_accesses 5842572 # DTB write accesses +system.cpu1.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25583613 # DTB read accesses +system.cpu1.dtb.write_accesses 5852903 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31368532 # DTB hits -system.cpu1.dtb.misses 47567 # DTB misses -system.cpu1.dtb.accesses 31416099 # DTB accesses -system.cpu1.itb.inst_hits 5790816 # ITB inst hits -system.cpu1.itb.inst_misses 7158 # ITB inst misses +system.cpu1.dtb.hits 31389031 # DTB hits +system.cpu1.dtb.misses 47485 # DTB misses +system.cpu1.dtb.accesses 31436516 # DTB accesses +system.cpu1.itb.inst_hits 5792513 # ITB inst hits +system.cpu1.itb.inst_misses 7242 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1942,284 +1916,284 @@ system.cpu1.itb.flush_tlb 255 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2684 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2667 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1580 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1547 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5797974 # ITB inst accesses -system.cpu1.itb.hits 5790816 # DTB hits -system.cpu1.itb.misses 7158 # DTB misses -system.cpu1.itb.accesses 5797974 # DTB accesses -system.cpu1.numCycles 235384601 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5799755 # ITB inst accesses +system.cpu1.itb.hits 5792513 # DTB hits +system.cpu1.itb.misses 7242 # DTB misses +system.cpu1.itb.accesses 5799755 # DTB accesses +system.cpu1.numCycles 235437063 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14589178 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46084175 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7299586 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4554390 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10179964 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2322435 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82610 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 48394674 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1151 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1760 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 51069 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1300436 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5788667 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 351586 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2955 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76205210 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.749083 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.107109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14594322 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46143705 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7296861 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4549130 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10187153 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2325105 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 84075 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48390355 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1006 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1773 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 50802 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1299927 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5790405 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 352119 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3045 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76215873 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.749895 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.108619 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66032287 86.65% 86.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 647062 0.85% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 866139 1.14% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1142625 1.50% 90.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1039142 1.36% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 573208 0.75% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1303078 1.71% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 377648 0.50% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4224021 5.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66035998 86.64% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 646269 0.85% 87.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 866115 1.14% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1144603 1.50% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1038380 1.36% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570616 0.75% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1298592 1.70% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 378941 0.50% 94.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4236359 5.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76205210 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031011 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.195782 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15588837 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49317422 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9252055 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 521656 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1523167 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 986244 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 83403 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54452083 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 278013 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1523167 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16469267 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19674049 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 26510190 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8818021 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3208448 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51956781 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13421 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 604219 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2079670 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 451 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 54191440 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237039699 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 219510796 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 4998 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 40313487 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13877953 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 415796 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 370913 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6599828 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9995387 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6641278 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 924791 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1180275 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 48354458 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1004264 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62036555 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93414 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9463744 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23885542 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 245582 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76205210 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.814072 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.522064 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76215873 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030993 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.195992 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15595502 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49311936 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9258524 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 522439 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1525385 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 986467 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 83299 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54522655 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 277301 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1525385 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16476975 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19655955 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 26515105 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8823591 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3216801 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 52024243 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13429 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 607553 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2083322 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 488 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 54254654 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237368382 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 219812592 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5012 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 40368418 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13886236 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 416636 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 371803 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6618695 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10010762 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6654363 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 928897 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1221940 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 48420965 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1005597 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62096685 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94311 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9477685 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23931706 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 245448 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76215873 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.814747 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.522121 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53886192 70.71% 70.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6968313 9.14% 79.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3603419 4.73% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3067011 4.02% 88.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6180907 8.11% 96.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1416351 1.86% 98.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 790440 1.04% 99.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 228268 0.30% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 64309 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53862159 70.67% 70.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6987914 9.17% 79.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3609115 4.74% 84.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3073312 4.03% 88.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6185840 8.12% 96.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1415029 1.86% 98.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 789705 1.04% 99.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 228522 0.30% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 64277 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76205210 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76215873 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29954 0.68% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 6 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4154847 94.70% 95.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 202692 4.62% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 30122 0.69% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4155854 94.74% 95.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 200598 4.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 197719 0.32% 0.32% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 29431617 47.44% 47.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46723 0.08% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 843 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26206761 42.24% 90.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6152865 9.92% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 197857 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 29468242 47.46% 47.77% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46687 0.08% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 846 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26218549 42.22% 90.07% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6164475 9.93% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62036555 # Type of FU issued -system.cpu1.iq.rate 0.263554 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4387499 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.070724 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 204795562 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58831312 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 43493604 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11047 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6062 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4926 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 66220464 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5871 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 319800 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62096685 # Type of FU issued +system.cpu1.iq.rate 0.263751 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4386578 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.070641 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 204926211 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58913069 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 43552448 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11222 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6050 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4957 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 66279422 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5984 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 320383 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2036379 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2915 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15518 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 769053 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2041284 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2958 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15466 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 770955 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16877667 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 333288 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16877302 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 331906 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1523167 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14985510 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 225691 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 49480647 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96107 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9995387 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6641278 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 719443 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50947 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6143 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15518 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 171517 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 135143 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 306660 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 61000330 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25886068 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1036225 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1525385 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14957873 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 224833 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 49549209 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 95185 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 10010762 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6654363 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 720304 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50705 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4281 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15466 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 171203 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 135670 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 306873 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 61058870 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25897367 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1037815 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 121925 # number of nop insts executed -system.cpu1.iew.exec_refs 31986182 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5823905 # Number of branches executed -system.cpu1.iew.exec_stores 6100114 # Number of stores executed -system.cpu1.iew.exec_rate 0.259152 # Inst execution rate -system.cpu1.iew.wb_sent 60530443 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 43498530 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24164344 # num instructions producing a value -system.cpu1.iew.wb_consumers 44485345 # num instructions consuming a value +system.cpu1.iew.exec_nop 122647 # number of nop insts executed +system.cpu1.iew.exec_refs 32008147 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5821795 # Number of branches executed +system.cpu1.iew.exec_stores 6110780 # Number of stores executed +system.cpu1.iew.exec_rate 0.259343 # Inst execution rate +system.cpu1.iew.wb_sent 60589807 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 43557405 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24211075 # num instructions producing a value +system.cpu1.iew.wb_consumers 44594441 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.184798 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.543198 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.185007 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.542917 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9351616 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 758682 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 265186 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74682043 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.531552 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.520144 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9363446 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 760149 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 265641 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74690488 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.532256 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.520816 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60574973 81.11% 81.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6925092 9.27% 90.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1956264 2.62% 93.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1088628 1.46% 94.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1022152 1.37% 95.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 532797 0.71% 96.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 718663 0.96% 97.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 378466 0.51% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1485008 1.99% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60561931 81.08% 81.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6932594 9.28% 90.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1961063 2.63% 92.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1092193 1.46% 94.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1024970 1.37% 95.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 536622 0.72% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 713910 0.96% 97.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 380912 0.51% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1486293 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74682043 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31143561 # Number of instructions committed -system.cpu1.commit.committedOps 39697401 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74690488 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31194382 # Number of instructions committed +system.cpu1.commit.committedOps 39754477 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13831233 # Number of memory references committed -system.cpu1.commit.loads 7959008 # Number of loads committed -system.cpu1.commit.membars 199700 # Number of memory barriers committed -system.cpu1.commit.branches 5073252 # Number of branches committed -system.cpu1.commit.fp_insts 4858 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 35121772 # Number of committed integer instructions. -system.cpu1.commit.function_calls 494294 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1485008 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13852886 # Number of memory references committed +system.cpu1.commit.loads 7969478 # Number of loads committed +system.cpu1.commit.membars 200339 # Number of memory barriers committed +system.cpu1.commit.branches 5070949 # Number of branches committed +system.cpu1.commit.fp_insts 4906 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 35178713 # Number of committed integer instructions. +system.cpu1.commit.function_calls 493679 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1486293 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 121317994 # The number of ROB reads -system.cpu1.rob.rob_writes 99664484 # The number of ROB writes -system.cpu1.timesIdled 865516 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159179391 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2318646728 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31060678 # Number of Instructions Simulated -system.cpu1.committedOps 39614518 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 31060678 # Number of Instructions Simulated -system.cpu1.cpi 7.578218 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.578218 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.131957 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.131957 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 276434717 # number of integer regfile reads -system.cpu1.int_regfile_writes 44854574 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22375 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19728 # number of floating regfile writes -system.cpu1.misc_regfile_reads 15285924 # number of misc regfile reads -system.cpu1.misc_regfile_writes 428613 # number of misc regfile writes +system.cpu1.rob.rob_reads 121392021 # The number of ROB reads +system.cpu1.rob.rob_writes 99804752 # The number of ROB writes +system.cpu1.timesIdled 864703 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159221190 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2318646914 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31111502 # Number of Instructions Simulated +system.cpu1.committedOps 39671597 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 31111502 # Number of Instructions Simulated +system.cpu1.cpi 7.567525 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.567525 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.132144 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.132144 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 276724007 # number of integer regfile reads +system.cpu1.int_regfile_writes 44911737 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22398 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19708 # number of floating regfile writes +system.cpu1.misc_regfile_reads 15283998 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429459 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2234,10 +2208,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1518441783518 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1518441783518 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1518454987022 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1518454987022 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 78712e3a3..927b487de 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,22 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts @@ -112,6 +121,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -134,18 +144,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -156,6 +169,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -178,14 +192,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -204,18 +221,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -227,6 +247,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -248,17 +269,20 @@ workload= [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -277,30 +301,36 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -313,6 +343,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -335,6 +366,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -344,6 +376,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -366,6 +399,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -373,6 +407,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -384,6 +419,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -410,6 +446,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -421,19 +458,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -443,6 +484,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -452,6 +494,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -480,6 +523,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -489,8 +533,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -502,6 +578,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -517,6 +594,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -531,6 +610,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -540,6 +620,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -561,8 +642,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -571,6 +654,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -581,6 +665,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -591,6 +676,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -601,6 +687,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -615,6 +702,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -628,6 +716,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -645,6 +734,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -657,6 +747,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -668,6 +759,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -678,6 +770,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -690,6 +783,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -703,6 +797,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -713,6 +808,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -723,6 +819,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -733,6 +830,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -745,6 +843,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -759,6 +858,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -771,6 +871,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -785,6 +886,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -795,6 +897,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -805,6 +908,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -815,6 +919,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -823,6 +928,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -831,6 +937,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -840,11 +947,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 87a0dc109..98143dc12 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,145 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.631415 # Number of seconds simulated -sim_ticks 2631415171500 # Number of ticks simulated -final_tick 2631415171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.629717 # Number of seconds simulated +sim_ticks 2629717216500 # Number of ticks simulated +final_tick 2629717216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 471038 # Simulator instruction rate (inst/s) -host_op_rate 599389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20585916294 # Simulator tick rate (ticks/s) -host_mem_usage 424736 # Number of bytes of host memory used -host_seconds 127.83 # Real time elapsed on the host -sim_insts 60210883 # Number of instructions simulated -sim_ops 76617506 # Number of ops (including micro ops) simulated +host_inst_rate 340896 # Simulator instruction rate (inst/s) +host_op_rate 433786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14888327014 # Simulator tick rate (ticks/s) +host_mem_usage 445372 # Number of bytes of host memory used +host_seconds 176.63 # Real time elapsed on the host +sim_insts 60212334 # Number of instructions simulated +sim_ops 76619433 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 278752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4724944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 298016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4661584 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4336188 # Number of bytes read from this memory -system.physmem.bytes_read::total 134022064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 278752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704484 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1530592 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1485560 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706648 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 406404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4399060 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 298016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704420 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3689984 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1527272 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1489008 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706264 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73861 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10859 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 72871 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 67782 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690904 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 382648 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 371390 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811702 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47220316 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6366 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68770 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690901 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57656 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 381818 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 372252 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811726 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47250805 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 105932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1795590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 113326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1772656 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 161788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1647854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50931554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 105932 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 161788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1402476 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 581661 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 564548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2548685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1402476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47220316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 154543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1672826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50964230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 113326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 154543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267869 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1403187 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 580774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 566224 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550184 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1403187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47250805 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 105932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2377252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 113326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2353430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 161788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2212402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53480239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690904 # Number of read requests accepted -system.physmem.writeReqs 811702 # Number of write requests accepted -system.physmem.readBursts 15690904 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811702 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004216000 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 154543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2239050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53514414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690901 # Number of read requests accepted +system.physmem.writeReqs 811726 # Number of write requests accepted +system.physmem.readBursts 15690901 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811726 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004215808 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6838848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134022064 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6706648 # Total written bytes from the system interface side +system.physmem.bytesWritten 6837952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021512 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706264 # Total written bytes from the system interface side system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704845 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 704883 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4518 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980392 # Per bank write bursts system.physmem.perBankRdBursts::1 980205 # Per bank write bursts system.physmem.perBankRdBursts::2 980222 # Per bank write bursts -system.physmem.perBankRdBursts::3 980428 # Per bank write bursts +system.physmem.perBankRdBursts::3 980431 # Per bank write bursts system.physmem.perBankRdBursts::4 986950 # Per bank write bursts -system.physmem.perBankRdBursts::5 980709 # Per bank write bursts -system.physmem.perBankRdBursts::6 980611 # Per bank write bursts -system.physmem.perBankRdBursts::7 980420 # Per bank write bursts +system.physmem.perBankRdBursts::5 980708 # Per bank write bursts +system.physmem.perBankRdBursts::6 980610 # Per bank write bursts +system.physmem.perBankRdBursts::7 980424 # Per bank write bursts system.physmem.perBankRdBursts::8 980615 # Per bank write bursts system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts -system.physmem.perBankRdBursts::11 979555 # Per bank write bursts -system.physmem.perBankRdBursts::12 980153 # Per bank write bursts -system.physmem.perBankRdBursts::13 980095 # Per bank write bursts -system.physmem.perBankRdBursts::14 980165 # Per bank write bursts +system.physmem.perBankRdBursts::11 979558 # Per bank write bursts +system.physmem.perBankRdBursts::12 980154 # Per bank write bursts +system.physmem.perBankRdBursts::13 980093 # Per bank write bursts +system.physmem.perBankRdBursts::14 980155 # Per bank write bursts system.physmem.perBankRdBursts::15 980109 # Per bank write bursts -system.physmem.perBankWrBursts::0 6734 # Per bank write bursts -system.physmem.perBankWrBursts::1 6600 # Per bank write bursts -system.physmem.perBankWrBursts::2 6608 # Per bank write bursts -system.physmem.perBankWrBursts::3 6671 # Per bank write bursts -system.physmem.perBankWrBursts::4 6747 # Per bank write bursts -system.physmem.perBankWrBursts::5 7057 # Per bank write bursts -system.physmem.perBankWrBursts::6 7034 # Per bank write bursts -system.physmem.perBankWrBursts::7 6884 # Per bank write bursts -system.physmem.perBankWrBursts::8 7000 # Per bank write bursts -system.physmem.perBankWrBursts::9 6825 # Per bank write bursts +system.physmem.perBankWrBursts::0 6731 # Per bank write bursts +system.physmem.perBankWrBursts::1 6599 # Per bank write bursts +system.physmem.perBankWrBursts::2 6610 # Per bank write bursts +system.physmem.perBankWrBursts::3 6672 # Per bank write bursts +system.physmem.perBankWrBursts::4 6746 # Per bank write bursts +system.physmem.perBankWrBursts::5 7052 # Per bank write bursts +system.physmem.perBankWrBursts::6 7033 # Per bank write bursts +system.physmem.perBankWrBursts::7 6881 # Per bank write bursts +system.physmem.perBankWrBursts::8 7002 # Per bank write bursts +system.physmem.perBankWrBursts::9 6827 # Per bank write bursts system.physmem.perBankWrBursts::10 6323 # Per bank write bursts -system.physmem.perBankWrBursts::11 6129 # Per bank write bursts +system.physmem.perBankWrBursts::11 6122 # Per bank write bursts system.physmem.perBankWrBursts::12 6612 # Per bank write bursts -system.physmem.perBankWrBursts::13 6395 # Per bank write bursts -system.physmem.perBankWrBursts::14 6622 # Per bank write bursts +system.physmem.perBankWrBursts::13 6399 # Per bank write bursts +system.physmem.perBankWrBursts::14 6618 # Per bank write bursts system.physmem.perBankWrBursts::15 6616 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2631410752000 # Total gap between requests +system.physmem.totGap 2629712785000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6700 # Read request sizes (log2) +system.physmem.readPktSize::2 6706 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152172 # Read request sizes (log2) +system.physmem.readPktSize::6 152163 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754038 # Write request sizes (log2) +system.physmem.writePktSize::2 754070 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57664 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1280991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1124435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1124568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3790382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2700913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2699740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2717442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 51875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 37 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57656 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1290849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1134741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1135188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3791353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2690884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2690157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2706986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 51561 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 56279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -155,28 +167,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5010 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 4995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4689 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -187,301 +199,302 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11200.204894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1031.239605 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16762.903946 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23441 25.97% 25.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14726 16.31% 42.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2829 3.13% 45.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2153 2.39% 47.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1359 1.51% 49.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1176 1.30% 50.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 955 1.06% 51.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1145 1.27% 52.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 612 0.68% 53.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 559 0.62% 54.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 621 0.69% 54.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 534 0.59% 55.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 322 0.36% 55.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 268 0.30% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 218 0.24% 56.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 586 0.65% 57.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 164 0.18% 57.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 127 0.14% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 130 0.14% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 257 0.28% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 89 0.10% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 142 0.16% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 48 0.05% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 45 0.05% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 41 0.05% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 166 0.18% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 19 0.02% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 18 0.02% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 150 0.17% 61.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 341 0.38% 61.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 19 0.02% 61.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 17 0.02% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 76 0.08% 61.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 15 0.02% 61.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 8 0.01% 61.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 16 0.02% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 76 0.08% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 11 0.01% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 6 0.01% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 22 0.02% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 3 0.00% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 6 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 382 0.42% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 8 0.01% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 6 0.01% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 146 0.16% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 2 0.00% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 137 0.15% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 197 0.22% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 7 0.01% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 7 0.01% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 32 0.04% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 137 0.15% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 6 0.01% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 2 0.00% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 6 0.01% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 337 0.37% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 1 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 1 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 2 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 130 0.14% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 2 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 1 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 71 0.08% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 129 0.14% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 3 0.00% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 75 0.08% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 261 0.29% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 1 0.00% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 1 0.00% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 62 0.07% 64.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 15 0.02% 64.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 204 0.23% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 122 0.14% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 133 0.15% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 389 0.43% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 64 0.07% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 120 0.13% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 252 0.28% 65.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 133 0.15% 65.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 13 0.01% 66.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 68 0.08% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 520 0.58% 66.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 68 0.08% 66.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 11 0.01% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 136 0.15% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 250 0.28% 67.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 121 0.13% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 68 0.08% 67.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 65 0.07% 67.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 388 0.43% 67.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 132 0.15% 68.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 121 0.13% 68.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10823 2 0.00% 68.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 55 0.06% 68.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 259 0.29% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 71 0.08% 68.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 69 0.08% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 128 0.14% 68.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 328 0.36% 69.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 133 0.15% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 193 0.21% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 136 0.15% 69.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 377 0.42% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 11 0.01% 70.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 64 0.07% 70.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 322 0.36% 70.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 132 0.15% 70.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 68 0.08% 70.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 129 0.14% 70.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 391 0.43% 71.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 67 0.07% 71.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 129 0.14% 71.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 641 0.71% 72.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 136 0.15% 72.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 66 0.07% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 2 0.00% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 391 0.43% 73.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 128 0.14% 73.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 67 0.07% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 131 0.15% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 320 0.35% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 67 0.07% 73.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 67 0.07% 73.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 13 0.01% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 1 0.00% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 376 0.42% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 137 0.15% 74.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 192 0.21% 74.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 131 0.15% 74.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 326 0.36% 75.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 124 0.14% 75.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 68 0.08% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21056-21063 1 0.00% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 71 0.08% 75.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 259 0.29% 75.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 56 0.06% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 120 0.13% 75.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 134 0.15% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 388 0.43% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 64 0.07% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 67 0.07% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 121 0.13% 76.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 253 0.28% 77.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 133 0.15% 77.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 10 0.01% 77.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 70 0.08% 77.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 519 0.57% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 69 0.08% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 10 0.01% 77.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 133 0.15% 78.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 251 0.28% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 120 0.13% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 70 0.08% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 64 0.07% 78.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 387 0.43% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 134 0.15% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 119 0.13% 79.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 56 0.06% 79.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 259 0.29% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 71 0.08% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 68 0.08% 79.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 125 0.14% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 325 0.36% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 133 0.15% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 192 0.21% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 377 0.42% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 11 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 65 0.07% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 69 0.08% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 321 0.36% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 130 0.14% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 67 0.07% 82.07% # Bytes accessed per row activation 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Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23393 25.86% 25.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14737 16.29% 42.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2929 3.24% 45.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2185 2.42% 47.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1403 1.55% 49.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1153 1.27% 50.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 940 1.04% 51.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1175 1.30% 52.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 610 0.67% 53.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 557 0.62% 54.26% # Bytes accessed per row activation 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0.01% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 271 0.30% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 14 0.02% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 4 0.00% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 136 0.15% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 11 0.01% 63.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 341 0.38% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 2 0.00% 64.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 14 0.02% 64.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 4 0.00% 64.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 205 0.23% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 168 0.19% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 3 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 126 0.14% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 267 0.30% 65.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 256 0.28% 65.48% # Bytes accessed per row activation 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261 0.29% 66.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 193 0.21% 66.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 9 0.01% 66.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 455 0.50% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 64 0.07% 67.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 5 0.01% 67.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 257 0.28% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10183 1 0.00% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 265 0.29% 67.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 124 0.14% 68.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 4 0.00% 68.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 195 0.22% 68.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11207 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 336 0.37% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 123 0.14% 68.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 266 0.29% 69.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 267 0.30% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 121 0.13% 69.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 75 0.08% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 4 0.00% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 387 0.43% 70.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 197 0.22% 70.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 78 0.09% 70.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 1 0.00% 70.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 129 0.14% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 206 0.23% 70.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 65 0.07% 70.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 65 0.07% 70.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 71 0.08% 70.96% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::17152-17159 68 0.08% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 460 0.51% 73.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17600-17607 1 0.00% 73.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 71 0.08% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 66 0.07% 73.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 64 0.07% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 208 0.23% 73.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 128 0.14% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 77 0.09% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 196 0.22% 74.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 1 0.00% 74.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 386 0.43% 74.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 3 0.00% 74.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 72 0.08% 74.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 120 0.13% 74.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 270 0.30% 74.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 265 0.29% 75.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 123 0.14% 75.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 334 0.37% 75.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 195 0.22% 75.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21824-21831 1 0.00% 75.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 3 0.00% 76.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 127 0.14% 76.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 264 0.29% 76.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 255 0.28% 76.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 5 0.01% 76.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 65 0.07% 76.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 452 0.50% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 9 0.01% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 192 0.21% 77.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 3 0.00% 77.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 259 0.29% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 193 0.21% 78.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 7 0.01% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 454 0.50% 78.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 66 0.07% 78.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 5 0.01% 78.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 256 0.28% 78.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 266 0.29% 79.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 124 0.14% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 2 0.00% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 195 0.22% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 332 0.37% 79.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 123 0.14% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 266 0.29% 80.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 267 0.30% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 122 0.13% 80.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 74 0.08% 80.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 4 0.00% 80.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 387 0.43% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 194 0.21% 81.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 77 0.09% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 1 0.00% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 128 0.14% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 205 0.23% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 64 0.07% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 66 0.07% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 71 0.08% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 457 0.51% 82.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 65 0.07% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 130 0.14% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 128 0.14% 83.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 400 0.44% 83.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 128 0.14% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 135 0.15% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 65 0.07% 83.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 456 0.50% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 71 0.08% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 66 0.07% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 64 0.07% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 205 0.23% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 128 0.14% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 76 0.08% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 194 0.21% 85.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 386 0.43% 85.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 3 0.00% 85.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 73 0.08% 85.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 121 0.13% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 265 0.29% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 265 0.29% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 123 0.14% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 333 0.37% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 195 0.22% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 2 0.00% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 125 0.14% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 265 0.29% 87.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 256 0.28% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 5 0.01% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 65 0.07% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 452 0.50% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 7 0.01% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 192 0.21% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 259 0.29% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 3 0.00% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 192 0.21% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 9 0.01% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 452 0.50% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 64 0.07% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 5 0.01% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 255 0.28% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 264 0.29% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 126 0.14% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 3 0.00% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 194 0.21% 90.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 335 0.37% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 123 0.14% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 264 0.29% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 264 0.29% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 120 0.13% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 72 0.08% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 4 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 385 0.43% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 194 0.21% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 76 0.08% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 128 0.14% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 209 0.23% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 65 0.07% 93.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::47616-47623 67 0.07% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 129 0.14% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 390 0.43% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 67 0.07% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 131 0.15% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5359 5.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90271 # Bytes accessed per row activation -system.physmem.totQLat 377292466250 # Total ticks spent queuing -system.physmem.totMemAccLat 474547986250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454375000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18801145000 # Total ticks spent accessing banks -system.physmem.avgQLat 24045.34 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1198.22 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 73 0.08% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 459 0.51% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 3 0.00% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 69 0.08% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48448-48455 1 0.00% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 129 0.14% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 129 0.14% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5220 5.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90454 # Bytes accessed per row activation +system.physmem.totQLat 377144928750 # Total ticks spent queuing +system.physmem.totMemAccLat 474552728750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454360000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18953440000 # Total ticks spent accessing banks +system.physmem.avgQLat 24035.94 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1207.93 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30243.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30243.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage @@ -489,268 +502,256 @@ system.physmem.busUtilRead 2.98 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing -system.physmem.readRowHits 15616441 # Number of row buffer hits during reads -system.physmem.writeRowHits 91020 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.18 # Row buffer hit rate for writes -system.physmem.avgGap 159454.26 # Average gap between requests +system.physmem.readRowHits 15616330 # Number of row buffer hits during reads +system.physmem.writeRowHits 90931 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.11 # Row buffer hit rate for writes +system.physmem.avgGap 159351.16 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54391586 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743633 # Transaction distribution -system.membus.trans_dist::ReadResp 16743633 # Transaction distribution -system.membus.trans_dist::WriteReq 763392 # Transaction distribution -system.membus.trans_dist::WriteResp 763392 # Transaction distribution -system.membus.trans_dist::Writeback 57664 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution -system.membus.trans_dist::ReadExReq 131346 # Transaction distribution -system.membus.trans_dist::ReadExResp 131346 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.physmem.prechargeAllPercent 2.39 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54426353 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743636 # Transaction distribution +system.membus.trans_dist::ReadResp 16743636 # Transaction distribution +system.membus.trans_dist::WriteReq 763424 # Transaction distribution +system.membus.trans_dist::WriteResp 763424 # Transaction distribution +system.membus.trans_dist::Writeback 57656 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4518 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4518 # Transaction distribution +system.membus.trans_dist::ReadExReq 131342 # Transaction distribution +system.membus.trans_dist::ReadExResp 131342 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892518 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279376 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892570 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279432 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343440 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35343496 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18870589 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471520 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18869661 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143126845 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143126845 # Total data (bytes) +system.membus.tot_pkt_size::total 143125917 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143125917 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1220589500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225680000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3747000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3756000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18118484000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171618500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4951896724 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4990533473 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35075499000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35075577250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 62057 # number of replacements -system.l2c.tags.tagsinuse 51615.015118 # Cycle average of tags in use -system.l2c.tags.total_refs 1699237 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127445 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.333101 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2576505750500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38217.986822 # Average occupied blocks per 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-system.l2c.overall_mshr_miss_latency::total 9026599130 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 370327500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4084996355 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9015282635 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343871250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83402251750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83755912750 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 842500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83269942750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167016908250 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8431436509 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8268193000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16699629509 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82922372500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167022999000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8435630009 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8264647000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16700277009 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343871250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91833688259 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92191542759 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 842500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91538135750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183716537759 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027723 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026053 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016492 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989921 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992126 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991074 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.550367 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.523590 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537231 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.237249 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.218716 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101836 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.237249 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.218716 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101836 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91187019500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183723276009 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010184 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028343 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014479 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025409 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016487 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990483 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991575 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991062 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543948 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.530386 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537263 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010184 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.234426 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014479 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.221499 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101827 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010184 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.234426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014479 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.221499 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101827 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61802.163093 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61683.277185 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63889.532561 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60684.612984 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63871.851321 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60487.476586 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58415.657469 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58335.455393 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58377.311545 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58336.694106 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58312.496793 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58324.919986 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58579.590165 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58702.597502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58617.684463 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58579.590165 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58702.597502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58617.684463 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -902,45 +903,45 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52751818 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471631 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471631 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596380 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2913 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2913 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247521 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247521 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725079 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753474 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20108 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50543 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549204 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54752376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83781573 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79692 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138642313 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138642313 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 169620 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808134500 # Layer occupancy (ticks) +system.toL2Bus.throughput 52790683 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471881 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471881 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763424 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763424 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596450 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2909 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2909 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247508 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247508 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725145 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753790 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20211 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50526 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549672 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54754616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83791781 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28748 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138654661 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138654661 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 169908 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808598000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865505750 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865648250 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420696776 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4421117527 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12940000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13024000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30620250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30647250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48128720 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715358 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715358 # Transaction distribution +system.iobus.throughput 48159799 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution system.iobus.trans_dist::WriteResp 8167 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -962,12 +963,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -989,14 +990,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646645 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646645 # Total data (bytes) +system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646653 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1042,141 +1043,141 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374819000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42584048000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42583673750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7352406 # DTB read hits -system.cpu0.dtb.read_misses 6766 # DTB read misses -system.cpu0.dtb.write_hits 5599485 # DTB write hits -system.cpu0.dtb.write_misses 1847 # DTB write misses -system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7421376 # DTB read hits +system.cpu0.dtb.read_misses 6854 # DTB read misses +system.cpu0.dtb.write_hits 5628030 # DTB write hits +system.cpu0.dtb.write_misses 1815 # DTB write misses +system.cpu0.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6337 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 131 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 151 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7359172 # DTB read accesses -system.cpu0.dtb.write_accesses 5601332 # DTB write accesses +system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7428230 # DTB read accesses +system.cpu0.dtb.write_accesses 5629845 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12951891 # DTB hits -system.cpu0.dtb.misses 8613 # DTB misses -system.cpu0.dtb.accesses 12960504 # DTB accesses -system.cpu0.itb.inst_hits 30170189 # ITB inst hits -system.cpu0.itb.inst_misses 3579 # ITB inst misses +system.cpu0.dtb.hits 13049406 # DTB hits +system.cpu0.dtb.misses 8669 # DTB misses +system.cpu0.dtb.accesses 13058075 # DTB accesses +system.cpu0.itb.inst_hits 30610107 # ITB inst hits +system.cpu0.itb.inst_misses 3562 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2748 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30173768 # ITB inst accesses -system.cpu0.itb.hits 30170189 # DTB hits -system.cpu0.itb.misses 3579 # DTB misses -system.cpu0.itb.accesses 30173768 # DTB accesses -system.cpu0.numCycles 2629696361 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30613669 # ITB inst accesses +system.cpu0.itb.hits 30610107 # DTB hits +system.cpu0.itb.misses 3562 # DTB misses +system.cpu0.itb.accesses 30613669 # DTB accesses +system.cpu0.numCycles 2628235952 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29597158 # Number of instructions committed -system.cpu0.committedOps 37762240 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33970200 # Number of integer alu accesses +system.cpu0.committedInsts 29990580 # Number of instructions committed +system.cpu0.committedOps 38158663 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34282971 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4584 # Number of float alu accesses -system.cpu0.num_func_calls 1050225 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3920547 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33970200 # number of integer instructions +system.cpu0.num_func_calls 1059870 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3968282 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34282971 # number of integer instructions system.cpu0.num_fp_insts 4584 # number of float instructions -system.cpu0.num_int_register_reads 194623734 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36521551 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3225 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1362 # number of times the floating registers were written -system.cpu0.num_mem_refs 13522491 # number of memory refs -system.cpu0.num_load_insts 7673972 # Number of load instructions -system.cpu0.num_store_insts 5848519 # Number of store instructions -system.cpu0.num_idle_cycles 2290697984.129271 # Number of idle cycles -system.cpu0.num_busy_cycles 338998376.870729 # Number of busy cycles -system.cpu0.not_idle_fraction 0.128912 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.871088 # Percentage of idle cycles +system.cpu0.num_int_register_reads 196555242 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36964020 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3346 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1240 # number of times the floating registers were written +system.cpu0.num_mem_refs 13622094 # number of memory refs +system.cpu0.num_load_insts 7743834 # Number of load instructions +system.cpu0.num_store_insts 5878260 # Number of store instructions +system.cpu0.num_idle_cycles 2282805163.828333 # Number of idle cycles +system.cpu0.num_busy_cycles 345430788.171666 # Number of busy cycles +system.cpu0.not_idle_fraction 0.131431 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.868569 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856199 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.856725 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60648231 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856711 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.791937 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 20135568250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 208.641443 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 302.215282 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.407503 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.590264 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997767 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29750188 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30898043 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60648231 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29750188 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30898043 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60648231 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29750188 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30898043 # number of overall hits -system.cpu0.icache.overall_hits::total 60648231 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 420001 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 436711 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856712 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 420001 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 436711 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856712 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 420001 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 436711 # number of overall misses -system.cpu0.icache.overall_misses::total 856712 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5711192500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6097938000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11809130500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5711192500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6097938000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11809130500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5711192500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6097938000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11809130500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30170189 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 31334754 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61504943 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30170189 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 31334754 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61504943 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30170189 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 31334754 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61504943 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013921 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013937 # miss rate for ReadReq accesses +system.cpu0.icache.tags.replacements 856230 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.853093 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60649685 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856742 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.791072 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 20173406250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 217.243034 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 293.610060 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.424303 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.573457 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997760 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 30192721 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30456964 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60649685 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30192721 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30456964 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60649685 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30192721 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30456964 # number of overall hits +system.cpu0.icache.overall_hits::total 60649685 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 417386 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 439357 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 856743 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 417386 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 439357 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 856743 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 417386 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 439357 # number of overall misses +system.cpu0.icache.overall_misses::total 856743 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5696153000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6111476500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11807629500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5696153000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6111476500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11807629500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5696153000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6111476500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11807629500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30610107 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 30896321 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61506428 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30610107 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 30896321 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61506428 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30610107 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 30896321 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61506428 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013636 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014220 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013921 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013937 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013636 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014220 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013921 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013937 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013636 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014220 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.045005 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13963.325861 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13784.247799 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13784.247799 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13784.247799 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13647.206662 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.046955 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.997052 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13647.206662 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.046955 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13781.997052 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13647.206662 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.046955 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13781.997052 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,48 +1186,48 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 420001 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 436711 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856712 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 420001 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 436711 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856712 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 420001 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 436711 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 856712 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869726500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5221934000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10091660500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869726500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5221934000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10091660500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869726500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5221934000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10091660500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 417386 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 439357 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 856743 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 417386 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 439357 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 856743 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 417386 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 439357 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 856743 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4859799000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5230292500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10090091500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4859799000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5230292500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10090091500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4859799000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5230292500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10090091500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 435321250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1072000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1072500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 435321250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1072000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for ReadReq accesses +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1072500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013636 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014220 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013636 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014220 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.013929 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013636 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014220 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013929 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11779.525091 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11779.525091 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11779.525091 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11643.416406 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11904.425103 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11777.267512 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11643.416406 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11904.425103 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11777.267512 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11643.416406 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11904.425103 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11777.267512 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1234,113 +1235,113 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627593 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.877442 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23660330 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628105 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.669386 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 627680 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.877363 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23660930 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628192 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.665125 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.884282 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 328.993161 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.357196 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642565 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6452957 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6745780 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13198737 # number of ReadReq hits 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(read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11417305 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11756165 # number of overall hits -system.cpu0.dcache.overall_hits::total 23173470 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 182326 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 186686 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 369012 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 127483 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 122951 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250434 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6110 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5462 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11572 # number of LoadLockedReq misses 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cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6635283 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6932466 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13567749 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5091831 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5133336 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10225167 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124634 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123126 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247760 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124634 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123125 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247759 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11727114 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12065802 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23792916 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11727114 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12065802 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23792916 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027478 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026929 # miss rate for ReadReq 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average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13859.726063 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 27325.781451 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 27325.781451 # average overall miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.794485 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.082879 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360927 # Average 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uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13259276491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12977158000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26236434491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104749071741 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103559950250 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208309021991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027230 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024775 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024203 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048296 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045152 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046732 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026037 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026037 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12929.815885 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.909276 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12845.432194 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44044.222537 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43181.702661 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43618.712915 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11484.125665 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12261.324825 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11857.522239 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1432,68 +1433,68 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7647205 # DTB read hits -system.cpu1.dtb.read_misses 7298 # DTB read misses -system.cpu1.dtb.write_hits 5633094 # DTB write hits -system.cpu1.dtb.write_misses 1843 # DTB write misses -system.cpu1.dtb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7578699 # DTB read hits +system.cpu1.dtb.read_misses 7251 # DTB read misses +system.cpu1.dtb.write_hits 5604812 # DTB write hits +system.cpu1.dtb.write_misses 1846 # DTB write misses +system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6730 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6708 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7654503 # DTB read accesses -system.cpu1.dtb.write_accesses 5634937 # DTB write accesses +system.cpu1.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7585950 # DTB read accesses +system.cpu1.dtb.write_accesses 5606658 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13280299 # DTB hits -system.cpu1.dtb.misses 9141 # DTB misses -system.cpu1.dtb.accesses 13289440 # DTB accesses -system.cpu1.itb.inst_hits 31334771 # ITB inst hits -system.cpu1.itb.inst_misses 3728 # ITB inst misses +system.cpu1.dtb.hits 13183511 # DTB hits +system.cpu1.dtb.misses 9097 # DTB misses +system.cpu1.dtb.accesses 13192608 # DTB accesses +system.cpu1.itb.inst_hits 30896338 # ITB inst hits +system.cpu1.itb.inst_misses 3789 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2858 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2857 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31338499 # ITB inst accesses -system.cpu1.itb.hits 31334771 # DTB hits -system.cpu1.itb.misses 3728 # DTB misses -system.cpu1.itb.accesses 31338499 # DTB accesses -system.cpu1.numCycles 2633133982 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30900127 # ITB inst accesses +system.cpu1.itb.hits 30896338 # DTB hits +system.cpu1.itb.misses 3789 # DTB misses +system.cpu1.itb.accesses 30900127 # DTB accesses +system.cpu1.numCycles 2631198481 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30613725 # Number of instructions committed -system.cpu1.committedOps 38855266 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34913201 # Number of integer alu accesses +system.cpu1.committedInsts 30221754 # Number of instructions committed +system.cpu1.committedOps 38460770 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34602143 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5685 # Number of float alu accesses -system.cpu1.num_func_calls 1090107 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4028756 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34913201 # number of integer instructions +system.cpu1.num_func_calls 1080538 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3981203 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34602143 # number of integer instructions system.cpu1.num_fp_insts 5685 # number of float instructions -system.cpu1.num_int_register_reads 200222637 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37674133 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4268 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written -system.cpu1.num_mem_refs 13877284 # number of memory refs -system.cpu1.num_load_insts 7989860 # Number of load instructions -system.cpu1.num_store_insts 5887424 # Number of store instructions -system.cpu1.num_idle_cycles 2288817928.029144 # Number of idle cycles -system.cpu1.num_busy_cycles 344316053.970855 # Number of busy cycles -system.cpu1.not_idle_fraction 0.130763 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.869237 # Percentage of idle cycles +system.cpu1.num_int_register_reads 198301383 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37233535 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4147 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1540 # number of times the floating registers were written +system.cpu1.num_mem_refs 13778426 # number of memory refs +system.cpu1.num_load_insts 7920474 # Number of load instructions +system.cpu1.num_store_insts 5857952 # Number of store instructions +system.cpu1.num_idle_cycles 2292395060.642381 # Number of idle cycles +system.cpu1.num_busy_cycles 338803420.357619 # Number of busy cycles +system.cpu1.not_idle_fraction 0.128764 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.871236 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1510,10 +1511,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1557205456000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1557205456000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1557221573750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1557221573750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |